99f35eab45
Use set operations instead of plain lists to enumerate register classes.
...
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
llvm-svn: 133105
2011-06-15 23:28:14 +00:00
5750ca7089
Remove custom allocation order boilerplate that is no longer needed.
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The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.
Some targets still use custom allocation orders:
ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.
X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.
SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.
llvm-svn: 132781
2011-06-09 16:56:59 +00:00
0713a9d8fc
Add a parameter to CCState so that it can access the MachineFunction.
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No functional change.
Part of PR6965
llvm-svn: 132763
2011-06-08 23:55:35 +00:00
60cdf8e727
Flag unallocatable register classes instead of giving them empty
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allocation orders.
llvm-svn: 132509
2011-06-02 23:07:24 +00:00
4dae7379ef
Fix 80 column violations.
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llvm-svn: 132341
2011-05-31 16:30:33 +00:00
2f14b0bb1d
Add XCore intrinsic for crc8.
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llvm-svn: 132340
2011-05-31 16:24:49 +00:00
542f9a2bcf
Add XCore intrinsic for crc32.
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llvm-svn: 132336
2011-05-31 14:47:36 +00:00
08600bcf65
Use the dwarf->llvm mapping to print register names in the cfi
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directives.
Fixes PR9826.
llvm-svn: 132317
2011-05-30 20:20:15 +00:00
fc9bae6f8b
Replace the -unwind-tables option with a per function flag. This is more
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LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.
llvm-svn: 132033
2011-05-25 03:44:17 +00:00
5de2375db8
Remove dead code.
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llvm-svn: 131974
2011-05-24 18:27:52 +00:00
2518f8376d
Make the logic for determining function alignment more explicit. No functionality change.
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llvm-svn: 131012
2011-05-06 20:34:06 +00:00
1a180156b6
Remove unused STL header includes.
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llvm-svn: 130068
2011-04-23 19:53:52 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
9a827b30ab
Add XCore intrinsics for initializing / starting / synchronizing threads.
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llvm-svn: 128633
2011-03-31 15:13:13 +00:00
6120962d7d
Add XCore intrinsic for setpsc.
...
llvm-svn: 127821
2011-03-17 18:42:05 +00:00
c871eff3f5
Add XCore intrinsics for setclk, setrdy.
...
llvm-svn: 127761
2011-03-16 21:56:00 +00:00
d4346f2388
Add checkevent intrinsic to check if any resources owned by the current thread
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can event.
llvm-svn: 127741
2011-03-16 18:34:00 +00:00
024932fc77
Don't indent cases in a switch, no functionality change.
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llvm-svn: 127681
2011-03-15 15:55:30 +00:00
5f1a26ea39
On the XCore the scavenging slot should be closest to the SP.
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llvm-svn: 127680
2011-03-15 15:10:11 +00:00
3a68eb150b
Add XCore intrinsics for getps, setps, setsr and clrsr.
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llvm-svn: 127678
2011-03-15 13:45:47 +00:00
b2c80da4ae
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
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llvm-svn: 126518
2011-02-25 21:41:48 +00:00
42f52e737e
Add XCore intrinsic for eeu instruction.
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llvm-svn: 126384
2011-02-24 13:39:18 +00:00
bfa5cc0e08
Add XCore intrinsic for clre instruction.
...
llvm-svn: 126322
2011-02-23 18:52:05 +00:00
4995b05f56
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
...
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
llvm-svn: 126320
2011-02-23 18:35:59 +00:00
2c610aa3ed
Add XCore intrinsic for the setv instruction.
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llvm-svn: 126315
2011-02-23 16:46:37 +00:00
12377e0947
Fix format for setc instruction.
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llvm-svn: 126314
2011-02-23 15:20:16 +00:00
aab96995f6
Add XCore intrinsic for settw instruction.
...
llvm-svn: 126313
2011-02-23 14:45:03 +00:00
1ae65c7cb8
Add XCore intrinsics for various instructions on ports.
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llvm-svn: 126132
2011-02-21 18:23:30 +00:00
ba1186c23e
Use explicit add_subdirectory's for LLVM target sublibraries instead
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of testing for its presence at cmake time.
This way the build automatically regenerates the makefiles when a svn
update brings in a new sublibrary.
llvm-svn: 126068
2011-02-20 02:55:27 +00:00
81c4306005
Swap VT and DebugLoc operands of getExtLoad() for consistency with
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other getNode() methods. Radar 9002173.
llvm-svn: 125665
2011-02-16 16:23:55 +00:00
d9dde78c27
Add intrinsic for setc instruction on the XCore.
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llvm-svn: 125186
2011-02-09 13:22:12 +00:00
a31b9c2f7c
Add XCore intrinsics for resource instructions.
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llvm-svn: 124794
2011-02-03 13:14:25 +00:00
8607a67d37
Add support for trampolines on the XCore.
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llvm-svn: 124722
2011-02-02 14:57:41 +00:00
0e7e34e476
Remove more duplicated code.
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llvm-svn: 124056
2011-01-23 04:43:11 +00:00
aea4958ea6
Remove duplicated code.
...
llvm-svn: 124054
2011-01-23 04:28:49 +00:00
bbb1a54b84
Fix a few more places that should use MBB::getLastNonDebugInstr().
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llvm-svn: 123408
2011-01-13 22:47:43 +00:00
441ae5b88c
Update CMake stuff
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llvm-svn: 123171
2011-01-10 12:39:23 +00:00
2f93128109
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
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llvm-svn: 123170
2011-01-10 12:39:04 +00:00
3ae2b79aa3
Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy
...
etc. takes an option OptSize. If OptSize is true, it would return
the inline limit for functions with attribute OptSize.
llvm-svn: 122952
2011-01-06 06:52:41 +00:00
2a0a3b43d7
Flag -> Glue, the ongoing saga
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llvm-svn: 122513
2010-12-23 18:28:41 +00:00
3e5fbd74ed
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
...
something that just glues two nodes together, even if it is
sometimes used for flags.
llvm-svn: 122310
2010-12-21 02:38:05 +00:00
7283b8d18c
Move more PEI-related hooks to TFI
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llvm-svn: 120229
2010-11-27 23:05:25 +00:00
d08fbd19f5
Move callee-saved regs spills / reloads to TFI
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llvm-svn: 120228
2010-11-27 23:05:03 +00:00
14ee344944
Move getInitialFrameState() to TargetFrameInfo
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llvm-svn: 119754
2010-11-18 23:25:52 +00:00
0eecf5d201
Move hasFP() and few related hooks to TargetFrameInfo.
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llvm-svn: 119740
2010-11-18 21:19:35 +00:00
f7183edb59
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
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llvm-svn: 119097
2010-11-15 00:06:54 +00:00
66031ed839
move all the target's asmprinters into the main target. The piece
...
that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.
llvm-svn: 119056
2010-11-14 18:43:56 +00:00
19fa38000a
Remove some explicit arguments to getELFSection. This is
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a leftover from the removal of isExplicit.
llvm-svn: 118774
2010-11-11 03:40:25 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
...
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
0e023ea02a
fix a long standing wart: all the ComplexPattern's were being
...
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
llvm-svn: 114471
2010-09-21 20:31:19 +00:00
Jakob Stoklund Olesen