Commit Graph

390 Commits

Author SHA1 Message Date
Anton Korobeynikov 59e2b8e894 Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
makes the code faster.

llvm-svn: 81220
2009-09-08 15:22:32 +00:00
Evan Cheng 7a37b1a2ca Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
llvm-svn: 80191
2009-08-27 01:23:50 +00:00
Chris Lattner e9a75a6654 rename TAI -> MAI, being careful not to make MAILJMP instructions :)
llvm-svn: 79777
2009-08-22 21:43:10 +00:00
Chris Lattner 7b26fce23e Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
llvm-svn: 79763
2009-08-22 20:48:53 +00:00
Devang Patel 0939595711 Record variable debug info at ISel time directly.
llvm-svn: 79742
2009-08-22 17:12:53 +00:00
Jim Grosbach 841850ed26 Add Thumb2 eh_sjlj_setjmp implementation
llvm-svn: 78701
2009-08-11 19:42:21 +00:00
Jim Grosbach 1d5350c08f fix GetInstSizeInBytes for eh_sjlj_setjmp
llvm-svn: 78683
2009-08-11 17:08:15 +00:00
Jim Grosbach f24f9d9cb6 Whitespace cleanup. Remove trailing whitespace.
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
Evan Cheng 092b701a2c Add support for folding loads / stores into 16-bit moves used by Thumb2.
llvm-svn: 78558
2009-08-10 06:32:05 +00:00
Evan Cheng 55c014a9f3 80 col violation.
llvm-svn: 78557
2009-08-10 05:51:48 +00:00
Anton Korobeynikov 887d05ce9b Use VLDM / VSTM to spill/reload 128-bit Neon registers
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
Evan Cheng 2aa91cc2be Code refactoring. No functionality change.
llvm-svn: 78455
2009-08-08 03:20:32 +00:00
Evan Cheng 4c3b1ca5a0 Fix support to use NEON for single precision fp math.
llvm-svn: 78397
2009-08-07 19:30:41 +00:00
Evan Cheng b972e5633f It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
2009-08-07 00:34:42 +00:00
David Goodwin e5b5d8fbb3 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
llvm-svn: 78244
2009-08-05 21:02:22 +00:00
Chris Lattner e98a3c3ca3 Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.

The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain.  It should be removed 
IMNSHO, but I'll leave that to ARMish folks to decide.

llvm-svn: 77877
2009-08-02 05:20:37 +00:00
Evan Cheng e64f48ba8b Workaround a couple of Darwin assembler bugs.
llvm-svn: 77781
2009-08-01 06:13:52 +00:00
Evan Cheng 95d6325859 t2BR_JT is mov pc, it's 2 byte long, not 4.
llvm-svn: 77744
2009-07-31 22:22:22 +00:00
Evan Cheng f6d0fa3d33 - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.

llvm-svn: 77701
2009-07-31 18:28:05 +00:00
Evan Cheng 780748d565 - More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
2009-07-28 05:48:47 +00:00
Evan Cheng 0e075e2429 convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).
llvm-svn: 77230
2009-07-27 18:44:00 +00:00
Evan Cheng 8f2ed1bc5a Clean up.
llvm-svn: 77221
2009-07-27 18:25:24 +00:00
Evan Cheng 056c669e93 Get rid of some more getOpcode calls.
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.

llvm-svn: 77218
2009-07-27 18:20:05 +00:00
Evan Cheng 371ec9e810 If CPSR is modified but the def is dead, then it's ok to fold the load / store.
llvm-svn: 77182
2009-07-27 04:18:04 +00:00
Evan Cheng c47e109335 Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
llvm-svn: 77181
2009-07-27 03:14:20 +00:00
Evan Cheng 186332f898 Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
llvm-svn: 77175
2009-07-27 00:33:08 +00:00
Evan Cheng 0e5b149930 Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
llvm-svn: 77174
2009-07-27 00:24:36 +00:00
Evan Cheng 26b51b15ed Just use a single isMoveInstr to catch all the cases.
llvm-svn: 77173
2009-07-27 00:05:15 +00:00
Evan Cheng f3a1fce8ae Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
2009-07-25 00:33:29 +00:00
Evan Cheng 666c912ce3 Make sure thumb2 jumptable entries are aligned.
llvm-svn: 76986
2009-07-24 18:20:44 +00:00
Eli Friedman 95fc6ee51a Remove unused member functions.
llvm-svn: 76960
2009-07-24 07:43:59 +00:00
Evan Cheng 6cfbe61361 FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
llvm-svn: 76925
2009-07-24 00:53:56 +00:00
David Goodwin cdd405d804 Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
llvm-svn: 76919
2009-07-24 00:16:18 +00:00
Anton Korobeynikov c5df7e2dc1 Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.

llvm-svn: 76124
2009-07-16 23:26:06 +00:00
Torok Edwin fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Torok Edwin 56d0659726 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379
2009-07-11 20:10:48 +00:00
Evan Cheng bf041366c4 80 col violation.
llvm-svn: 75358
2009-07-11 06:37:27 +00:00
Evan Cheng 3b88dd6900 Move isPredicated from .cpp to .h
llvm-svn: 75217
2009-07-10 01:38:27 +00:00
Evan Cheng e3a53c448b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
David Goodwin af7451b674 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
llvm-svn: 75010
2009-07-08 16:09:28 +00:00