Commit Graph

429554 Commits

Author SHA1 Message Date
Daniil Fukalov 77d97be0aa [NFC] Fix cvt_f32_ubyte.ll test.
Remove (unintended) infinite loop in the test.

Reviewed By: vangthao

Differential Revision: https://reviews.llvm.org/D129328
2022-07-08 21:19:21 +03:00
Cole Kissane ea61750c35 [NFC] Refactor llvm::zlib namespace
* Refactor compression namespaces across the project, making way for a possible
  introduction of alternatives to zlib compression.
  Changes are as follows:
  * Relocate the `llvm::zlib` namespace to `llvm::compression::zlib`.

Reviewed By: MaskRay, leonardchan, phosek

Differential Revision: https://reviews.llvm.org/D128953
2022-07-08 11:19:07 -07:00
tlattner eb1ffd817c Update references to Discourse instead of the mailing lists.
Update the references to the old Mailman mailing lists to point to Discourse forums.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D128766
2022-07-08 11:16:47 -07:00
Nicolai Hähnle 5a731d733c Fix test: LLVMGetBitcodeModule takes ownership of memory buffer
Clarify this behavior in the C interface header file and fix a related
bug in a test.

Differential Revision: https://reviews.llvm.org/D129113
2022-07-08 20:06:44 +02:00
Iain Sandoe bc2a6defc8 [C++20][Modules] Allow for redeclarations in partitions.
The existing provision is not sufficient, it did not allow for the cases
where an implementation partition includes the primary module interface,
or for the case that an exported interface partition is contains a decl
that is then implemented in a regular implementation unit.

It is somewhat unfortunate that we have to compare top level module names
to achieve this, since built modules are not necessarily available.

TODO: It might be useful to cache a hash of the primary module name if
this test proves to be a  significant load.

Differential Revision: https://reviews.llvm.org/D127624
2022-07-08 19:02:59 +01:00
Ryan Thomas Lynch (@emosy) f192392299 [vscode-mlir] add tablegen <> bracket colorization
Add support for colorizing angle brackets "<>" in TableGen files.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D128229
2022-07-08 10:58:38 -07:00
Jacques Pienaar e08a991f56 [mlir][tosa] Enable decomposing Conv2D also where 1 input dim is dynamic
Restricted to just 1 dynamic input dim as that worked all the way through to
codegen.

Differential Revision: https://reviews.llvm.org/D129334
2022-07-08 10:57:04 -07:00
Philip Reames b12930e133 [RISCV] Switch to using get.active.lane.mask when tail folding
The motivation here is to a) bring us closer into alignment with AArch64 under the assumption that codepath is better tested, and b) simplify pattern matching in an upcoming change.

The immediate impact is a significant IR reduction but a fairly minimal change in the generated assembly. Due to a difference in expansion behavior we get a saturating add vs an unsaturating one for the old code, but that's about it. This difference comes down to different handling of overflow, which doesn't seem to be possible here anyways, so the assembly codegen is arguably a minor regression. I don't expect that to matter in practice.

Differential Revision: https://reviews.llvm.org/D129221
2022-07-08 10:24:59 -07:00
Craig Topper 92f1794d41 [RISCV] Mark fminnum_vl and fmaxnum_vl as commutable. 2022-07-08 10:19:09 -07:00
Craig Topper 069ba96660 [RISCV] Add commuted fixed vector vfmax.vf and vfmin.vf tests. NFC
The ISD opcodes aren't marked commutable so we don't match these
properly.
2022-07-08 10:19:09 -07:00
Philip Reames 264018d764 [RISCV] Mark vsadd(u)_vl as commutable
This allows fixed length vectors involving splats on the LHS to commute into the _vx form of the instruction. Oddly, the generic canonicalization rules appear to catch the scalable vector cases. I haven't fully dug in to understand why, but I suspect it's because of a difference in how we represent splats (splat_vector vs build_vector).

Differential Revision: https://reviews.llvm.org/D129302
2022-07-08 10:18:21 -07:00
Alexander Yermolovich a84e1e6c0d [DWARF] Add linkagename to hash
Originally encountered with RUST, but also there are cases with distributed LTO
where debug info dwo units contain structurally the same debug information, with
difference in DW_AT_linkage_name. This causes collision on DWO ID.

Differential Revision: https://reviews.llvm.org/D129317
2022-07-08 10:15:25 -07:00
Nandor Licker f92d319c70 [mlir] Fixed double-free bug in SymbolUserMap
`SymbolUserMap` relied on `try_emplace` and `std::move` to relocate an entry to another key.  However, if this triggered the resizing of the `DenseMap`, the value was destroyed before it could be moved to the new storage location, leading to a dangling `users` reference to be inserted into the map. On destruction, since a new entry was created from one that was already freed, a double-free error occurred.

Fixed issue by re-fetching the iterator after the mutation of the container.

Differential Revision: https://reviews.llvm.org/D129345
2022-07-08 20:06:35 +03:00
Craig Topper a246eb6814 [RISCV] Mark (s/u)min_vl and (s/u)max_vl as commutable. 2022-07-08 09:59:42 -07:00
Craig Topper cd783bf997 [RISCV] Add fixed vector vmin(u).vx and vmax(u).vx tests. NFC 2022-07-08 09:59:41 -07:00
Simon Pilgrim 6fede5e06c [X86] Regenerate vec_shift6.ll to remove superfluous whitespace. NFC 2022-07-08 17:59:10 +01:00
Arthur Eubanks 095a493cea [gn build] Manually port d2ead9e3 2022-07-08 09:49:21 -07:00
Slava Zakharin 73026a4fbf [flang] Changed lowering for allocatable assignment to make array-value-copy correct.
Array-value-copy fails to generate a temporary array for case like this:
subroutine bug(b)
  real, allocatable :: b(:)
  b = b(2:1:-1)
end subroutine

Since LHS may need to be reallocated, lowering produces the following FIR:
%rhs_load = fir.array_load %b %slice

%lhs_mem = fir.if %b_is_allocated_with_right_shape {
   fir.result %b
} else {
   %new_storage = fir.allocmem %rhs_shape
   fir.result %new_storage
}

%lhs = fir.array_load %lhs_mem
%loop = fir.do_loop {
 ....
}
fir.array_merge_store %lhs, %loop to %lhs_mem
// deallocate old storage if reallocation occured,
// and update b descriptor if needed.

Since %b in array_load and %lhs_mem in array_merge_store are not the same SSA
values, array-value-copy does not detect the conflict and does not produce
a temporary array. This causes incorrect result in runtime.

The suggested change in lowering is to generate this:
%rhs_load = fir.array_load %b %slice
%lhs_mem = fir.if %b_is_allocated_with_right_shape {
   %lhs = fir.array_load %b
   %loop = fir.do_loop {
      ....
   }
   fir.array_merge_store %lhs, %loop to %b
   fir.result %b
} else {
   %new_storage = fir.allocmem %rhs_shape
   %lhs = fir.array_load %new_storage
   %loop = fir.do_loop {
      ....
   }
   fir.array_merge_store %lhs, %loop to %new_storage
   fir.result %new_storage
}
// deallocate old storage if reallocation occured,
// and update b descriptor if needed.

Note that there are actually 3 branches in FIR, so the assignment loops
are currently produced in three copies, which is a code-size issue.
It is possible to generate just two branches with two copies of the loops,
but it is not addressed in this change-set.

Differential Revision: https://reviews.llvm.org/D129314
2022-07-08 09:41:34 -07:00
Florian Hahn 0c27b38849
[VPlan] Move VPWidenSelectRecipe::execute to VPlanRecipes.cpp (NFC).
Depends on D127968.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D127970
2022-07-08 09:35:23 -07:00
Nikolas Klauser b48c5010a4 [libc++] Make parameter names consistent and enforce the naming style using readability-identifier-naming
Ensure that parameter names have the style `__lower_case`

Reviewed By: ldionne, #libc

Spies: aheejin, sstefan1, libcxx-commits, miyuki

Differential Revision: https://reviews.llvm.org/D129051
2022-07-08 18:17:47 +02:00
Matt Arsenault 02769f2b3f AArch64/GlobalISel: Stop using legal s1 values
As far as I can tell treating s1 values as legal makes no sense. There
are no allocatable 1-bit registers. SelectionDAG legalizes the usual
set of boolean operations to 32-bits, and this should do the
same. This avoids some special case handling in the selector of s1
values, and some extra code to look through truncates.

This makes some code worse at -O0, since nothing cleans up the and 1
the artifact combiner inserts. We could probably add some
non-essential combines or teach the artifact combiner to elide
intermediates betweeen boolean uses and defs.
2022-07-08 11:55:08 -04:00
Matt Arsenault 13ac4c3de9 GlobalISel: Add buildBoolExtInReg helper 2022-07-08 11:55:08 -04:00
Matt Arsenault e9a45d45d0 GlobalISel: Allow forming atomic/volatile G_SEXTLOAD
Mirror the change to G_ZEXTLOAD.
2022-07-08 11:55:08 -04:00
Matt Arsenault 1ee6ce9bad GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD
SelectionDAG has a target hook, getExtendForAtomicOps, which it uses
in the computeKnownBits implementation for ATOMIC_LOAD. This is pretty
ugly (as is having a separate load opcode for atomics), so instead
allow making use of atomic zextload. Enable this for AArch64 since the
DAG path defaults in to the zext behavior.

The tablegen changes are pretty ugly, but partially helps migrate
SelectionDAG from using ISD::ATOMIC_LOAD to regular ISD::LOAD with
atomic memory operands. For now the DAG emitter will emit matchers for
patterns which the DAG will not produce.

I'm still a bit confused by the intent of the isLoad/isStore/isAtomic
bits. The DAG implementation rejects trying to use any of these in
combination. For now I've opted to make the isLoad checks also check
isAtomic, although I think having isLoad and isAtomic set on these
makes most sense.
2022-07-08 11:55:08 -04:00
Joseph Huber 0d7161af89 [Clang] Fix test failing due to renamed arg 2022-07-08 11:50:56 -04:00
Nikita Popov d686ea32b1 [ConstantFolding] Guard against unfolded FP binop
Check that the operation actually folded before trying to flush
denormals. A minor variation of the pr33453 test exposed this
with the FP binops marked as undesirable.
2022-07-08 17:45:33 +02:00
Joseph Huber 74a8fce6e8 [LinkerWrapper] Fix save-temps and argument name
Summary:
The previous path reworked some handling of temporary files which
exposed some bugs related to capturing local state by reference in the
callback labmda. Squashing this by copying in everything instead. There
was also a problem where the argument name was changed for
`--bitcode-library=` but clang still used `--target-library=`.
2022-07-08 11:38:33 -04:00
Nikita Popov d287051404 [InstCombine] Avoid ConstantExpr::get() in vector binop fold (NFCI)
Use the ConstantFoldBinaryOpOperands() API instead. This case
would bail out on a non-folded result anyway.
2022-07-08 17:20:14 +02:00
Joseph Huber e0de264f63 [LinkerWrapper][NFC] Move error handling to a common function
Summary:
This patch merges all the error handling functions to a single function
call so we don't define the same lambda many times.
2022-07-08 11:18:38 -04:00
Joseph Huber d2ead9e324 [LinkerWrapper][NFC] Rework command line argument handling in the linker wrapper
Summary:
This patch reworks the command line argument handling in the linker
wrapper from using the LLVM `cl` interface to using the `Option`
interface with TableGen. This has several benefits compared to the old
method.

We use arguments from the linker arguments in the linker
wrapper, such as the libraries and input files, this allows us to
properly parse these. Additionally we can now easily set up aliases to
the linker wrapper arguments and pass them in the linker input directly.
That is, pass an option like `cuda-path=` as `--offload-arg=cuda-path=`
in the linker's inputs. This will allow us to handle offloading
compilation in the linker itself some day. Finally, this is also a much
cleaner interface for passing arguments to the individual device linking
jobs.
2022-07-08 11:18:38 -04:00
Nikita Popov 29c6bf45c3 [InstCombine] Avoid ConstantExpr::get() call
Avoid calling ConstantExpr::get() for associative/commutative
binops, call ConstantFoldBinaryOpOperands() instead. We only
want to perform the reassociation of the constants actually fold.
2022-07-08 17:13:06 +02:00
Simon Pilgrim b53046122f [DAG] SimplifyDemandedBits - fold AND(INSERT_SUBVECTOR(C,X,I),M) -> INSERT_SUBVECTOR(AND(C,M),X,I)
If all the demanded bits of the AND mask covering the inserted subvector 'X' are known to be one, then the mask isn't affecting the subvector at all.

In which case, if the base vector 'C' is undef/constant, then move the AND mask up to just (constant) fold it directly.

Addresses some of the regressions from D129150, particularly the cases where we're attempting to zero the upper elements of a widened vector.

Differential Revision: https://reviews.llvm.org/D129290
2022-07-08 16:08:31 +01:00
Ye Luo fca79b78c4 [libomptarget] compile DeviceRTL bc files with -O3
bc files of DeviceRTL are compiled with -O3, the same as the static library.

Differential Revision: https://reviews.llvm.org/D129344
2022-07-08 10:00:26 -05:00
Nikita Popov 8edb9c3c56 [ConstantExpr] Don't create float binop expressions
Mark the fadd, fsub, fmul, fdiv, and frem expressions as
undesirable, so they are not created automatically. This is in
preparation for their removal.
2022-07-08 16:53:46 +02:00
Nikita Popov fc18a88231 [InstCombine] Avoid creating float binop ConstantExprs
Replace ConstantExpr:getFAdd etc with call to
ConstantFoldBinaryOpOperands(). I'm using the constant folding API
rather than IRBuilder here to ensure that this does actually
constant fold. These transforms don't use m_ImmConstant(), so this
would not otherwise be guaranteed (and apparently, they can't use
m_ImmConstant because they want to handle scalable vector splats).

There is an opportunity here to further migrate these to the
ConstantFoldFPInstOperands() API, which would respect the denormal
mode. I've held off on doing so here, because some of this code
explicitly checks for denormal results, and I don't want to touch
it in a mostly NFC change.
2022-07-08 16:36:04 +02:00
Sanjay Patel 79bb915fb6 [InstCombine] enhance fold for subtract-from-constant -> xor
A low-bit mask is not required:
https://alive2.llvm.org/ce/z/yPShss

This matches the SDAG implementation that was updated at:
8b75671314
2022-07-08 10:02:19 -04:00
Sanjay Patel 0cf5d40d4c [InstCombine] add tests for masked sub; NFC 2022-07-08 10:02:19 -04:00
Valentin Clement 015834e455
[flang][openacc][NFC] Extract device_type parser to its own
Move the device_type parser to a separate parser AccDeviceTypeExprList. Preparatory work for D106968.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D106967
2022-07-08 16:02:04 +02:00
Valentin Clement 36e24da8eb
[flang][openacc][NFC] Make self clause value optional in ACC.td and extract the parser
Set the isOptional flag for the self clause. Move the optional and parenthesis part of the parser. Update the rest of the code to deal with the optional value.

Preparatory work for D106968.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D106965
2022-07-08 15:45:12 +02:00
Cullen Rhodes d1c51d45f0 [AArch64] Use Neoverse N2 sched model as default for:
- Cortex-A710
  - Cortex-X2
  - Neoverse-V1
  - Neoverse-512tvb

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D129203
2022-07-08 13:34:13 +00:00
Daniil Fukalov 6858a17f66 [LiveIntervals] Fix incorrect range (re)construction from subranges.
After D82916 `updateAllRanges()` started to fix holes in main range with
subranges but it fails on instructions with two subregs def which are parts of
one reg. The main range constructed with //all// subranges of subregs just after
processing the first operand. So the main range gets intervals from subranges
those are not updated yet.

The patch takes into account lane mask to update the main range.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D128553
2022-07-08 16:07:19 +03:00
LLVM GN Syncbot fad7d53a5f [gn build] Port 1cdec6c96e 2022-07-08 12:39:02 +00:00
Louis Dionne d2e86866be [libc++] Re-apply the use of ABI tags to provide per-TU insulation
This commit re-applies 9ee97ce3b8, which was reverted by 61d417ce
because it broke the LLDB data formatter tests. It also re-applies
6148c79a (the manual GN change associated to it).

Differential Revision: https://reviews.llvm.org/D127444
2022-07-08 08:38:36 -04:00
Phoebe Wang 8fb083d33e [X86][FP16] Add constrained FP support for scalar emulation
This is a follow up patch to support constrained FP in FP16 emulation.

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D128114
2022-07-08 20:33:42 +08:00
Hui Xie 1cdec6c96e [libcxx][ranges] implement `std::ranges::set_difference`
implement `std::ranges::set_difference`
reused classic std::set_difference
added unit tests

Differential Revision: https://reviews.llvm.org/D128983
2022-07-08 13:26:23 +01:00
Sanjay Patel 8b75671314 [SDAG] try to replace subtract-from-constant with xor
This is almost the same as the abandoned D48529, but it
allows splat vector constants too.

This replaces the x86-specific code that was added with
the alternate patch D48557 with the original generic
combine.

This transform is a less restricted form of an existing
InstCombine and the proposed SDAG equivalent for that
in D128080:
https://alive2.llvm.org/ce/z/OUm6N_

Differential Revision: https://reviews.llvm.org/D128123
2022-07-08 08:14:24 -04:00
Aaron Ballman fee77a2073 Disable clang-format entirely for test directories
See discussion here:

https://github.com/llvm/llvm-project/issues/55982

And the RFC here:
https://discourse.llvm.org/t/rfc-disable-clang-format-in-the-clang-test-tree/63498/2

We don't generally expect test files to be formatted according to the
style guide. Indeed, some tests may require specific formatting for the
purposes of the test.

When tests intentionally do not conform to the "correct" formatting,
this causes errors in the CI, which can drown out real errors and causes
people to stop trusting the CI over time.

From the history of the clang/test/.clang-format file, it looks as if
there have been attempts to make clang-format do a subset of formatting
that would be useful for tests. However, it looks as if it's hard to
make clang-format do exactly the right thing -- see the back-and-forth
between
13316a7
and
7b5bddf.

These changes disable the .clang-format file for clang/test, llvm/test,
and clang-tools-extra/test.

Fixes #55982
Differential Revision: https://reviews.llvm.org/D128706
2022-07-08 07:34:18 -04:00
Aaron Ballman 35f48572e3 Fix the Clang sphinx bot
This should resolve the issues with:
https://lab.llvm.org/buildbot/#/builders/92/builds/29439
2022-07-08 07:23:40 -04:00
OCHyams 6b62ca9043 [NFC][SelectionDAG] Fix debug prints in salvageUnresolvedDbgValue
The prints are printing pointer values - fix by dereferencing the pointers.
2022-07-08 12:09:30 +01:00
Nikita Popov 11541aa9fd [PhaseOrdering] Add test for IndVars + SROA interaction (NFC) 2022-07-08 13:04:24 +02:00