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15 Commits

Author SHA1 Message Date
Evan Cheng f3179567de Add operand cycles for vldr / vstr. 
llvm-svn: 115353
 2010-10-01 21:40:30 +00:00
Evan Cheng 2a5d764858 NEON scheduling info fix. vmov reg, reg are single cycle instructions. 
llvm-svn: 115344
 2010-10-01 20:50:58 +00:00
Evan Cheng 2fb20b1d37 ARM instruction itinerary fixes: 
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.

llvm-svn: 115121
 2010-09-30 01:08:25 +00:00
Evan Cheng 4a010fd1ea Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP 
pipeline forwarding path.

llvm-svn: 115098
 2010-09-29 22:42:35 +00:00
Evan Cheng 2259d67a33 Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. 
llvm-svn: 115010
 2010-09-29 00:49:25 +00:00
Evan Cheng c35d7bbe43 Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. 
llvm-svn: 115008
 2010-09-29 00:27:46 +00:00
Evan Cheng 0097dd0d5a Add support to model pipeline bypass / forwarding. 
llvm-svn: 115005
 2010-09-28 23:50:49 +00:00
Evan Cheng 8f9a2244fc Remove a unused instruction itinerary class. 
llvm-svn: 114782
 2010-09-25 01:06:02 +00:00
Evan Cheng 62d626ce86 Fix zero and sign extension instructions scheduling itineraries. 
llvm-svn: 114780
 2010-09-25 00:49:35 +00:00
Evan Cheng e37da03e60 More pseudo instruction scheduling itinerary fixes. 
llvm-svn: 114768
 2010-09-24 22:41:41 +00:00
Evan Cheng 1d35ad62cc Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions. 
llvm-svn: 114766
 2010-09-24 22:03:46 +00:00
Evan Cheng 722cd122dc Fix LDM_RET schedule itinery. 
llvm-svn: 113435
 2010-09-08 22:57:08 +00:00
Jim Grosbach 7ea5fc0794 minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. 
llvm-svn: 106988
 2010-06-28 04:27:01 +00:00
Anton Korobeynikov 7d62e33291 Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
 2010-04-18 20:31:01 +00:00
Anton Korobeynikov 090323aee5 Split A8/A9 itins - they already were too big. 
llvm-svn: 100672
 2010-04-07 18:22:11 +00:00