75ed9dcbc6
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146684
2011-12-15 21:34:44 +00:00
c44b5e469b
Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.
...
llvm-svn: 146671
2011-12-15 18:57:27 +00:00
9dd3f62b38
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
...
llvm-svn: 146664
2011-12-15 17:54:01 +00:00
275e874c67
Pass optLevel to XCoreDAGToDAGISel.
...
Patch by Kyriakos Georgiou.
llvm-svn: 146656
2011-12-15 15:18:35 +00:00
b7a0b89ff0
Use SmallVector/assign(), rather than std::vector/push_back().
...
llvm-svn: 146627
2011-12-15 01:16:09 +00:00
1940baa76b
Add support for lowering fneg when AVX is enabled.
...
rdar://10566486
llvm-svn: 146625
2011-12-15 01:02:25 +00:00
ae94fb4009
The saved registers weren't being processed in the correct order. This lead to
...
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.
llvm-svn: 146612
2011-12-14 23:53:24 +00:00
9efd7ebf0a
Consider CPE alignment in CreateNewWater().
...
An aligned constant pool entry may require extra alignment padding where
the new water is created. Take that into account when computing offset.
Also consider the alignment of other constant pool entries when
splitting a basic block. Alignment padding may make it necessary to
move the split point higher.
llvm-svn: 146609
2011-12-14 23:48:54 +00:00
da51104282
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
...
llvm-svn: 146608
2011-12-14 23:35:06 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
...
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
bb18fb4f52
ARM NEON fix alignment encoding for VST2 w/ writeback.
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Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
8e987f5e25
Nuke old code. Missed in last commit.
...
llvm-svn: 146590
2011-12-14 21:41:32 +00:00
88ac761aa4
ARM NEON refactor VST2 w/ writeback instructions.
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In addition to improving the representation, this adds support for assembly
parsing of these instructions.
llvm-svn: 146588
2011-12-14 21:32:11 +00:00
b7ec06c5c9
ARM NEON improve factoring a bit. No functional change.
...
llvm-svn: 146585
2011-12-14 20:59:15 +00:00
da103bf9ec
Model ARM predicated write as read-mod-write. e.g.
...
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
llvm-svn: 146583
2011-12-14 20:00:08 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
e5585e8fed
Fix speling and 80-col.
...
llvm-svn: 146575
2011-12-14 18:49:13 +00:00
bff84e1914
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
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emission is not supported yet, but a patch that adds the support should follow
soon.
llvm-svn: 146572
2011-12-14 18:26:41 +00:00
4288b9786f
Fix copy/pasto that skipped the 'modify' step.
...
llvm-svn: 146571
2011-12-14 18:12:37 +00:00
1bb6e066f6
ARM/Thumb2 mov vs. mvn alias goes both ways.
...
llvm-svn: 146570
2011-12-14 17:56:51 +00:00
ded6160473
VFP2 is required for FP loads. Noticed by inspection.
...
llvm-svn: 146569
2011-12-14 17:55:03 +00:00
fce28914ea
Tidy up.
...
llvm-svn: 146568
2011-12-14 17:32:02 +00:00
a342667fd0
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
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When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
a26979be29
Fix 80-column violation and extraneous brackets.
...
llvm-svn: 146566
2011-12-14 17:26:05 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
...
rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
7fae11b231
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
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to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
llvm-svn: 146542
2011-12-14 02:11:42 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
...
rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
6eb142a616
Thumb2 pre/post indexed stores can be from any non-PC GPR.
...
rdar://10549786
llvm-svn: 146518
2011-12-13 21:10:25 +00:00
5ac89675a0
Thumb2 tweak for ccout handling in RSB parsing.
...
llvm-svn: 146516
2011-12-13 21:06:41 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
...
rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
...
llvm-svn: 146514
2011-12-13 20:40:37 +00:00
561e4e18cf
ARM pre-UAL NEG mnemonic for convenience when porting old code.
...
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
2a2348e6c2
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146508
2011-12-13 20:13:48 +00:00
9227f39c53
ARM add more 'gas' compatibility aliases for NEON instructions.
...
llvm-svn: 146507
2011-12-13 20:08:32 +00:00
563de603f7
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
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load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
5e9d16cb53
Expand .cprestore directive to multiple instructions if the offset does not fit
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in a 16-bit field.
llvm-svn: 146469
2011-12-13 03:09:05 +00:00
637cc6a8aa
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
...
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
llvm-svn: 146466
2011-12-13 01:56:10 +00:00
bfa576fe8e
Account for CPE alignment when searching for new water.
...
Constant pool entries with different alignment may cause more alignment
padding to be inserted. Compute the amount of padding needed, and try to
pick the location that requires the least amount of padding.
Also take the extra padding into account when the water is above the
use.
llvm-svn: 146458
2011-12-13 00:44:30 +00:00
4ea3c8f54a
Target/Hexagon: Fix CMake build. We don't use add_llvm_library_dependencies().
...
llvm-svn: 146457
2011-12-13 00:36:04 +00:00
8889bb08b8
LLVMBuild: Introduce a common section which currently has a list of the
...
subdirectories to traverse into.
- Originally I wanted to avoid this and just autoscan, but this has one key
flaw in that new subdirectories can not automatically trigger a rerun of the
llvm-build tool. This is particularly a pain when switching back and forth
between trees where one has added a subdirectory, as the dependencies will
tend to be wrong. This will also eliminates FIXME implicitly.
llvm-svn: 146436
2011-12-12 22:45:54 +00:00
5d5e0d819d
Emit B (unconditional branch) when -relocation-model=pic and J (jump) when
...
-relocation-model=static.
llvm-svn: 146432
2011-12-12 22:39:35 +00:00
faa88c0add
Fix indentation.
...
llvm-svn: 146431
2011-12-12 22:38:19 +00:00
36e0519ca2
fix warning
...
llvm-svn: 146420
2011-12-12 21:52:59 +00:00
fadc2c83e5
Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
...
These modifiers simply select either the low or high D subregister of a Neon
Q register. I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.
llvm-svn: 146417
2011-12-12 21:45:15 +00:00
1213a7a57f
Hexagon backend support
...
llvm-svn: 146412
2011-12-12 21:14:40 +00:00
27a7489a03
LLVMBuild: Remove trailing newline, which irked me.
...
llvm-svn: 146409
2011-12-12 19:48:00 +00:00
7c0face455
XOP instructions and encoding tests.
...
llvm-svn: 146407
2011-12-12 19:37:49 +00:00
91a7bcbb9b
Add a postOffset() alignment argument.
...
This computes the offset of the layout sucessor block, considering its
alignment as well.
llvm-svn: 146401
2011-12-12 19:25:54 +00:00
0863de458d
Fix typo.
...
llvm-svn: 146400
2011-12-12 19:25:51 +00:00
6dd2488383
XOP encoding bits and logic.
...
llvm-svn: 146397
2011-12-12 19:12:26 +00:00
17c27a8898
Also set the proper alignment on inner islands and the function itself.
...
Downgrade the alignment of the initial constant island when constant
pool entries are moved elsewhere.
This is all gated by -arm-align-constant-islands.
llvm-svn: 146391
2011-12-12 18:45:45 +00:00
2a75997858
Make MF a class member instead of passing it around everywhere.
...
Also add an MCP member pointing to the machine constant pool.
No functional change intended.
llvm-svn: 146382
2011-12-12 18:16:53 +00:00
b5f52aad22
Add a -arm-align-constant-islands flag, default off.
...
Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment. When the command line
flag is set, also align the basic block containing the constant pool
entries.
This is only a partial implementation of constant island alignment. More
to come.
llvm-svn: 146375
2011-12-12 16:49:37 +00:00
1fdfec63a4
Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.
...
llvm-svn: 146344
2011-12-11 19:12:35 +00:00
4683740967
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
...
llvm-svn: 146341
2011-12-11 14:35:48 +00:00
64ba50a972
Mips: Don't create a dangling IR function just to get the address of a symbol.
...
llvm-svn: 146340
2011-12-11 12:21:34 +00:00
a6c59b8fc8
Also remove unnecessary includes from this file, which was supposed to be part
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of r146334!
llvm-svn: 146338
2011-12-11 00:45:13 +00:00
a461c1c069
Minimize #include's and forward-declares in Target.
...
llvm-svn: 146335
2011-12-10 22:35:47 +00:00
b9cda978ab
Refactor the implementation of the TargetOptions out of TargetMachine, taking
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the only parts of TM that depends on CodeGen headers with it.
llvm-svn: 146334
2011-12-10 22:34:41 +00:00
6641294e3b
Revert r146322 to appease buildbots. Original commit message:
...
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
llvm-svn: 146328
2011-12-10 19:55:03 +00:00
df0b779e9f
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
...
llvm-svn: 146322
2011-12-10 08:42:24 +00:00
67a7f18faf
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
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llvm-svn: 146318
2011-12-10 04:50:53 +00:00
146ac7b609
Try to align the point where a large basic block is split.
...
The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.
This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.
<rdar://problem/10550705>
There is still an issue with correctly packing differently aligned
entries in the island.
llvm-svn: 146314
2011-12-10 02:55:10 +00:00
b3734522fa
More debug output formatting.
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llvm-svn: 146313
2011-12-10 02:55:06 +00:00
c7f355b8e1
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
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does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
llvm-svn: 146311
2011-12-10 02:28:43 +00:00
54337b8617
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146300
2011-12-10 00:01:02 +00:00
4e36a934dc
Splats can contain undef's; make sure to handle them correctly. PR11526.
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llvm-svn: 146299
2011-12-09 23:54:42 +00:00
8be2f6577e
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146296
2011-12-09 23:34:09 +00:00
ef70e9b704
ARM allows '' syntax, not just '#imm' for assembly.
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Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
llvm-svn: 146285
2011-12-09 22:25:03 +00:00
6192b6570d
ARM assembly aliases for BIC<-->AND (immediate).
...
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
ea1b353e67
ARM NEON data type aliases for VBIC(register).
...
llvm-svn: 146281
2011-12-09 21:46:04 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
f85723626c
User a helper overload for a common pattern.
...
llvm-svn: 146270
2011-12-09 19:44:39 +00:00
8a4009dab2
Tidy up. Better base class factoring.
...
llvm-svn: 146267
2011-12-09 19:07:20 +00:00
b076e6f3d5
Tidy up. Better base class factoring.
...
llvm-svn: 146266
2011-12-09 18:54:11 +00:00
5f5fa12413
Tweak debugging output.
...
llvm-svn: 146264
2011-12-09 18:20:35 +00:00
863683c590
This is now implemented.
...
llvm-svn: 146258
2011-12-09 15:45:57 +00:00
16bbfbec66
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
...
llvm-svn: 146257
2011-12-09 15:44:03 +00:00
2dc5dec41d
X86: Split (v)rounds[sd] into a normal and an intrinsic version.
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llvm-svn: 146256
2011-12-09 15:43:55 +00:00
feb9f27de1
Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
...
llvm-svn: 146247
2011-12-09 06:41:08 +00:00
557cda7f1d
Remove hasSSE1orAVX(). It's the same as hasXMM().
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llvm-svn: 146246
2011-12-09 06:32:46 +00:00
5ee8464e48
Rename WrapperPIC. It is now used for both pic and static.
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llvm-svn: 146232
2011-12-09 01:53:17 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
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specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
8cc83fa1b7
ARM convenience aliases for VSQRT.
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llvm-svn: 146201
2011-12-08 22:51:25 +00:00
b96bca81e7
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
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llvm-svn: 146196
2011-12-08 22:30:45 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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llvm-svn: 146194
2011-12-08 22:19:04 +00:00
bb15fec2b8
Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
...
llvm-svn: 146193
2011-12-08 22:15:21 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
2a217be25f
Add various missing AVX patterns which was causing crashes. Sadly, the generated
...
code looks pretty bad compared to SSE.
rdar://10538793
llvm-svn: 146191
2011-12-08 22:05:28 +00:00
98bc797b4d
ARM asm parser, just issue a warning for a duplicate reg in a list.
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For better 'gas' compatibility.
llvm-svn: 146185
2011-12-08 21:34:20 +00:00
f10ee84956
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
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MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
llvm-svn: 146183
2011-12-08 21:05:38 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
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llvm-svn: 146182
2011-12-08 20:56:26 +00:00
57a7f41d5d
Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
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Fixes failures caused by r146171.
llvm-svn: 146180
2011-12-08 20:51:38 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
...
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
...
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
dee6c8275c
Implement 64-bit support for thread local storage handling.
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- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
llvm-svn: 146175
2011-12-08 20:34:32 +00:00
0b9b9da6c8
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
...
llvm-svn: 146171
2011-12-08 19:32:14 +00:00
4edc7360c7
ARM assembler support for register name aliases.
...
rdar://10550084
llvm-svn: 146170
2011-12-08 19:27:38 +00:00
4d1a2d449f
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
...
if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
llvm-svn: 146163
2011-12-08 19:00:42 +00:00
c09e4593b2
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
...
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
d19760a40c
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
...
llvm-svn: 146151
2011-12-08 14:43:19 +00:00
a4bcf27dae
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
...
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
528ff4bee0
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)
...
llvm-svn: 146137
2011-12-08 04:36:44 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
...
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
14e024dff7
Drop the HasInlineAsm flag.
...
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.
A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.
llvm-svn: 146124
2011-12-08 01:22:39 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
...
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
bd97f5d753
Simplify offset verification.
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llvm-svn: 146121
2011-12-08 01:10:05 +00:00
0dd1bc9c79
Fix copy/past-o.
...
llvm-svn: 146120
2011-12-08 01:02:26 +00:00
31a462c02c
ARM NEON two-operand aliases for VMUL.
...
llvm-svn: 146119
2011-12-08 00:59:47 +00:00
2a82333f54
Don't include alignment padding in BBInfo.Size.
...
Compute alignment padding before and after basic blocks dynamically.
Heed basic block alignment.
This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size. It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.
This makes the ARMConstantIslandPass aware of aligned basic blocks.
It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size. If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected. This could cause constant
pool entries to move out of range.
To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly. Normal
functions should be unaffected.
llvm-svn: 146118
2011-12-08 00:55:02 +00:00
9a6ba3c94e
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
...
llvm-svn: 146116
2011-12-08 00:52:55 +00:00
086d013e56
ARM VFP support 'flds/fldd' aliases for 'vldr'
...
llvm-svn: 146115
2011-12-08 00:49:29 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
...
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
4350c183d4
Modify class ReadHardware and add definition of 64-bit version of instruction
...
RDHWR.
llvm-svn: 146101
2011-12-07 23:31:26 +00:00
66232aa19d
Add newline.
...
llvm-svn: 146100
2011-12-07 23:26:03 +00:00
36d2198dae
Add 64-bit HWR29 register.
...
llvm-svn: 146099
2011-12-07 23:23:52 +00:00
9778e7a67c
32 to 64-bit anyext pattern.
...
llvm-svn: 146097
2011-12-07 23:21:19 +00:00
ae378af667
32 to 64-bit zext pattern.
...
llvm-svn: 146096
2011-12-07 23:14:41 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
...
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
...
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
...
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
56b70de01b
Variable cleanup. Based on past patch submittals variable names have
...
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.
llvm-svn: 146088
2011-12-07 22:35:30 +00:00
b2e05cb6b1
64-bit WrapperPICPat patterns.
...
llvm-svn: 146086
2011-12-07 22:11:43 +00:00
6820eebde1
Define base class for WrapperPICPat.
...
llvm-svn: 146081
2011-12-07 21:54:54 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
...
llvm-svn: 146080
2011-12-07 21:48:50 +00:00
4f864b78e6
Fix comment.
...
llvm-svn: 146063
2011-12-07 20:15:01 +00:00
d16e926a6b
Fix comment.
...
llvm-svn: 146062
2011-12-07 20:13:53 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
...
llvm-svn: 146059
2011-12-07 20:10:24 +00:00
d633c2f120
Nuke inadvertant debugging commit.
...
llvm-svn: 146057
2011-12-07 19:56:16 +00:00
d6ae4ba002
Darwin assembler improved relocs when w/o subsections_via_symbols.
...
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
2011-12-07 19:46:59 +00:00
18b0e5dca0
Thumb2 alias for long-form pop and friends.
...
rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
...
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
...
llvm-svn: 146039
2011-12-07 17:51:15 +00:00
1d578e8835
Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.
...
llvm-svn: 146031
2011-12-07 08:30:53 +00:00
302cf8d5d0
Adjust the stack by one pointer size for all frameless stacks.
...
llvm-svn: 146030
2011-12-07 07:58:55 +00:00
3c86459997
Fix off-by-one error when encoding the stack size for a frameless stack.
...
llvm-svn: 146029
2011-12-07 07:49:49 +00:00
7f8e563a69
Add bundle aware API for querying instruction properties and switch the code
...
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
llvm-svn: 146026
2011-12-07 07:15:52 +00:00
ac9df3d411
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
...
llvm-svn: 146024
2011-12-07 06:34:06 +00:00
16c744180d
make base register selection used in eliminateFrameIndex 64-bit clean
...
llvm-svn: 146023
2011-12-07 06:34:02 +00:00
abbc2529c1
set mayStore and mayLoad on CR pseudos
...
llvm-svn: 146022
2011-12-07 06:33:57 +00:00
2ba61e47a9
64-bit LR8 load should use X11 not R11
...
llvm-svn: 146021
2011-12-07 06:32:37 +00:00
2f0400b780
Eliminate delta argument from AdjustBBOffsetsAfter.
...
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
llvm-svn: 146018
2011-12-07 05:17:30 +00:00
97c857199e
Compute some alignment information for each basic block.
...
These fields are not used for anything yet.
llvm-svn: 146017
2011-12-07 04:17:35 +00:00
2cf294a213
ARM tidy up and remove no longer needed InstAlias definitions.
...
The TokenAlias handling of data type suffices renders these unnecessary.
llvm-svn: 146010
2011-12-07 01:50:36 +00:00
af748e1180
Move common expression into a method.
...
llvm-svn: 146008
2011-12-07 01:22:52 +00:00
585ce30b8b
ARM Implement ARM ARM Table A7-3 via TokenAlias.
...
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
llvm-svn: 146007
2011-12-07 01:17:58 +00:00
e2b3ff2a07
Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
...
No functional change is intended.
llvm-svn: 146005
2011-12-07 01:08:25 +00:00
d4b8249434
ARM: NEON SHLL instruction immediate operand range checking.
...
llvm-svn: 146003
2011-12-07 01:07:24 +00:00
61e6d987bf
Add a few moreLocal/Global R_MIPS_GOT related fixups and
...
make the addend fixup code a bit more generic
Patch by Jack Carter.
llvm-svn: 145998
2011-12-07 00:28:57 +00:00
47c24c2084
ARM: Parameterize the immediate operand type for NEON VSHLL.
...
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
llvm-svn: 145994
2011-12-07 00:02:17 +00:00
cc6bfa8e79
Revert r145971: "Use conservative size estimate for tBR_JTr."
...
This caused more offset errors.
llvm-svn: 145980
2011-12-06 22:41:31 +00:00
67a70c995a
Explicitly check for the different SUB instructions.
...
llvm-svn: 145976
2011-12-06 22:14:27 +00:00
2a81dd4a3c
First chunk of MachineInstr bundle support.
...
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
llvm-svn: 145975
2011-12-06 22:12:01 +00:00
33fe130e12
Use conservative size estimate for tBR_JTr.
...
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
llvm-svn: 145971
2011-12-06 21:55:39 +00:00
2fa7448f31
Remove alignment from deserted constant islands.
...
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.
This should fix the many Thumb1 assembler errors in the nightly test
suite.
The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.
<rdar://problem/10534709>
llvm-svn: 145970
2011-12-06 21:55:35 +00:00
5a173cd367
Encode the total stack if there isn't a frame.
...
llvm-svn: 145969
2011-12-06 21:34:01 +00:00
a73c0c99ea
* Add a macro to remove a magic number.
...
* Rename variables to reflect what they're actually used for.
llvm-svn: 145968
2011-12-06 21:23:42 +00:00
bde7f8ffe2
add RESTORE_CR and support CR unspills
...
llvm-svn: 145961
2011-12-06 20:55:36 +00:00
4ec02b02ac
remove old FIXME
...
llvm-svn: 145960
2011-12-06 20:52:56 +00:00
87571b6392
Check the correct value for small stack sizes. Also modify some comments.
...
llvm-svn: 145954
2011-12-06 19:16:17 +00:00
a4e87944a8
For a small sized stack, we encode that value directly with no "stack adjust" value.
...
llvm-svn: 145952
2011-12-06 19:09:06 +00:00
04424665c3
PTX: Continue to fix up the register mess.
...
llvm-svn: 145947
2011-12-06 17:39:48 +00:00
3063ac87aa
PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols
...
llvm-svn: 145946
2011-12-06 17:39:46 +00:00
83320e03e6
Add X86ISD::HADD/HSUB to getTargetNodeName
...
llvm-svn: 145929
2011-12-06 09:31:36 +00:00
6572e0f203
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
...
llvm-svn: 145927
2011-12-06 09:04:59 +00:00
8d4ba198d6
Merge floating point and integer UNPCK X86ISD node types.
...
llvm-svn: 145926
2011-12-06 08:21:25 +00:00
3cb802c775
Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs.
...
llvm-svn: 145924
2011-12-06 05:31:16 +00:00
e303e24d77
ARM mode 'mul' operand ordering tweak.
...
Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
5f143be8c5
Thumb2: MUL two-operand form encoding operand order fix.
...
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
llvm-svn: 145922
2011-12-06 05:03:45 +00:00
bf41eb3a98
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
...
llvm-svn: 145921
2011-12-06 04:59:07 +00:00
175c7d0da5
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
0c24d8a406
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
...
llvm-svn: 145912
2011-12-06 03:34:48 +00:00
1b1a122b4c
Add register HWR29 numbering. Patch by Jack Carter
...
llvm-svn: 145910
2011-12-06 03:34:36 +00:00
4e87e850a2
Add a comment.
...
llvm-svn: 145896
2011-12-06 01:57:48 +00:00
425e180ce8
Tidy up value checking.
...
llvm-svn: 145895
2011-12-06 01:53:17 +00:00
d3002490bf
MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.
...
llvm-svn: 145894
2011-12-06 01:48:32 +00:00
c77830d21e
[arm-fast-isel] Doublewords only require word-alignment.
...
rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
2e05db2fa0
Align ARM constant pool islands via their basic block.
...
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
llvm-svn: 145890
2011-12-06 01:43:02 +00:00
10e1252269
Use logarithmic units for basic block alignment.
...
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.
CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.
Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.
Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.
llvm-svn: 145889
2011-12-06 01:26:19 +00:00
f7cef7ecad
The compact encoding of the registers are 3-bits each. Make sure we shift the
...
value over that much.
llvm-svn: 145888
2011-12-06 01:26:14 +00:00
9105085b4a
Fix ARM handling of tBcc branch relaxation.
...
rdar://10069056
llvm-svn: 145885
2011-12-06 01:08:19 +00:00
2608157f79
Use an existing function.
...
llvm-svn: 145883
2011-12-06 00:51:12 +00:00
25b63fa117
Move target-specific logic out of generic MCAssembler.
...
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
llvm-svn: 145881
2011-12-06 00:47:03 +00:00
34a7c6dfd7
Simple branch relaxation for Thumb2 Bcc instructions.
...
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
llvm-svn: 145871
2011-12-05 23:45:46 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
...
llvm-svn: 145863
2011-12-05 22:27:04 +00:00
e489babf9b
Thumb2 prefer ADD register encoding T2 to T3 when possible.
...
rdar://10529664
llvm-svn: 145860
2011-12-05 22:16:39 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
...
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
9b8ac674bc
Split ExtIns into two base classes and have instructions EXT and INS derive from
...
them.
llvm-svn: 145852
2011-12-05 21:14:28 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
...
rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
...
O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
...
Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
9e90c5cde3
Fix previous commit. Oops.
...
llvm-svn: 145844
2011-12-05 20:12:26 +00:00
2b37e4fc80
Tidy up. No functional change.
...
llvm-svn: 145843
2011-12-05 20:09:44 +00:00
0a978ef715
ARM assmebler parsing for two-operand VMUL instructions.
...
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
llvm-svn: 145842
2011-12-05 19:55:46 +00:00
8f6834dfa5
enable PPC register scavenging by default (update tests and remove some FIXMEs)
...
llvm-svn: 145819
2011-12-05 17:55:17 +00:00
72a26e8b8d
don't include CR bit subregs in callee-saved list
...
llvm-svn: 145818
2011-12-05 17:55:12 +00:00
b544019a60
add register pressure for CR regs
...
llvm-svn: 145816
2011-12-05 17:54:17 +00:00
51bec1a37a
Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions.
...
llvm-svn: 145804
2011-12-05 07:27:14 +00:00
6a55b1dd9f
Clean up and optimizations to the X86 shuffle lowering code. No functional change.
...
llvm-svn: 145803
2011-12-05 06:56:46 +00:00
80381f6cbf
Fix 80-column issues.
...
llvm-svn: 145783
2011-12-04 00:52:23 +00:00
965e0c6de2
Emit the ctors in the proper order on ARM/EABI.
...
Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
6dae604f50
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
...
AnalyzeBranch doesn't change the successor, just the order.
llvm-svn: 145779
2011-12-03 21:24:48 +00:00
006e43bcc0
Check for stack space more intelligently.
...
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
llvm-svn: 145766
2011-12-03 09:32:07 +00:00
165ca1d4ba
Fix a bug in the x86-32 code generated for segmented stacks.
...
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
llvm-svn: 145765
2011-12-03 09:21:07 +00:00
8fd1254a0a
Creating multiple JITs on X86 in multiple threads causes multiple writes (of
...
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.
llvm-svn: 145745
2011-12-03 02:45:50 +00:00
ec3b77e00d
[arm-fast-isel] Unaligned stores of floats require special care.
...
rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
9dff9f4c41
ARM NEON VEXT aliases for data type suffices.
...
llvm-svn: 145726
2011-12-02 23:34:39 +00:00
2635f54cb6
ARM VEXT tighten up operand classes a bit.
...
llvm-svn: 145722
2011-12-02 22:57:57 +00:00
eb53822f5a
ARM VST1 single lane assembly parsing.
...
llvm-svn: 145718
2011-12-02 22:34:51 +00:00
50f02cb21b
Move global variables in TargetMachine into new TargetOptions class. As an API
...
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
dda976b804
ARM VLD1 single lane assembly parsing.
...
llvm-svn: 145712
2011-12-02 22:01:52 +00:00
81c9003695
ARM encoder method needs the physical register number, not the enum.
...
llvm-svn: 145711
2011-12-02 22:01:25 +00:00
9fd0e55e91
[arm-fast-isel] After promoting a function parameter be sure to update the
...
argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
1280eb1d06
Add XOP feature flag.
...
llvm-svn: 145682
2011-12-02 15:14:37 +00:00
b67440367f
Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions
...
llvm-svn: 145681
2011-12-02 08:18:41 +00:00
abeb79eee3
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
...
llvm-svn: 145680
2011-12-02 07:16:01 +00:00
f9ce7b60ef
remove unneeded FIXME comment
...
llvm-svn: 145679
2011-12-02 04:58:17 +00:00
58ca360081
update PPC 940 hazard rec. to function in postRA mode
...
llvm-svn: 145676
2011-12-02 04:58:02 +00:00
04945c42c6
ARM start parsing VLD1 single lane instructions.
...
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
f60485c4cf
Dummy commit to check commit access.
...
llvm-svn: 145619
2011-12-01 19:15:08 +00:00
676c093758
Add missing functions.
...
llvm-svn: 145608
2011-12-01 18:26:19 +00:00
10fe1fe39e
Add a few more functions to TargetLibraryInfo. More of rdar://10500969.
...
llvm-svn: 145596
2011-12-01 17:54:37 +00:00
9da7f305a4
For 64-bit the rest of the general regs are ok for the q constraint. Make
...
sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
llvm-svn: 145579
2011-12-01 08:12:41 +00:00
d61887dd0a
Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.
...
llvm-svn: 145573
2011-12-01 04:49:21 +00:00
c1870b2633
Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437.
...
llvm-svn: 145553
2011-12-01 01:43:47 +00:00
9430e284a9
Support for encoding all FMA4 instructions and tablegen patterns for all
...
remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
23c30b90e3
Remove unused variable
...
llvm-svn: 145517
2011-11-30 19:53:11 +00:00
a68c9a847e
ARM parsing for VLD1 all lanes, with writeback.
...
llvm-svn: 145510
2011-11-30 19:35:44 +00:00
738da252ab
Add a few functions to TargetLibraryInfo.
...
llvm-svn: 145508
2011-11-30 19:19:00 +00:00
3ecf976ca9
ARM parsing for VLD1 two register all lanes, no writeback.
...
llvm-svn: 145504
2011-11-30 18:21:25 +00:00
5feb3dab79
X86: Turns out bulldozer also supports sse42 and lzcnt.
...
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.
llvm-svn: 145494
2011-11-30 15:48:16 +00:00
981f32327d
X86: Add subtargets for AMD's bulldozer.
...
llvm-svn: 145493
2011-11-30 15:27:46 +00:00
96923cc2bb
X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).
...
llvm-svn: 145488
2011-11-30 10:13:37 +00:00
c4977ba413
Add instruction selection support for AVX2 horizontal add/sub instructions.
...
llvm-svn: 145487
2011-11-30 09:10:50 +00:00
0a672eaf9e
Merge VPERM2F128/VPERM2I128 ISD node types.
...
llvm-svn: 145485
2011-11-30 07:47:51 +00:00
bafd224c8b
Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
...
llvm-svn: 145483
2011-11-30 06:25:25 +00:00
abba0947db
Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional
...
change intended.
llvm-svn: 145468
2011-11-30 01:51:49 +00:00
cd6f5e757c
ARM parsing aliases for VLD1 single register all lanes.
...
llvm-svn: 145464
2011-11-30 01:09:44 +00:00
82e1bd8e94
Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable
...
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is
specified.
rdar://10466410
llvm-svn: 145460
2011-11-29 23:57:10 +00:00
182b6a077e
Tidy up a bit.
...
llvm-svn: 145458
2011-11-29 23:51:09 +00:00
ae672f8118
Add comment.
...
llvm-svn: 145456
2011-11-29 23:33:40 +00:00
e1154eef0b
ARM parsing aliases for data-size suffices on VST1.
...
llvm-svn: 145454
2011-11-29 23:21:31 +00:00
dc25f9f38a
Change names for MIPS "generic" processors defined in Mips.td to match what GNU
...
tools use. Patch by Simon Atanasyan.
"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"
llvm-svn: 145451
2011-11-29 23:08:41 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
...
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
648e48d02e
Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins.
...
llvm-svn: 145448
2011-11-29 22:48:34 +00:00
98d032fd67
ARM assembly parsing and encoding for three-register VST1.
...
llvm-svn: 145442
2011-11-29 22:38:04 +00:00
bde32d36bb
Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
...
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.
This also makes the AVX variants redundant.
llvm-svn: 145440
2011-11-29 22:27:25 +00:00
312b97c267
comment.
...
llvm-svn: 145422
2011-11-29 19:33:49 +00:00
539d0a8a09
build/CMake: Finish removal of add_llvm_library_dependencies.
...
llvm-svn: 145420
2011-11-29 19:25:30 +00:00
de3a2118db
MC/X86/COFF: Allow quotes in names when targeting MS/Windows,
...
as MC is the only assembler we support.
This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.
llvm-svn: 145409
2011-11-29 18:00:06 +00:00
7a81dea516
Fixed vsqrt.ss intrinsic usage - order of input operands was wrong.
...
Added a test.
Thanks Bruno for reviewing the patch.
llvm-svn: 145403
2011-11-29 15:00:45 +00:00
1d63ae3731
Fix shuffle decoding for memory forms for (V)SHUFPS/D.
...
llvm-svn: 145392
2011-11-29 07:58:09 +00:00
c16db840be
Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD.
...
llvm-svn: 145390
2011-11-29 07:49:05 +00:00
12b72def4e
Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled.
...
llvm-svn: 145376
2011-11-29 05:37:58 +00:00
897a7d4b9c
Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2.
...
llvm-svn: 145370
2011-11-29 03:57:34 +00:00
ae9132207f
Better fix for ARM MOVT relocation encoding of thumb bit.
...
Replaces r145318 with a more targetted fix for the relocation handling.
llvm-svn: 145346
2011-11-29 01:15:25 +00:00
aa93ceb164
Add missing avx pattern.
...
llvm-svn: 145272
2011-11-28 20:27:23 +00:00
12330650f8
Silence wrong warnings from GCC about variables possibly being used
...
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.
llvm-svn: 145239
2011-11-28 10:31:27 +00:00
818a983e93
Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar.
...
llvm-svn: 145238
2011-11-28 10:14:51 +00:00
b0456936da
Make isCommutedVSHUFP more like the way isCommutedSHUFP is handled.
...
llvm-svn: 145218
2011-11-28 01:14:24 +00:00
79ee88a511
Merge detecting and handling for VSHUFPSY and VSHUFPDY since a lot of the code was similar for both.
...
llvm-svn: 145199
2011-11-27 21:41:12 +00:00
97b3da5433
Add several new instructions supported by the latest MicroBlaze.
...
These instructions are not generated by the backend yet, this will come in a later commit.
llvm-svn: 145161
2011-11-27 05:16:58 +00:00
d2e2e1782f
Optimize comparison against 0 in conditional instructions.
...
Fix a couple of 80-column violations.
llvm-svn: 145159
2011-11-27 01:36:20 +00:00
7ba71be392
Move code into anonymous namespaces.
...
llvm-svn: 145154
2011-11-26 23:01:57 +00:00
51280d565b
Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created.
...
llvm-svn: 145153
2011-11-26 22:55:48 +00:00
69d5040485
Rename a couple of options and fix some simple typos.
...
llvm-svn: 145152
2011-11-26 21:50:38 +00:00
7704bd7ac3
Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type.
...
llvm-svn: 145148
2011-11-26 20:47:44 +00:00
0f9a1f5e6c
This patch contains support for encoding FMA4 instructions and
...
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
989eaf6e3f
ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.
...
llvm-svn: 145129
2011-11-25 09:19:57 +00:00
d65a444478
Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64.
...
llvm-svn: 145126
2011-11-24 22:57:10 +00:00
d26466748b
Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish.
...
llvm-svn: 145125
2011-11-24 22:20:08 +00:00
651db37352
X86: alias cqo to cqto.
...
llvm-svn: 145121
2011-11-24 12:02:46 +00:00
049e9e4d22
This patch makes the following changes necessary for MIPS' direct code emission.
...
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).
llvm-svn: 145113
2011-11-23 22:19:28 +00:00
f5ddf13f79
This patch addresses gp relative fixups/relocations for jump tables.
...
llvm-svn: 145112
2011-11-23 22:18:04 +00:00
ebcb451874
X86: Use btq for bit tests if the immediate can't be encoded in 32 bits.
...
Before:
movabsq $4294967296, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
testq %rax, %rdi ## encoding: [0x48,0x85,0xf8]
jne LBB0_2 ## encoding: [0x75,A]
After:
btq $32, %rdi ## encoding: [0x48,0x0f,0xba,0xe7,0x20]
jb LBB0_2 ## encoding: [0x72,A]
btq is usually slower than testq because it doesn't fuse with the jump, but here we're better off
saving one register and a giant movabsq.
llvm-svn: 145103
2011-11-23 13:54:17 +00:00
779ba6d7b7
I added several lines in X86 code generator that allow to choose
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VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.
The patch was reviewed by Bruno.
llvm-svn: 145099
2011-11-23 10:23:16 +00:00
02845410f9
Fix PR11422.
...
This was a bug in keeping track of the available domains when merging
domain values.
The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr
to the integer domain which is only available in AVX2.
Also add an assertion to catch future attempts at emitting AVX2
instructions.
llvm-svn: 145096
2011-11-23 04:03:08 +00:00
6f0ae783fe
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
...
llvm-svn: 145065
2011-11-22 16:21:04 +00:00
83c4592619
More fixes to the X86InstComments for shuffle instructions. In particular add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries.
...
llvm-svn: 145063
2011-11-22 14:27:57 +00:00
ccb7097509
Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms.
...
llvm-svn: 145055
2011-11-22 01:57:35 +00:00
f563977795
Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX.
...
llvm-svn: 145053
2011-11-22 00:44:41 +00:00
6270d072c5
Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled.
...
llvm-svn: 145028
2011-11-21 08:26:50 +00:00
669199ca94
Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled.
...
llvm-svn: 145026
2011-11-21 06:57:39 +00:00
a065238c6e
Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled.
...
llvm-svn: 145022
2011-11-21 01:12:36 +00:00
e79761df73
Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.
...
llvm-svn: 145005
2011-11-20 00:12:05 +00:00
a3a6583694
Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.
...
llvm-svn: 145004
2011-11-19 22:34:59 +00:00
bac86038ac
Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns.
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llvm-svn: 145003
2011-11-19 21:01:54 +00:00
3af6ae089f
Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns.
...
llvm-svn: 144999
2011-11-19 17:46:46 +00:00
f984efbfce
Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.
...
llvm-svn: 144989
2011-11-19 09:02:40 +00:00
81390be00f
Collapse X86 PSIGNB/PSIGNW/PSIGND node types.
...
llvm-svn: 144988
2011-11-19 07:33:10 +00:00
de6b73bb4d
Extend VPBLENDVB and VPSIGN lowering to work for AVX2.
...
llvm-svn: 144987
2011-11-19 07:07:26 +00:00
66e2b5a61e
Remove unused parameters from the AVX maskmov classes.
...
llvm-svn: 144985
2011-11-19 04:49:22 +00:00
1ec141d0f9
Add AVX2 vpbroadcast support
...
llvm-svn: 144967
2011-11-18 02:49:55 +00:00
ee93ff736a
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
...
llvm-svn: 144959
2011-11-18 01:17:34 +00:00
0eff3e5c21
Add TODO comment.
...
llvm-svn: 144920
2011-11-17 21:46:13 +00:00
f41e1d0246
Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments.
...
llvm-svn: 144896
2011-11-17 07:49:38 +00:00
15b2498e88
Dead code.
...
llvm-svn: 144888
2011-11-17 07:24:49 +00:00
f17b600577
Remove seemingly unnecessary duplicate VROUND definitions.
...
llvm-svn: 144885
2011-11-17 07:04:00 +00:00
489c0ff4a4
Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
...
names for fwrite and fputs.
Fixes <rdar://problem/9815881>.
llvm-svn: 144876
2011-11-17 01:27:36 +00:00
ce619ddfc5
Don't unconditionally set the kill flag.
...
rdar://10456186
llvm-svn: 144872
2011-11-17 01:16:53 +00:00
20439a42b0
Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing.
...
llvm-svn: 144867
2011-11-17 00:21:52 +00:00
d3f02cbce9
Generalize the fixup info for ARM mode.
...
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
2011-11-16 22:48:37 +00:00
b31abde0f3
Lower 64-bit constant pool node.
...
llvm-svn: 144849
2011-11-16 22:44:38 +00:00
eb42071721
Lower 64-bit block address.
...
llvm-svn: 144847
2011-11-16 22:42:10 +00:00
7ccdb7c0ae
Fix encoding of NOP used for padding in ARM mode .align.
...
llvm-svn: 144842
2011-11-16 22:40:25 +00:00
7b8547c4d0
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
...
nodes.
llvm-svn: 144841
2011-11-16 22:39:56 +00:00
6d617ceca2
64-bit jump register instruction.
...
llvm-svn: 144840
2011-11-16 22:36:01 +00:00
011538dc79
Another missing X86ISD::MOVLPD pattern. rdar://10450317
...
llvm-svn: 144839
2011-11-16 22:24:44 +00:00
bfe5c5c968
ARM assembly parsing for shifted register operands for MOV instruction.
...
llvm-svn: 144837
2011-11-16 21:50:05 +00:00
01e0439240
Clean up debug printing of ARM shifted operands.
...
llvm-svn: 144836
2011-11-16 21:46:50 +00:00
3127ab6d8f
ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
...
llvm-svn: 144814
2011-11-16 19:12:24 +00:00
1a2f9ee3c8
ARM assembly parsing for RRX mnemonic.
...
rdar://9704684
llvm-svn: 144812
2011-11-16 19:05:59 +00:00
48784ed5b7
Added missing comment about new custom lowering of DEC64
...
llvm-svn: 144811
2011-11-16 19:03:23 +00:00
80979b6ea6
Check to make sure we can select the instruction before trying to put the
...
operands into a register. Otherwise, we may materialize dead code.
llvm-svn: 144805
2011-11-16 18:39:44 +00:00
abcac56869
ARM mode aliases for bitwise instructions w/ register operands.
...
rdar://9704684
llvm-svn: 144803
2011-11-16 18:31:45 +00:00
0ca7ce389c
Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
...
llvm-svn: 144798
2011-11-16 17:09:59 +00:00
b345060a85
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
...
llvm-svn: 144794
2011-11-16 09:18:28 +00:00
ecb2908bf9
Sink codegen optimization level into MCCodeGenInfo along side relocation model
...
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
llvm-svn: 144788
2011-11-16 08:38:26 +00:00
3ed7d9ee5a
Fix the execution domain on a bunch of SSE/AVX instructions.
...
llvm-svn: 144784
2011-11-16 07:30:46 +00:00
f6d1728d8f
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
...
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal. The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block. The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op. The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.
Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.
llvm-svn: 144781
2011-11-16 07:11:57 +00:00
07d8b5e2c9
Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636.
...
llvm-svn: 144777
2011-11-16 05:02:04 +00:00
af13d767a2
Add FIXME comment.
...
llvm-svn: 144743
2011-11-16 00:32:20 +00:00
653183fd5c
Enable -widen-vmovs by default.
...
This will widen 32-bit register vmov instructions to 64-bit when
possible. The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.
The copies are only widened if they are marked as clobbering the whole
D-register.
llvm-svn: 144734
2011-11-15 23:53:18 +00:00
e891fe8d6c
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
llvm-svn: 144727
2011-11-15 23:19:15 +00:00
003cea6011
ARM assembly parsing for data type suffices on NEON VMOV aliases.
...
llvm-svn: 144722
2011-11-15 22:54:42 +00:00
37010002f2
AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code.
...
llvm-svn: 144720
2011-11-15 22:50:37 +00:00
75fb4abcdc
ARM assembly parsing two operand forms for shift instructions.
...
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
a01033709f
ARM VFP assembly parsing for VADD and VSUB two-operand forms.
...
llvm-svn: 144710
2011-11-15 22:15:10 +00:00
8279c1828f
ARM accept an immediate offset in memory operands w/o the '#'.
...
llvm-svn: 144709
2011-11-15 22:14:41 +00:00
7c7ba1baa1
Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
...
by later instructions.
Only done for DEC64m right now.
Fixes <rdar://problem/6172640>
llvm-svn: 144705
2011-11-15 21:57:53 +00:00
8d579230c6
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
...
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'
rdar://10450488.
llvm-svn: 144701
2011-11-15 21:45:55 +00:00
84f0ba5747
ARM size suffix on VFP single-precision 'vmov' is optional.
...
rdar://10435114
llvm-svn: 144698
2011-11-15 21:18:35 +00:00
a92a5d8548
Fix typo.
...
llvm-svn: 144695
2011-11-15 21:01:30 +00:00
131b45e632
ARM alternate size suffices for VTRN instructions.
...
rdar://10435076
llvm-svn: 144694
2011-11-15 20:49:46 +00:00
05060f0748
Fix a misplaced paren bug.
...
llvm-svn: 144692
2011-11-15 20:30:41 +00:00
5803f6d5a2
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
...
Yet more of rdar://10435076.
llvm-svn: 144691
2011-11-15 20:29:42 +00:00
c5b1bc561e
ARM assembly parsing for two-operand form of 'mul' instruction.
...
rdar://10449856.
llvm-svn: 144689
2011-11-15 20:14:51 +00:00
72dfd20aba
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
llvm-svn: 144688
2011-11-15 20:02:06 +00:00
efa7e95d06
Thumb2 two-operand 'mul' instruction wide encoding parsing.
...
rdar://10449724
llvm-svn: 144684
2011-11-15 19:55:16 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
...
llvm-svn: 144683
2011-11-15 19:55:00 +00:00
6efa7b9852
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
llvm-svn: 144679
2011-11-15 19:29:45 +00:00
6ee8fc88c7
Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit
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registers and instructions when ABI is N64.
llvm-svn: 144666
2011-11-15 18:53:55 +00:00
494913270e
Set nomacro before emitting the sequence of instructions that set global pointer
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register.
llvm-svn: 144665
2011-11-15 18:44:44 +00:00
66a14c0650
Simplify function PassByValArg64.
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llvm-svn: 144664
2011-11-15 18:42:25 +00:00
b7796ae938
Delete files.
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llvm-svn: 144655
2011-11-15 18:22:48 +00:00
1c0590c5da
Remove MipsMCSymbolRefExpr.
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llvm-svn: 144654
2011-11-15 18:20:08 +00:00
Chad Rosier