38a400df3b
Move PPC bits to lib/Target/PowerPC.
...
llvm-svn: 147124
2011-12-22 01:57:09 +00:00
2da9777cef
Hopefully fix the cmake build.
...
llvm-svn: 147121
2011-12-22 01:11:01 +00:00
4449b21294
Fix name in comments.
...
llvm-svn: 147119
2011-12-22 01:06:53 +00:00
e2eed9649e
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
...
ELF relocations.
Patch by Jack Carter.
llvm-svn: 147118
2011-12-22 01:05:17 +00:00
32a756b7ce
Unbreak cmake build after r147115.
...
llvm-svn: 147117
2011-12-22 01:03:35 +00:00
a0124055b1
Move the ARM specific parts of the ELF writer to Target/ARM.
...
llvm-svn: 147115
2011-12-22 00:37:50 +00:00
2b80dad572
ARM NEON mnemonic aliase for vrecpeq.
...
llvm-svn: 147109
2011-12-21 23:52:37 +00:00
7869d8c01e
ARM VFP optional data type on VMOV GPR<-->SPR.
...
llvm-svn: 147104
2011-12-21 23:24:15 +00:00
260b4b336a
ARM NEON optional data type on VSWP instructions.
...
llvm-svn: 147103
2011-12-21 23:09:28 +00:00
a50e24fcb3
ARM NEON mnemonic aliases for vzipq and vswpq.
...
llvm-svn: 147102
2011-12-21 23:04:33 +00:00
1152cc0cad
ARM asm parser should be more lenient w/ .thumb_func directive.
...
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
llvm-svn: 147100
2011-12-21 22:30:16 +00:00
8c59bbc1ed
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
...
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
3172488cc0
Fix 80-column violations.
...
llvm-svn: 147095
2011-12-21 20:59:09 +00:00
b3ef713e44
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
...
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
3588a43e3a
Move common code into an MRI function.
...
llvm-svn: 147071
2011-12-21 19:50:05 +00:00
c80a264386
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
...
llvm-svn: 147069
2011-12-21 19:40:55 +00:00
3ede414127
No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
...
necessary. Please chime in if I'm mistaken.
llvm-svn: 147065
2011-12-21 19:14:52 +00:00
7248bda595
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
...
llvm-svn: 147064
2011-12-21 18:56:22 +00:00
b264d33854
Move the X86 specific bits of the ELF writer to the Target/X86 directory.
...
Other targets will follow shortly.
llvm-svn: 147060
2011-12-21 17:30:17 +00:00
1ad4095d6b
Reduce the exposure of Triple::OSType in the ELF object writer. This will
...
avoid including ADT/Triple.h in many places when the target specific bits are
moved.
llvm-svn: 147059
2011-12-21 17:00:36 +00:00
b8b1b4c1de
Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored.
...
llvm-svn: 147046
2011-12-21 08:06:52 +00:00
f30188418b
Fix typo in a couple comments
...
llvm-svn: 147045
2011-12-21 06:30:53 +00:00
dc8a1aaea6
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
...
llvm-svn: 147032
2011-12-21 03:04:10 +00:00
7de7ab83fa
ARM assembly parsing allows constant expressions for lane indices.
...
llvm-svn: 147028
2011-12-21 01:19:23 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
...
llvm-svn: 147025
2011-12-21 00:38:54 +00:00
964c891e61
Fix bug in zero-store peephole pattern reported in pr11615.
...
The patch and test case were originally written by Mans Rullgard.
llvm-svn: 147024
2011-12-21 00:31:10 +00:00
1d8efaba7e
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
...
case for DCLO and DCLZ.
llvm-svn: 147022
2011-12-21 00:20:27 +00:00
410ce9cb44
Expand 64-bit CTPOP and CTTZ.
...
llvm-svn: 147021
2011-12-21 00:14:05 +00:00
91c052c4d8
Expand 64-bit atomic load and store.
...
llvm-svn: 147019
2011-12-21 00:02:58 +00:00
4706ac9715
Add definition of DSBH (Double Swap Bytes within Halfwords) and
...
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
llvm-svn: 147017
2011-12-20 23:56:43 +00:00
43c1ff4db3
Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
...
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
WSBW is removed since it is not an instruction the current architectures
support.
llvm-svn: 147015
2011-12-20 23:47:44 +00:00
79aed157e7
64-bit uint-fp conversion nodes are expanded.
...
llvm-svn: 147014
2011-12-20 23:40:56 +00:00
2bb8d068f5
Enable custom lowering DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 147013
2011-12-20 23:35:46 +00:00
8e2c02e2d6
Set the correct stack pointer register that should be saved or restored.
...
llvm-svn: 147012
2011-12-20 23:28:36 +00:00
cd22e4a81e
ARM .req register name aliases are case insensitive, just like regnames.
...
llvm-svn: 147009
2011-12-20 23:11:00 +00:00
cb2a85bc22
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
...
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
llvm-svn: 147008
2011-12-20 23:10:57 +00:00
2c8d1734f8
Fix indentation.
...
llvm-svn: 147007
2011-12-20 22:58:01 +00:00
cf10f08825
64-bit data directive.
...
llvm-svn: 147005
2011-12-20 22:52:19 +00:00
494fdf1499
32-to-64-bit sext_inreg pattern.
...
llvm-svn: 147004
2011-12-20 22:40:40 +00:00
8756816e6f
Add 64-bit extload patterns.
...
llvm-svn: 147003
2011-12-20 22:36:08 +00:00
0cee2045c9
Add patterns for matching extloads with 64-bit address. The patterns are enabled
...
only when the target ABI is N64.
llvm-svn: 147001
2011-12-20 22:33:53 +00:00
4eda145c7f
Move comment to appropriate place.
...
llvm-svn: 147000
2011-12-20 22:26:38 +00:00
dac1d48d8d
Add code in MipsDAGToDAGISel for selecting constant +0.0.
...
MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
llvm-svn: 146999
2011-12-20 22:25:50 +00:00
b95c102c2f
Heed spill slot alignment on ARM.
...
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
llvm-svn: 146997
2011-12-20 22:15:04 +00:00
14468c6cb6
Revert part of r146995 that was accidentally commmitted.
...
llvm-svn: 146996
2011-12-20 22:09:36 +00:00
4e210691c0
32-to-64-bit sign extension pattern.
...
llvm-svn: 146995
2011-12-20 22:06:20 +00:00
9b9bd1cc15
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
...
only when the target ABI is N64.
llvm-svn: 146992
2011-12-20 21:50:49 +00:00
2c59052984
ARM assembly parsing and encoding for VST2 single-element, double spaced.
...
llvm-svn: 146990
2011-12-20 20:46:29 +00:00
75e2ab5db2
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
...
llvm-svn: 146983
2011-12-20 19:21:26 +00:00
68132d8093
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
...
llvm-svn: 146981
2011-12-20 18:26:50 +00:00
135d244b56
First steps in ARM AsmParser support for .eabi_attribute and .arch
...
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
llvm-svn: 146977
2011-12-20 17:38:12 +00:00
ec7e6e0946
This is the second fix related to VZEXT_MOVL node.
...
The failure that I see in the current version is:
LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
0x18b9870: v4i64 = undef [ID=4]
0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9970: i32 = Constant<0> [ID=3]
0x18b9170: v2i64 = undef [ORD=1] [ID=1]
0x18b9570: i32 = Constant<2> [ID=5]
llvm-svn: 146975
2011-12-20 13:34:28 +00:00
24680c24d8
Begin teaching the X86 target how to efficiently codegen patterns that
...
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.
The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.
llvm-svn: 146974
2011-12-20 11:19:37 +00:00
e805b16e3d
Fix up the CMake build for the new files added in r146960, they're
...
likely to stay either way that discussion ends up resolving itself.
llvm-svn: 146966
2011-12-20 08:42:11 +00:00
a379b18173
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
...
llvm-svn: 146960
2011-12-20 02:50:00 +00:00
75f12cc3fe
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
...
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
llvm-svn: 146949
2011-12-20 01:29:27 +00:00
e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
94580ab375
Add basic generic CodeGen support for half.
...
llvm-svn: 146927
2011-12-20 00:02:33 +00:00
045b6c71a6
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
...
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"
rdar://10603913
llvm-svn: 146925
2011-12-19 23:51:07 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
db47e0c49d
Add patterns for matching immediates whose lower 16-bit is cleared. These
...
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
llvm-svn: 146900
2011-12-19 20:21:18 +00:00
9e1d369e3c
Tidy up. Simplify logic. No functional change intended.
...
llvm-svn: 146896
2011-12-19 19:52:25 +00:00
64f4de29e0
ARM NEON two-operand aliases for VPADD.
...
rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
2a232d81f6
Remove definitions of double word shift plus 32 instructions. Assembler or
...
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
llvm-svn: 146893
2011-12-19 19:44:09 +00:00
e16acacc3a
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
...
llvm-svn: 146892
2011-12-19 19:43:50 +00:00
c4db30e358
Remove unused predicate.
...
llvm-svn: 146889
2011-12-19 19:32:20 +00:00
3c9f336361
Remove the restriction on the first operand of the add node in SelectAddr.
...
This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
llvm-svn: 146888
2011-12-19 19:28:37 +00:00
92a939ae73
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
...
llvm-svn: 146887
2011-12-19 19:02:41 +00:00
9ae4fc035b
ARM NEON implied destination aliases for VMAX/VMIN.
...
llvm-svn: 146885
2011-12-19 18:57:38 +00:00
cef98cddbe
ARM NEON relax parse time diagnostics for alignment specifiers.
...
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
a7d2421603
Tidy up.
...
llvm-svn: 146882
2011-12-19 18:11:17 +00:00
24159e346d
Remove a register class that can just as well be synthesized.
...
Add the new TableGen register class synthesizer feature to the release
notes.
llvm-svn: 146875
2011-12-19 16:53:40 +00:00
c7b437ae34
Emit a getMatchingSuperRegClass() implementation for every target.
...
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
llvm-svn: 146873
2011-12-19 16:53:34 +00:00
1b54835a10
Another variadics tweak.
...
llvm-svn: 146852
2011-12-18 20:51:31 +00:00
530b820500
Use the fancy new VariadicFunction template instead of a plain variadic function.
...
Some compilers were complaining about passing StringRef to it.
llvm-svn: 146850
2011-12-18 19:59:20 +00:00
32481916eb
Hexagon: Remove unused variables.
...
llvm-svn: 146846
2011-12-18 12:00:09 +00:00
a913dde0ef
Remove an unused X86ISD node type.
...
llvm-svn: 146833
2011-12-17 19:16:44 +00:00
792edd3c75
X86: Factor the bswap asm matching to be slightly less horrible to read.
...
llvm-svn: 146831
2011-12-17 14:36:05 +00:00
903231bc58
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
...
llvm-svn: 146805
2011-12-17 01:25:34 +00:00
d3df3d3527
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
...
asm parsing and testcase.
llvm-svn: 146801
2011-12-17 01:14:52 +00:00
da07b3ad42
Make sure that the lower bits on the VSELECT condition are properly set.
...
llvm-svn: 146800
2011-12-17 01:08:46 +00:00
465cdf3ba4
Preserve more memory operands in ARMExpandPseudo.
...
I don't think this affects anything but verbose assembly.
llvm-svn: 146787
2011-12-17 00:07:02 +00:00
9790187b6c
Fix off-by-one error in bucket sort.
...
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/10594653>
llvm-svn: 146767
2011-12-16 23:00:05 +00:00
5af144809e
Don't adjust for alignment padding in OffsetIsInRange.
...
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.
When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.
llvm-svn: 146751
2011-12-16 19:10:00 +00:00
9ca2e7293b
Hexagon: Fix a nasty order-of-initialization bug.
...
Reenable the tests.
llvm-svn: 146750
2011-12-16 19:08:59 +00:00
2a05f691ab
Note ARM constant island alignment in the release notes.
...
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.
llvm-svn: 146739
2011-12-16 16:07:41 +00:00
a4d411cb1b
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
...
llvm-svn: 146726
2011-12-16 08:06:31 +00:00
93d990bd61
Target/Hexagon: Fix CMake build.
...
llvm-svn: 146724
2011-12-16 06:21:02 +00:00
4a29971f02
ARM NEON aliases for vmovq.f*
...
llvm-svn: 146714
2011-12-16 00:12:22 +00:00
66886253a7
Thumb2 ADR assembly parsing w/o the .w suffix.
...
llvm-svn: 146710
2011-12-15 23:52:17 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
...
llvm-svn: 146709
2011-12-15 23:46:18 +00:00
c9e935c7e2
Move parts of lib/Target that use CodeGen into lib/CodeGen.
...
llvm-svn: 146702
2011-12-15 22:58:58 +00:00
c9bf1b1bff
Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.)
...
llvm-svn: 146700
2011-12-15 22:56:53 +00:00
a47294e24d
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
...
llvm-svn: 146699
2011-12-15 22:56:33 +00:00
b3705e0b9e
Add MCTargetDesc library to Hexagon target
...
llvm-svn: 146692
2011-12-15 22:29:08 +00:00
4a5c887370
ARM NEON VTBL/VTBX assembly parsing and encoding.
...
llvm-svn: 146691
2011-12-15 22:27:11 +00:00
cba8e8c3e0
Enable proper constant island alignment by default.
...
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.
llvm-svn: 146690
2011-12-15 22:14:45 +00:00
41dbf59e12
Add missing zmovl AVX patterns which were causing crashes.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146689
2011-12-15 22:11:31 +00:00
c2f16a3499
Silence warning.
...
llvm-svn: 146686
2011-12-15 21:54:55 +00:00
2f50e92f40
ARM NEON two-register double spaced register list parsing support.
...
llvm-svn: 146685
2011-12-15 21:44:33 +00:00
75ed9dcbc6
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146684
2011-12-15 21:34:44 +00:00
c44b5e469b
Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.
...
llvm-svn: 146671
2011-12-15 18:57:27 +00:00
9dd3f62b38
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
...
llvm-svn: 146664
2011-12-15 17:54:01 +00:00
275e874c67
Pass optLevel to XCoreDAGToDAGISel.
...
Patch by Kyriakos Georgiou.
llvm-svn: 146656
2011-12-15 15:18:35 +00:00
b7a0b89ff0
Use SmallVector/assign(), rather than std::vector/push_back().
...
llvm-svn: 146627
2011-12-15 01:16:09 +00:00
1940baa76b
Add support for lowering fneg when AVX is enabled.
...
rdar://10566486
llvm-svn: 146625
2011-12-15 01:02:25 +00:00
ae94fb4009
The saved registers weren't being processed in the correct order. This lead to
...
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.
llvm-svn: 146612
2011-12-14 23:53:24 +00:00
9efd7ebf0a
Consider CPE alignment in CreateNewWater().
...
An aligned constant pool entry may require extra alignment padding where
the new water is created. Take that into account when computing offset.
Also consider the alignment of other constant pool entries when
splitting a basic block. Alignment padding may make it necessary to
move the split point higher.
llvm-svn: 146609
2011-12-14 23:48:54 +00:00
da51104282
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
...
llvm-svn: 146608
2011-12-14 23:35:06 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
...
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
bb18fb4f52
ARM NEON fix alignment encoding for VST2 w/ writeback.
...
Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
8e987f5e25
Nuke old code. Missed in last commit.
...
llvm-svn: 146590
2011-12-14 21:41:32 +00:00
88ac761aa4
ARM NEON refactor VST2 w/ writeback instructions.
...
In addition to improving the representation, this adds support for assembly
parsing of these instructions.
llvm-svn: 146588
2011-12-14 21:32:11 +00:00
b7ec06c5c9
ARM NEON improve factoring a bit. No functional change.
...
llvm-svn: 146585
2011-12-14 20:59:15 +00:00
da103bf9ec
Model ARM predicated write as read-mod-write. e.g.
...
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
llvm-svn: 146583
2011-12-14 20:00:08 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
...
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
e5585e8fed
Fix speling and 80-col.
...
llvm-svn: 146575
2011-12-14 18:49:13 +00:00
bff84e1914
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
...
emission is not supported yet, but a patch that adds the support should follow
soon.
llvm-svn: 146572
2011-12-14 18:26:41 +00:00
4288b9786f
Fix copy/pasto that skipped the 'modify' step.
...
llvm-svn: 146571
2011-12-14 18:12:37 +00:00
1bb6e066f6
ARM/Thumb2 mov vs. mvn alias goes both ways.
...
llvm-svn: 146570
2011-12-14 17:56:51 +00:00
ded6160473
VFP2 is required for FP loads. Noticed by inspection.
...
llvm-svn: 146569
2011-12-14 17:55:03 +00:00
fce28914ea
Tidy up.
...
llvm-svn: 146568
2011-12-14 17:32:02 +00:00
a342667fd0
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
...
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
a26979be29
Fix 80-column violation and extraneous brackets.
...
llvm-svn: 146566
2011-12-14 17:26:05 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
...
rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
7fae11b231
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
...
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
llvm-svn: 146542
2011-12-14 02:11:42 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
...
rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
6eb142a616
Thumb2 pre/post indexed stores can be from any non-PC GPR.
...
rdar://10549786
llvm-svn: 146518
2011-12-13 21:10:25 +00:00
5ac89675a0
Thumb2 tweak for ccout handling in RSB parsing.
...
llvm-svn: 146516
2011-12-13 21:06:41 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
...
rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
...
llvm-svn: 146514
2011-12-13 20:40:37 +00:00
561e4e18cf
ARM pre-UAL NEG mnemonic for convenience when porting old code.
...
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
2a2348e6c2
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146508
2011-12-13 20:13:48 +00:00
9227f39c53
ARM add more 'gas' compatibility aliases for NEON instructions.
...
llvm-svn: 146507
2011-12-13 20:08:32 +00:00
563de603f7
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
...
load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
5e9d16cb53
Expand .cprestore directive to multiple instructions if the offset does not fit
...
in a 16-bit field.
llvm-svn: 146469
2011-12-13 03:09:05 +00:00
637cc6a8aa
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
...
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
llvm-svn: 146466
2011-12-13 01:56:10 +00:00
bfa576fe8e
Account for CPE alignment when searching for new water.
...
Constant pool entries with different alignment may cause more alignment
padding to be inserted. Compute the amount of padding needed, and try to
pick the location that requires the least amount of padding.
Also take the extra padding into account when the water is above the
use.
llvm-svn: 146458
2011-12-13 00:44:30 +00:00
4ea3c8f54a
Target/Hexagon: Fix CMake build. We don't use add_llvm_library_dependencies().
...
llvm-svn: 146457
2011-12-13 00:36:04 +00:00
8889bb08b8
LLVMBuild: Introduce a common section which currently has a list of the
...
subdirectories to traverse into.
- Originally I wanted to avoid this and just autoscan, but this has one key
flaw in that new subdirectories can not automatically trigger a rerun of the
llvm-build tool. This is particularly a pain when switching back and forth
between trees where one has added a subdirectory, as the dependencies will
tend to be wrong. This will also eliminates FIXME implicitly.
llvm-svn: 146436
2011-12-12 22:45:54 +00:00
5d5e0d819d
Emit B (unconditional branch) when -relocation-model=pic and J (jump) when
...
-relocation-model=static.
llvm-svn: 146432
2011-12-12 22:39:35 +00:00
faa88c0add
Fix indentation.
...
llvm-svn: 146431
2011-12-12 22:38:19 +00:00
36e0519ca2
fix warning
...
llvm-svn: 146420
2011-12-12 21:52:59 +00:00
fadc2c83e5
Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
...
These modifiers simply select either the low or high D subregister of a Neon
Q register. I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.
llvm-svn: 146417
2011-12-12 21:45:15 +00:00
1213a7a57f
Hexagon backend support
...
llvm-svn: 146412
2011-12-12 21:14:40 +00:00
27a7489a03
LLVMBuild: Remove trailing newline, which irked me.
...
llvm-svn: 146409
2011-12-12 19:48:00 +00:00
7c0face455
XOP instructions and encoding tests.
...
llvm-svn: 146407
2011-12-12 19:37:49 +00:00
91a7bcbb9b
Add a postOffset() alignment argument.
...
This computes the offset of the layout sucessor block, considering its
alignment as well.
llvm-svn: 146401
2011-12-12 19:25:54 +00:00
0863de458d
Fix typo.
...
llvm-svn: 146400
2011-12-12 19:25:51 +00:00
6dd2488383
XOP encoding bits and logic.
...
llvm-svn: 146397
2011-12-12 19:12:26 +00:00
17c27a8898
Also set the proper alignment on inner islands and the function itself.
...
Downgrade the alignment of the initial constant island when constant
pool entries are moved elsewhere.
This is all gated by -arm-align-constant-islands.
llvm-svn: 146391
2011-12-12 18:45:45 +00:00
2a75997858
Make MF a class member instead of passing it around everywhere.
...
Also add an MCP member pointing to the machine constant pool.
No functional change intended.
llvm-svn: 146382
2011-12-12 18:16:53 +00:00
b5f52aad22
Add a -arm-align-constant-islands flag, default off.
...
Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment. When the command line
flag is set, also align the basic block containing the constant pool
entries.
This is only a partial implementation of constant island alignment. More
to come.
llvm-svn: 146375
2011-12-12 16:49:37 +00:00
1fdfec63a4
Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.
...
llvm-svn: 146344
2011-12-11 19:12:35 +00:00
4683740967
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
...
llvm-svn: 146341
2011-12-11 14:35:48 +00:00
64ba50a972
Mips: Don't create a dangling IR function just to get the address of a symbol.
...
llvm-svn: 146340
2011-12-11 12:21:34 +00:00
a6c59b8fc8
Also remove unnecessary includes from this file, which was supposed to be part
...
of r146334!
llvm-svn: 146338
2011-12-11 00:45:13 +00:00
a461c1c069
Minimize #include's and forward-declares in Target.
...
llvm-svn: 146335
2011-12-10 22:35:47 +00:00
b9cda978ab
Refactor the implementation of the TargetOptions out of TargetMachine, taking
...
the only parts of TM that depends on CodeGen headers with it.
llvm-svn: 146334
2011-12-10 22:34:41 +00:00
6641294e3b
Revert r146322 to appease buildbots. Original commit message:
...
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
llvm-svn: 146328
2011-12-10 19:55:03 +00:00
df0b779e9f
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
...
llvm-svn: 146322
2011-12-10 08:42:24 +00:00
67a7f18faf
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
...
llvm-svn: 146318
2011-12-10 04:50:53 +00:00
146ac7b609
Try to align the point where a large basic block is split.
...
The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.
This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.
<rdar://problem/10550705>
There is still an issue with correctly packing differently aligned
entries in the island.
llvm-svn: 146314
2011-12-10 02:55:10 +00:00
b3734522fa
More debug output formatting.
...
llvm-svn: 146313
2011-12-10 02:55:06 +00:00
c7f355b8e1
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
...
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
llvm-svn: 146311
2011-12-10 02:28:43 +00:00
54337b8617
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146300
2011-12-10 00:01:02 +00:00
4e36a934dc
Splats can contain undef's; make sure to handle them correctly. PR11526.
...
llvm-svn: 146299
2011-12-09 23:54:42 +00:00
8be2f6577e
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146296
2011-12-09 23:34:09 +00:00
ef70e9b704
ARM allows '' syntax, not just '#imm' for assembly.
...
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
llvm-svn: 146285
2011-12-09 22:25:03 +00:00
6192b6570d
ARM assembly aliases for BIC<-->AND (immediate).
...
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
ea1b353e67
ARM NEON data type aliases for VBIC(register).
...
llvm-svn: 146281
2011-12-09 21:46:04 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
...
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
f85723626c
User a helper overload for a common pattern.
...
llvm-svn: 146270
2011-12-09 19:44:39 +00:00
8a4009dab2
Tidy up. Better base class factoring.
...
llvm-svn: 146267
2011-12-09 19:07:20 +00:00
b076e6f3d5
Tidy up. Better base class factoring.
...
llvm-svn: 146266
2011-12-09 18:54:11 +00:00
5f5fa12413
Tweak debugging output.
...
llvm-svn: 146264
2011-12-09 18:20:35 +00:00
863683c590
This is now implemented.
...
llvm-svn: 146258
2011-12-09 15:45:57 +00:00
16bbfbec66
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
...
llvm-svn: 146257
2011-12-09 15:44:03 +00:00
2dc5dec41d
X86: Split (v)rounds[sd] into a normal and an intrinsic version.
...
llvm-svn: 146256
2011-12-09 15:43:55 +00:00
feb9f27de1
Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
...
llvm-svn: 146247
2011-12-09 06:41:08 +00:00
557cda7f1d
Remove hasSSE1orAVX(). It's the same as hasXMM().
...
llvm-svn: 146246
2011-12-09 06:32:46 +00:00
5ee8464e48
Rename WrapperPIC. It is now used for both pic and static.
...
llvm-svn: 146232
2011-12-09 01:53:17 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
...
specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
8cc83fa1b7
ARM convenience aliases for VSQRT.
...
llvm-svn: 146201
2011-12-08 22:51:25 +00:00
b96bca81e7
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
...
llvm-svn: 146196
2011-12-08 22:30:45 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
...
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
bb15fec2b8
Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
...
llvm-svn: 146193
2011-12-08 22:15:21 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
...
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
2a217be25f
Add various missing AVX patterns which was causing crashes. Sadly, the generated
...
code looks pretty bad compared to SSE.
rdar://10538793
llvm-svn: 146191
2011-12-08 22:05:28 +00:00
98bc797b4d
ARM asm parser, just issue a warning for a duplicate reg in a list.
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For better 'gas' compatibility.
llvm-svn: 146185
2011-12-08 21:34:20 +00:00
f10ee84956
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
...
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
llvm-svn: 146183
2011-12-08 21:05:38 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
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llvm-svn: 146182
2011-12-08 20:56:26 +00:00
57a7f41d5d
Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
...
Fixes failures caused by r146171.
llvm-svn: 146180
2011-12-08 20:51:38 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
...
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
...
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
dee6c8275c
Implement 64-bit support for thread local storage handling.
...
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
llvm-svn: 146175
2011-12-08 20:34:32 +00:00
0b9b9da6c8
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
...
llvm-svn: 146171
2011-12-08 19:32:14 +00:00
4edc7360c7
ARM assembler support for register name aliases.
...
rdar://10550084
llvm-svn: 146170
2011-12-08 19:27:38 +00:00
4d1a2d449f
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
...
if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
llvm-svn: 146163
2011-12-08 19:00:42 +00:00
c09e4593b2
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
...
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
d19760a40c
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
...
llvm-svn: 146151
2011-12-08 14:43:19 +00:00
a4bcf27dae
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
...
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
528ff4bee0
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)
...
llvm-svn: 146137
2011-12-08 04:36:44 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
...
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
14e024dff7
Drop the HasInlineAsm flag.
...
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.
A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.
llvm-svn: 146124
2011-12-08 01:22:39 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
...
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
bd97f5d753
Simplify offset verification.
...
llvm-svn: 146121
2011-12-08 01:10:05 +00:00
0dd1bc9c79
Fix copy/past-o.
...
llvm-svn: 146120
2011-12-08 01:02:26 +00:00
31a462c02c
ARM NEON two-operand aliases for VMUL.
...
llvm-svn: 146119
2011-12-08 00:59:47 +00:00
2a82333f54
Don't include alignment padding in BBInfo.Size.
...
Compute alignment padding before and after basic blocks dynamically.
Heed basic block alignment.
This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size. It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.
This makes the ARMConstantIslandPass aware of aligned basic blocks.
It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size. If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected. This could cause constant
pool entries to move out of range.
To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly. Normal
functions should be unaffected.
llvm-svn: 146118
2011-12-08 00:55:02 +00:00
9a6ba3c94e
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
...
llvm-svn: 146116
2011-12-08 00:52:55 +00:00
086d013e56
ARM VFP support 'flds/fldd' aliases for 'vldr'
...
llvm-svn: 146115
2011-12-08 00:49:29 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
...
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
4350c183d4
Modify class ReadHardware and add definition of 64-bit version of instruction
...
RDHWR.
llvm-svn: 146101
2011-12-07 23:31:26 +00:00
66232aa19d
Add newline.
...
llvm-svn: 146100
2011-12-07 23:26:03 +00:00
36d2198dae
Add 64-bit HWR29 register.
...
llvm-svn: 146099
2011-12-07 23:23:52 +00:00
9778e7a67c
32 to 64-bit anyext pattern.
...
llvm-svn: 146097
2011-12-07 23:21:19 +00:00
ae378af667
32 to 64-bit zext pattern.
...
llvm-svn: 146096
2011-12-07 23:14:41 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
...
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
...
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
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llvm-svn: 146091
2011-12-07 22:52:54 +00:00
56b70de01b
Variable cleanup. Based on past patch submittals variable names have
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been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.
llvm-svn: 146088
2011-12-07 22:35:30 +00:00
b2e05cb6b1
64-bit WrapperPICPat patterns.
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llvm-svn: 146086
2011-12-07 22:11:43 +00:00
6820eebde1
Define base class for WrapperPICPat.
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llvm-svn: 146081
2011-12-07 21:54:54 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
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llvm-svn: 146080
2011-12-07 21:48:50 +00:00
4f864b78e6
Fix comment.
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llvm-svn: 146063
2011-12-07 20:15:01 +00:00
d16e926a6b
Fix comment.
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llvm-svn: 146062
2011-12-07 20:13:53 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
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llvm-svn: 146059
2011-12-07 20:10:24 +00:00
d633c2f120
Nuke inadvertant debugging commit.
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llvm-svn: 146057
2011-12-07 19:56:16 +00:00
d6ae4ba002
Darwin assembler improved relocs when w/o subsections_via_symbols.
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
2011-12-07 19:46:59 +00:00
18b0e5dca0
Thumb2 alias for long-form pop and friends.
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rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
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llvm-svn: 146042
2011-12-07 18:04:19 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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llvm-svn: 146039
2011-12-07 17:51:15 +00:00
1d578e8835
Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.
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llvm-svn: 146031
2011-12-07 08:30:53 +00:00
302cf8d5d0
Adjust the stack by one pointer size for all frameless stacks.
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llvm-svn: 146030
2011-12-07 07:58:55 +00:00
3c86459997
Fix off-by-one error when encoding the stack size for a frameless stack.
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llvm-svn: 146029
2011-12-07 07:49:49 +00:00
7f8e563a69
Add bundle aware API for querying instruction properties and switch the code
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generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
llvm-svn: 146026
2011-12-07 07:15:52 +00:00
ac9df3d411
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
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llvm-svn: 146024
2011-12-07 06:34:06 +00:00
16c744180d
make base register selection used in eliminateFrameIndex 64-bit clean
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llvm-svn: 146023
2011-12-07 06:34:02 +00:00
abbc2529c1
set mayStore and mayLoad on CR pseudos
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llvm-svn: 146022
2011-12-07 06:33:57 +00:00
2ba61e47a9
64-bit LR8 load should use X11 not R11
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llvm-svn: 146021
2011-12-07 06:32:37 +00:00
2f0400b780
Eliminate delta argument from AdjustBBOffsetsAfter.
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The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
llvm-svn: 146018
2011-12-07 05:17:30 +00:00
97c857199e
Compute some alignment information for each basic block.
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These fields are not used for anything yet.
llvm-svn: 146017
2011-12-07 04:17:35 +00:00
2cf294a213
ARM tidy up and remove no longer needed InstAlias definitions.
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The TokenAlias handling of data type suffices renders these unnecessary.
llvm-svn: 146010
2011-12-07 01:50:36 +00:00
af748e1180
Move common expression into a method.
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llvm-svn: 146008
2011-12-07 01:22:52 +00:00
585ce30b8b
ARM Implement ARM ARM Table A7-3 via TokenAlias.
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Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
llvm-svn: 146007
2011-12-07 01:17:58 +00:00
e2b3ff2a07
Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
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No functional change is intended.
llvm-svn: 146005
2011-12-07 01:08:25 +00:00
Rafael Espindola