Commit Graph

15017 Commits

Author SHA1 Message Date
Benjamin Kramer f1f2133ac0 Remove dead recursive function. Yay for clang -Wunused-function.
llvm-svn: 112060
2010-08-25 17:27:58 +00:00
Daniel Dunbar a54a1b0edf ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed
comparison that would overflow.
 - The other under/overflow cases can't actually happen because the immediates
   which would trigger them are legal (so we don't enter this code), but
   adjusted the style to make it clear the transform is always valid.

llvm-svn: 112053
2010-08-25 16:58:05 +00:00
Eric Christopher 7a0d8c69cb Do type checks before we bother to do everything else.
llvm-svn: 112039
2010-08-25 08:43:57 +00:00
Anton Korobeynikov b3b53ecac0 Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there.
Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove
other flags-clobberring stuff (e.g. cmp instructions) occuring after
_alloca call.

llvm-svn: 112034
2010-08-25 07:50:11 +00:00
Eric Christopher 761e7fb605 Reorganize load mechanisms. Handle types in a little less fixed way.
Fix some todos.  No functional change.

llvm-svn: 112031
2010-08-25 07:23:49 +00:00
Bruno Cardoso Lopes 0770d25758 PUNPCKLDQ should also be used for v4f32
llvm-svn: 112020
2010-08-25 02:55:40 +00:00
Bruno Cardoso Lopes 2e45d522c1 teach lowering to get target specific nodes for pshufd, emulating the same isel behavior for now, so we can pass all vector shuffle tests
llvm-svn: 112017
2010-08-25 02:35:37 +00:00
Eric Christopher 15b182f4d4 Fix predicate and add a comment.
llvm-svn: 111981
2010-08-24 22:34:11 +00:00
Eric Christopher 236ec8f3b5 Rework braindead conditionals I put in yesterday.
llvm-svn: 111974
2010-08-24 22:07:27 +00:00
Eric Christopher 6c99ebf5b0 Fix thumb2 mode loads to have the correct operand ordering. Add a todo
to fix this in the port.

llvm-svn: 111973
2010-08-24 22:03:02 +00:00
Jim Grosbach 2eedb7949e Add ARM heuristic for when to allocate a virtual base register for stack
access. rdar://8277890&7352504

llvm-svn: 111968
2010-08-24 21:19:33 +00:00
Daniel Dunbar 1c8d777c93 MC/X86: Tweak imul recognition, previous hack only applies for the imul form
taking immediates.

llvm-svn: 111950
2010-08-24 19:37:56 +00:00
Daniel Dunbar 09392785b4 MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.
llvm-svn: 111947
2010-08-24 19:24:18 +00:00
Daniel Dunbar 94b84a19b9 MC/X86: Warn on scale factors > 1 without index register, instead of erroring,
for 'as' compatibility.

llvm-svn: 111945
2010-08-24 19:13:38 +00:00
Jim Grosbach b77d67f318 Move enabling the local stack allocation pass into the target where it belongs.
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.

llvm-svn: 111942
2010-08-24 19:05:43 +00:00
Jim Grosbach 35b7c033d4 add ARM cmd line option to force always using virtual base regs when possible.
Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.

llvm-svn: 111930
2010-08-24 18:04:52 +00:00
Dan Gohman c88fda477a Fix X86's isLegalAddressingMode to recognize that static addresses
need not be RIP-relative in small mode.

llvm-svn: 111917
2010-08-24 15:55:12 +00:00
Kalle Raiskila 7e25bc4145 Fix SPU BE to use all the available return registers.
llc used to assert on the added testcase.

llvm-svn: 111911
2010-08-24 11:50:48 +00:00
Kalle Raiskila 8f3e3ba5ff Remove some dead code from SPU BE that remained
from 64bit vector support.

llvm-svn: 111910
2010-08-24 11:05:51 +00:00
Bruno Cardoso Lopes 758d7b1f5c Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments
llvm-svn: 111890
2010-08-24 01:16:15 +00:00
Bill Wendling 2c64ba63a1 Add comments for what the condition code symbols mean.
llvm-svn: 111889
2010-08-24 01:11:30 +00:00
Eric Christopher 46d3a56e5d Update comment.
llvm-svn: 111887
2010-08-24 01:10:52 +00:00
Eric Christopher c0c00ca33f Fix the opcode and the operands for the load instruction.
llvm-svn: 111885
2010-08-24 01:10:04 +00:00
Eric Christopher eb47692c22 Add register class hack that needs to go away, but makes it more obvious
that it needs to go away.  Use loadRegFromStackSlot where possible.

Also, remember to update the value map.

llvm-svn: 111883
2010-08-24 00:50:47 +00:00
Eric Christopher 9d4e471cc2 Add some more debugging code, make it more obvious that RegOffset is
getting an address for an object and select some default values.

llvm-svn: 111871
2010-08-24 00:07:24 +00:00
Eric Christopher e3107d6283 Don't need the extra register here.
llvm-svn: 111864
2010-08-23 23:28:04 +00:00
Eric Christopher 414501c511 Add some more "get address into register" code and a more TODOs/FIXMEs.
llvm-svn: 111860
2010-08-23 23:14:31 +00:00
Eric Christopher 8d03b8a8ce Add an ARMFunctionInfo member and use it.
llvm-svn: 111854
2010-08-23 22:32:45 +00:00
Eric Christopher 00202ee329 Start getting ARM loads/address computation going.
llvm-svn: 111850
2010-08-23 21:44:12 +00:00
Bruno Cardoso Lopes 264d90fff7 Start using target speficic nodes for shuffles: pshufhw and pshuflw
llvm-svn: 111837
2010-08-23 20:41:02 +00:00
Gabor Greif 21fed6616c tyops
llvm-svn: 111835
2010-08-23 20:30:51 +00:00
Chris Lattner 58bd73a5a7 Add a new llvm.x86.int intrinsic, allowing access to the
x86 int and int3 instructions.  Patch by Peter Housel!

llvm-svn: 111831
2010-08-23 19:39:25 +00:00
Chris Lattner a42202e0e4 random improvement for variable shift codegen.
llvm-svn: 111813
2010-08-23 17:30:29 +00:00
Anton Korobeynikov cbbe4501df Revert invalid r111792. Jump tables are not broken on x86-64 / coff,
it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.

llvm-svn: 111801
2010-08-23 07:38:51 +00:00
Michael J. Spencer e87231232a Workaround broken jump tables on x86-64 COFF.
llvm-svn: 111792
2010-08-23 04:45:37 +00:00
Anton Korobeynikov db9820ecaa Use rip-rel addressing on win64 by default. For this we just
defaults to small pic code model.

llvm-svn: 111741
2010-08-21 17:21:11 +00:00
Michael J. Spencer 377aa20e6e MC: Add partial x86-64 support to COFF.
llvm-svn: 111728
2010-08-21 05:58:13 +00:00
Dan Gohman 42ef669d81 Fix x86 fast-isel's cmp+branch folding to avoid folding when the
comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.

llvm-svn: 111709
2010-08-21 02:32:36 +00:00
Bruno Cardoso Lopes 9f20e7a1bf Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly
llvm-svn: 111704
2010-08-21 01:32:18 +00:00
Bruno Cardoso Lopes 6f3b38a851 This is the first step towards refactoring the x86 vector shuffle code. The
general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.

The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.

llvm-svn: 111691
2010-08-20 22:55:05 +00:00
Bill Wendling 578ee4070c Create the new linker type "linker_private_weak_def_auto".
It's similar to "linker_private_weak", but it's known that the address of the
object is not taken. For instance, functions that had an inline definition, but
the compiler decided not to inline it. Note, unlike linker_private and
linker_private_weak, linker_private_weak_def_auto may have only default
visibility.  The symbols are removed by the linker from the final linked image
(executable or dynamic library).

llvm-svn: 111684
2010-08-20 22:05:50 +00:00
Bob Wilson 9a511c07e4 Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
zero-extend operations.

llvm-svn: 111614
2010-08-20 04:54:02 +00:00
Eric Christopher 985d9e4ea8 Fix loop conditionals (MO.isDef() asserts that it's a reg) and
move some constraints around.

llvm-svn: 111594
2010-08-20 00:36:24 +00:00
Eric Christopher d8e8a2945e Add a couple of random comments.
llvm-svn: 111592
2010-08-20 00:20:31 +00:00
Jim Grosbach 56e56323c8 Better handling of offsets on frame index references. rdar://8277890
llvm-svn: 111585
2010-08-19 23:52:25 +00:00
Jim Grosbach 8c58bd30dc Add Thumb1 support for virtual frame indices.
rdar://8277890

llvm-svn: 111533
2010-08-19 17:52:13 +00:00
Eric Christopher a5d60c62b1 Silence warning.
llvm-svn: 111518
2010-08-19 15:35:27 +00:00
Chris Lattner f547740d3f fix PR7465, mishandling of lcall and ljmp: intersegment long
call and jumps.

llvm-svn: 111496
2010-08-19 01:18:43 +00:00
Chris Lattner beb506eeed minor progress towards fixing PR7465
llvm-svn: 111494
2010-08-19 01:00:34 +00:00
Eric Christopher 0d274a0258 Add an AddOptionalDefs method and use it.
llvm-svn: 111489
2010-08-19 00:37:05 +00:00