56efafc056
[Hexagon] Moving pass declarations out of header and in to implementation files. Removing unused function getSubtargetInfo from HexagonMCCodeEmitter.cpp Removing deletion of copy construction and assignment operator since parent already deletes it.
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llvm-svn: 239744
2015-06-15 19:05:35 +00:00
6bbcb31fda
[Hexagon] Treat CFI as solo instructions
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llvm-svn: 235516
2015-04-22 15:47:35 +00:00
473e34782d
[Hexagon] Simplify boolean expression
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Patch by Richard
http://reviews.llvm.org/D8523
llvm-svn: 232955
2015-03-23 16:01:03 +00:00
7af9528747
Have getCalleeSavedRegs take a non-null MachineFunction all the
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time. The target independent code was passing in one all the
time and targets weren't checking validity before using. Update
a few calls to pass in a MachineFunction where necessary.
llvm-svn: 231970
2015-03-11 21:41:28 +00:00
4fd203d3e1
[Hexagon] Removing more V4 predicates since V4 is the required minimum.
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llvm-svn: 228614
2015-02-09 21:56:37 +00:00
b882f2b5cf
[Hexagon] Renaming Y2_barrier. Fixing issues where doubleword variants of instructions can't be newvalue producers.
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llvm-svn: 228330
2015-02-05 18:56:28 +00:00
2e3a26de0c
[Hexagon] Updating call/jump instruction patterns.
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llvm-svn: 226288
2015-01-16 17:05:27 +00:00
d7a56fd9ff
[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.
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llvm-svn: 224989
2014-12-30 15:44:17 +00:00
651b72095b
[Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores.
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llvm-svn: 224957
2014-12-29 21:33:45 +00:00
bda31b42a0
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.
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llvm-svn: 224952
2014-12-29 20:44:51 +00:00
ff370ed90e
[Hexagon] Adding deallocframe and circular addressing loads.
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llvm-svn: 224869
2014-12-26 20:30:58 +00:00
5ccbb1298b
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
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llvm-svn: 224556
2014-12-19 00:06:53 +00:00
174476ed96
Reverting 224550, was not ready for commit.
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llvm-svn: 224552
2014-12-18 23:36:15 +00:00
9000481cda
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
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llvm-svn: 224550
2014-12-18 23:27:51 +00:00
db0b13cef0
[Hexagon] Adding encodings for JR class instructions. Updating complier usages.
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llvm-svn: 223967
2014-12-10 21:24:10 +00:00
2a321f74f0
Remove the TargetMachine from DFAPacketizer since it was only
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being used to grab subtarget specific things that we can grab
from the MachineFunction anyhow.
llvm-svn: 219650
2014-10-14 01:03:16 +00:00
c6cc58e703
Remove unnecessary copying or replace it with moves in a bunch of places.
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NFC.
llvm-svn: 219061
2014-10-04 16:55:56 +00:00
ac3e325d67
Spelling correction
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Another trivial spelling change.
llvm-svn: 217364
2014-09-08 13:05:23 +00:00
ea0aee622e
Cleanup: Delete seemingly unused reference to MachineDominatorTree from ScheduleDAGInstrs.
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llvm-svn: 216124
2014-08-20 20:57:26 +00:00
fc6de428c8
Have MachineFunction cache a pointer to the subtarget to make lookups
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shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.
Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.
llvm-svn: 214838
2014-08-05 02:39:49 +00:00
d913448b38
Remove the TargetMachine forwards for TargetSubtargetInfo based
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information and update all callers. No functional change.
llvm-svn: 214781
2014-08-04 21:25:23 +00:00
906c2cd2e6
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition
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llvm-svn: 207508
2014-04-29 07:58:16 +00:00
062a2baef0
[C++] Use 'nullptr'. Target edition.
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llvm-svn: 207197
2014-04-25 05:30:21 +00:00
84e68b2994
[Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
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definition below all of the header #include lines, lib/Target/...
edition.
llvm-svn: 206842
2014-04-22 02:41:26 +00:00
840beec2d0
Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
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llvm-svn: 205610
2014-04-04 05:16:06 +00:00
b6d0bd48bd
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
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Remove the old functions.
llvm-svn: 202636
2014-03-02 12:27:27 +00:00
8a8cd2bab9
Re-sort all of the includes with ./utils/sort_includes.py so that
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subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.
Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.
llvm-svn: 198685
2014-01-07 11:48:04 +00:00
f907b891da
Correct word hyphenations
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This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.
llvm-svn: 196471
2013-12-05 05:44:44 +00:00
e79beacb32
Hexagon: Make helper functions static.
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llvm-svn: 182588
2013-05-23 15:43:11 +00:00
11bd54afd6
Hexagon: ArePredicatesComplement should not restrict itself to TFRs.
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llvm-svn: 181803
2013-05-14 16:36:34 +00:00
438cec566b
Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.
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No functionality change.
llvm-svn: 181628
2013-05-10 20:58:11 +00:00
300f0b966c
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
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llvm-svn: 181624
2013-05-10 20:27:34 +00:00
00681dc1f0
Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.
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No functionality change.
llvm-svn: 181535
2013-05-09 19:16:07 +00:00
18ee1193bf
Print IR from Hexagon MI passes with -print-before/after-all.
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llvm-svn: 181255
2013-05-06 21:58:00 +00:00
84c471029b
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
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llvm-svn: 181235
2013-05-06 18:49:23 +00:00
1d29750b7d
Hexagon: Honor __builtin_expect by using branch probabilities.
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* lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp):
Given a jump opcode return the right pred.new jump opcode with
a taken vs not-taken hint based on branch probabilities provided
by the target independent module.
* lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function.
* lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode):
Enhance existing function use branch probabilities like
HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps.
llvm-svn: 180923
2013-05-02 15:39:30 +00:00
5ed5181178
Hexagon: Use multiclass for Jump instructions.
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llvm-svn: 180885
2013-05-01 21:37:34 +00:00
a46059b74d
Hexagon: Replace switch-case in isDotNewInst with TSFlags.
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llvm-svn: 178281
2013-03-28 19:44:04 +00:00
f1214a8ab7
Hexagon: Use MO operand flags to mark constant extended instructions.
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llvm-svn: 176500
2013-03-05 18:51:42 +00:00
8425643728
Hexagon: Add constant extender support framework.
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llvm-svn: 176358
2013-03-01 17:37:13 +00:00
d92252469e
Hexagon: Use absolute addressing mode loads/stores for global+offset
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instead of redefining separate instructions for them.
llvm-svn: 175086
2013-02-13 21:38:46 +00:00
2ceafa6684
Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats".
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llvm-svn: 174193
2013-02-01 16:36:16 +00:00
bf75aaf53e
Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.
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llvm-svn: 170671
2012-12-20 06:45:39 +00:00
ed0881b2a6
Use the new script to sort the includes of every file under lib.
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Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
llvm-svn: 169131
2012-12-03 16:50:05 +00:00
cea3e77433
Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().
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Ordered memory operations are more constrained than volatile loads and
stores because they must be ordered with respect to all other memory
operations.
llvm-svn: 162861
2012-08-29 21:19:21 +00:00
8db5547252
Revert r158679 - use case is unclear (and it increases the memory footprint).
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Original commit message:
Allow up to 64 functional units per processor itinerary.
This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
This will be needed for some upcoming PowerPC itineraries.
llvm-svn: 159027
2012-06-22 20:27:13 +00:00
8eac009633
Allow up to 64 functional units per processor itinerary.
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This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
This will be needed for some upcoming PowerPC itineraries.
llvm-svn: 158679
2012-06-18 21:08:18 +00:00
f6b687e5d1
Revert 156634 upon request until code improvement changes are made.
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llvm-svn: 156775
2012-05-14 19:35:42 +00:00
95d0117bb3
Remove warnings from HexagonVLIWPacketizer.
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llvm-svn: 156636
2012-05-11 20:00:34 +00:00
31f8723ef3
Hexagon constant extender support.
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Patch by Jyotsna Verma.
llvm-svn: 156634
2012-05-11 19:56:59 +00:00
Colin LeMahieu