fa8667a2dd
Fix attribute handling.
...
llvm-svn: 48262
2008-03-12 00:07:03 +00:00
b398635456
Minor debug output bug.
...
llvm-svn: 48261
2008-03-12 00:02:46 +00:00
e6d90f5a95
Ultimately resolve aliases during linking, if possible
...
llvm-svn: 48259
2008-03-11 22:51:09 +00:00
e8fa50f63a
Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137
...
llvm-svn: 48257
2008-03-11 22:38:53 +00:00
24570836b2
Use PassManagerBase instead of FunctionPassManager for functions
...
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
llvm-svn: 48256
2008-03-11 22:29:46 +00:00
da7db7d9a1
Add helper for ultimate aliasee resoltion
...
llvm-svn: 48255
2008-03-11 22:28:56 +00:00
7358165c99
Handle multiple ret values.
...
llvm-svn: 48254
2008-03-11 22:24:29 +00:00
f6269f0914
Initialize.
...
llvm-svn: 48253
2008-03-11 22:08:21 +00:00
20af5a0fe7
Check to see if a two-entry PHI block can be simplified
...
before trying to merge the block into its predecessors.
This allows two-entry-phi-return.ll to be simplified
into a single basic block.
llvm-svn: 48252
2008-03-11 21:53:06 +00:00
2601d7ee50
Honour aliases visibility during asm emission
...
llvm-svn: 48249
2008-03-11 21:41:14 +00:00
db691cbd6d
Honour aliases visibility when reading from/writing to bitcode
...
llvm-svn: 48248
2008-03-11 21:40:17 +00:00
a3891365b5
Transfer physical register spill info when load / store folding happens.
...
llvm-svn: 48246
2008-03-11 21:34:46 +00:00
44b4c07cd1
Use the correct value for InSignBit.
...
llvm-svn: 48245
2008-03-11 21:29:43 +00:00
1351025a91
Initial codegen support for functions and calls with multiple return values.
...
llvm-svn: 48244
2008-03-11 21:11:25 +00:00
8abed80a69
Implement basic support for the 'f' register class constraint. This basically
...
works, but probably won't if you mix it with 't' or 'u' yet.
llvm-svn: 48243
2008-03-11 19:50:13 +00:00
7b27ccfd5e
coalesce away 80-bit floating point copies.
...
llvm-svn: 48241
2008-03-11 19:30:09 +00:00
7930d8e775
convert a massive if statement to a switch.
...
llvm-svn: 48240
2008-03-11 19:28:17 +00:00
120ad01fcb
start handling the 'f' x87 constraint.
...
llvm-svn: 48239
2008-03-11 19:06:29 +00:00
70c238a1d8
Skip functions that return multiple values.
...
llvm-svn: 48233
2008-03-11 18:04:06 +00:00
5663fe6613
Become multiple return value aware.
...
Right now, the pass does not optimize tail recursions
involving multiple return values.
llvm-svn: 48228
2008-03-11 17:33:32 +00:00
e418de3023
Add TODO reminder.
...
llvm-svn: 48227
2008-03-11 17:32:05 +00:00
d3a20c9e1e
Give PassManager and FunctionPassManager a common base class, with
...
add(Pass *) as a pure virtual member function. This will allow all
the various addPassesTo* functions in LLVM to avoid hard-coding what
type of PassManager is used.
llvm-svn: 48226
2008-03-11 16:41:42 +00:00
dfdf2c0633
Fix typos in comments.
...
llvm-svn: 48225
2008-03-11 16:18:48 +00:00
342e4104d3
Missed part of recommit.
...
llvm-svn: 48224
2008-03-11 10:27:36 +00:00
aa7c2105de
Recommitting parts of r48130. These do not appear to cause the observed failures.
...
llvm-svn: 48223
2008-03-11 10:09:17 +00:00
d54660aeed
Use TargetRegisterInfo::getPhysicalRegisterRegClass. Remove duplicated code.
...
llvm-svn: 48221
2008-03-11 07:55:13 +00:00
d85667b89c
If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_).
...
llvm-svn: 48220
2008-03-11 07:54:14 +00:00
e88a625ecd
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
...
llvm-svn: 48218
2008-03-11 07:19:34 +00:00
5b59e372dc
In 32-bit mode, mark 64-bit GPR's as unallocatable.
...
llvm-svn: 48217
2008-03-11 07:16:00 +00:00
b29f93613d
Some LegalizeTypes code factorization and minor
...
enhancements.
llvm-svn: 48215
2008-03-11 06:41:14 +00:00
5c7bda440f
compile: double test() {}
...
into:
_test:
fldz
ret
instead of:
_test:
subl $12, %esp
#IMPLICIT_DEF %xmm0
movsd %xmm0, (%esp)
fldl (%esp)
addl $12, %esp
ret
llvm-svn: 48213
2008-03-11 06:21:08 +00:00
a3860a2422
Fix the build on gcc 4.2.
...
llvm-svn: 48212
2008-03-11 05:56:09 +00:00
a7a2075ab8
Initial multiple return values support.
...
llvm-svn: 48210
2008-03-11 05:46:42 +00:00
1bd44363f2
Change the model for FP Stack return to use fp operands on the
...
RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
llvm-svn: 48209
2008-03-11 03:23:40 +00:00
3e0ec65678
variadic instructions don't have operand info for variadic arguments.
...
llvm-svn: 48208
2008-03-11 03:14:42 +00:00
d6819da453
Generalize ExpandIntToFP to handle the case where the operand is legal
...
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
llvm-svn: 48206
2008-03-11 01:59:03 +00:00
d3090bcfc8
If a register operand comes from the variadic part of a node, don't
...
verify the register constraint matches what the instruction expects.
llvm-svn: 48205
2008-03-11 00:59:28 +00:00
850e143cbf
Temporarily revert 48175.
...
llvm-svn: 48204
2008-03-11 00:27:34 +00:00
2591afca0a
Fix thinko: alias always defines new symbol. Even is aliasee itself is undefined.
...
llvm-svn: 48203
2008-03-11 00:24:53 +00:00
10f7d850cf
More APInt-ification.
...
llvm-svn: 48201
2008-03-11 00:11:06 +00:00
a4fa0ad30d
abort with an assert instead of a cerr to get line#
...
llvm-svn: 48199
2008-03-10 23:56:08 +00:00
fc42961f18
Use utostr instead of a stringstream.
...
llvm-svn: 48198
2008-03-10 23:55:07 +00:00
92275427e5
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
...
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
llvm-svn: 48197
2008-03-10 23:49:09 +00:00
2a3aeb1f72
Correctly clone FlaggedNodes.
...
llvm-svn: 48196
2008-03-10 23:48:14 +00:00
2f3648b261
Initialize ArgTypes directly instead of manually copying in the elements.
...
llvm-svn: 48195
2008-03-10 23:41:23 +00:00
830d86cab8
APInt-ify this.
...
llvm-svn: 48194
2008-03-10 23:38:17 +00:00
de66dc88cd
Remove an unnecessary #include
...
llvm-svn: 48193
2008-03-10 23:37:12 +00:00
7362d38391
Don't emit FP_REG_KILL into a block that just returns. Nothing
...
can be live out of the block anyway, so it isn't needed.
llvm-svn: 48192
2008-03-10 23:34:12 +00:00
f4300950f1
Implement more support for fp-to-i128 and i128-to-fp conversions.
...
llvm-svn: 48189
2008-03-10 23:03:31 +00:00
0fb187f81b
Disable prolog code that aligns the stack when a
...
local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
llvm-svn: 48188
2008-03-10 22:59:46 +00:00
c6c48fca74
Change the "enable/disable" mechanism so that we can enable PPC register
...
scavenging for 32-bit and 64-bit separately.
llvm-svn: 48186
2008-03-10 22:49:16 +00:00
510fc32d15
Add sanity checks
...
llvm-svn: 48184
2008-03-10 22:36:53 +00:00
d5160da577
Typo: 'function' => 'alias'
...
llvm-svn: 48183
2008-03-10 22:36:35 +00:00
66a6271c07
Syntactic sugar'ify stuff :)
...
llvm-svn: 48182
2008-03-10 22:36:08 +00:00
715ef43c2e
Always run 'make check' :) Fix fallout from prev. commit: query for possible
...
alias destination only if we don't have anything to link to
llvm-svn: 48181
2008-03-10 22:35:31 +00:00
eeb5ca6f5f
Make error messages to have common style
...
llvm-svn: 48180
2008-03-10 22:34:46 +00:00
e79f4c77f0
Properly link globals with aliases
...
llvm-svn: 48179
2008-03-10 22:34:28 +00:00
f6439246cc
Remove the LinkGlobal weirderness in common linking phase.
...
llvm-svn: 48177
2008-03-10 22:33:53 +00:00
1f93c50ace
Typo
...
llvm-svn: 48176
2008-03-10 22:33:22 +00:00
7abdb438a1
If the register allocator ran out of registers, just abort for now.
...
llvm-svn: 48175
2008-03-10 21:27:20 +00:00
4b3a7fa823
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
...
copyfromreg/copytoreg instead.
llvm-svn: 48174
2008-03-10 21:08:41 +00:00
272e234477
Fix mul expansion to check the correct number of bits for
...
zero extension when checking if an unsigned multiply is
safe.
llvm-svn: 48171
2008-03-10 20:42:19 +00:00
b9e4280e94
Somewhat better solution.
...
llvm-svn: 48170
2008-03-10 19:58:22 +00:00
ae2c56d93e
Default ISD::PREFETCH to expand.
...
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
d4e1d9eeb2
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
...
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
514b3ed536
fix 80 col violations.
...
llvm-svn: 48166
2008-03-10 18:55:53 +00:00
64d0f07085
Restore optimization that merges blocks when inline function
...
has single return value.
llvm-svn: 48162
2008-03-10 18:34:00 +00:00
72ea2dc9a9
Simplify
...
llvm-svn: 48161
2008-03-10 18:22:16 +00:00
c0325b2040
simplify
...
llvm-svn: 48160
2008-03-10 18:11:41 +00:00
708784ea4f
Stylistic modifications. No functionality changes.
...
llvm-svn: 48158
2008-03-10 17:46:45 +00:00
48e3375544
Integer comparison tests for CellSPU.
...
llvm-svn: 48152
2008-03-10 16:58:52 +00:00
cd4a6bed89
Fix formatting.
...
llvm-svn: 48151
2008-03-10 16:38:37 +00:00
a6729e8666
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
...
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
b1de7a35f9
Add description of individual bits in CR. This fix PR1765.
...
llvm-svn: 48143
2008-03-10 14:12:10 +00:00
2823eaebe8
Minor cleanup. No functionality change.
...
llvm-svn: 48142
2008-03-10 08:13:01 +00:00
4a3c5eab34
- Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where the source is defined; BLR is the live range which is defined by the copy.
...
If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
A = or A, B
...
B = A
...
C = A<kill>
...
= B
then do not add kills of A to the newly created B interval.
- Also fix some kill info update bug.
llvm-svn: 48141
2008-03-10 08:11:32 +00:00
831ae49599
Doh
...
llvm-svn: 48140
2008-03-10 07:59:01 +00:00
75d04819a6
Move StrongPHIElimination after live interval analysis. This will make things happier down the road.
...
llvm-svn: 48138
2008-03-10 07:22:36 +00:00
b5d11980d9
Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type (e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case.
...
llvm-svn: 48136
2008-03-10 07:19:13 +00:00
4ba3f0430b
Allow insert_subreg into implicit, target-specific values.
...
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
5cb21155e4
Update the .cvs files to match today's asm syntax change.
...
llvm-svn: 48128
2008-03-10 05:01:34 +00:00
fb2c1a999a
Turn unwind_to into "unwinds to".
...
llvm-svn: 48123
2008-03-10 02:20:00 +00:00
4e622ec86d
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
...
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
llvm-svn: 48122
2008-03-10 02:17:22 +00:00
aed9406bb7
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
...
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
llvm-svn: 48120
2008-03-09 20:49:33 +00:00
78e817d7fc
cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.
...
llvm-svn: 48119
2008-03-09 20:31:11 +00:00
3ba79ed9e8
make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll
...
llvm-svn: 48118
2008-03-09 20:12:44 +00:00
4c4234b59c
remove an extraneous (and ugly) default argument, thanks Duncan.
...
llvm-svn: 48117
2008-03-09 20:04:36 +00:00
d48ed17d18
Fix some compilation errors on msvc:
...
- "Redefinition of I" (iterator masks previous definition)
- include missing header file
Patch by Argiris Kirtzidis!
llvm-svn: 48115
2008-03-09 18:32:50 +00:00
0ac65c3b99
And again.
...
llvm-svn: 48112
2008-03-09 17:13:05 +00:00
929703b29e
Braces belong here. No functionality change.
...
llvm-svn: 48111
2008-03-09 17:11:18 +00:00
83750d9caf
SCCP also needs to be taught to follow unwind_to
...
llvm-svn: 48109
2008-03-09 09:44:38 +00:00
ce5f841bb5
fp_round's produced by getCopyFromParts should always be exact, because
...
they are produced by calls (which are known exact) and by cross block copies
which are known to be produced by extends.
This improves:
define double @test2() {
%tmp85 = call double asm sideeffect "fld0", "={st(0)}"()
ret double %tmp85
}
from:
_test2:
subl $20, %esp
# InlineAsm Start
fld0
# InlineAsm End
fstpl 8(%esp)
movsd 8(%esp), %xmm0
movsd %xmm0, (%esp)
fldl (%esp)
addl $20, %esp
#FP_REG_KILL
ret
to:
_test2:
# InlineAsm Start
fld0
# InlineAsm End
#FP_REG_KILL
ret
by avoiding a f64 <-> f80 trip
llvm-svn: 48108
2008-03-09 09:38:46 +00:00
86829f0ff7
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
...
an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
271506f29c
Don't eliminate blocks that are only reachable by unwind_to.
...
llvm-svn: 48106
2008-03-09 08:50:23 +00:00
9e07537e8c
Add ScheduleDAG support for copytoreg where the src/dst register are
...
in different register classes, e.g. copy of ST(0) to RFP*. This gets
some really trivial inline asm working that plops things on the top of
stack (PR879)
llvm-svn: 48105
2008-03-09 08:49:15 +00:00
b79bafcec8
add some code to support cross-register class copying from
...
RST -> RFP{32/64/80}. We only handle ST(0) for now.
llvm-svn: 48104
2008-03-09 08:46:19 +00:00
c4c9dde04c
rearrange some code, no functionality change.
...
llvm-svn: 48101
2008-03-09 07:58:04 +00:00
381bbdb924
fix 80 col violation
...
llvm-svn: 48100
2008-03-09 07:51:01 +00:00
42445be0df
Firstly, having a BranchInst isn't exclusive with having an unwind_to.
...
Secondly, we have to check whether the branch is actually pointing to the block
with the unwind in it. We could have gotten here because of the unwind_to alone.
llvm-svn: 48099
2008-03-09 07:50:37 +00:00
459f518703
claim ST(x) registers are 80 bits, which is true. This doesn't affect
...
codegen yet because these can't be spilled (they don't exist until after RA).
llvm-svn: 48098
2008-03-09 07:49:01 +00:00
83b3473dd8
extend fp values with FP_EXTEND not FP_ROUND.
...
llvm-svn: 48097
2008-03-09 07:47:22 +00:00
f3d637fa14
A BB that unwind_to an "unwind" inst is that same as one that doesn't unwind_to
...
at all.
llvm-svn: 48096
2008-03-09 07:36:38 +00:00
4c869594bc
rename FP_SETRESULT -> FP_SET_ST0
...
llvm-svn: 48094
2008-03-09 07:08:44 +00:00
d587e580a6
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
...
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
llvm-svn: 48093
2008-03-09 07:05:32 +00:00
b6387c8a74
Finish implementing a readme entry: when inserting an i64 variable
...
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48090
2008-03-09 05:42:06 +00:00
11fc6f8765
Update the block cloner which fixes bugpoint on code using unwind_to (phew!)
...
and also update the cloning interface's major user, the loop optimizations.
llvm-svn: 48088
2008-03-09 05:24:34 +00:00
5ce9b521d7
Update the inliner and simplifycfg to handle unwind_to.
...
llvm-svn: 48086
2008-03-09 05:10:13 +00:00
cc24104703
Two things. Preserve the unwind_to when splitting a BB.
...
Add the ability to remove just one instance of a BB from a phi node. This fixes
the compile error in the tree now.
llvm-svn: 48085
2008-03-09 05:04:48 +00:00
4d0ed842b1
Prune the unwind_to labels on BBs that don't need them. Another step in the
...
removal of invoke, PR1269.
llvm-svn: 48084
2008-03-09 04:55:16 +00:00
93930dc28c
add a note
...
llvm-svn: 48064
2008-03-09 01:08:22 +00:00
eef374c197
Implement a readme entry, compiling
...
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
llvm-svn: 48063
2008-03-09 01:05:04 +00:00
322c826c9d
Fix two problems in SelectionDAGLegalize::ExpandBUILD_VECTOR's handling
...
of BUILD_VECTORS that only have two unique elements:
1. The previous code was nondeterminstic, because it walked a map in
SDOperand order, which isn't determinstic.
2. The previous code didn't handle the case when one element was undef
very well. Now we ensure that the generated shuffle mask has the
undef vector on the RHS (instead of potentially being on the LHS)
and that any elements that refer to it are themselves undef. This
allows us to compile CodeGen/X86/vec_set-9.ll into:
_test3:
movd %rdi, %xmm0
punpcklqdq %xmm0, %xmm0
ret
instead of:
_test3:
movd %rdi, %xmm1
#IMPLICIT_DEF %xmm0
punpcklqdq %xmm1, %xmm0
ret
... saving a register.
llvm-svn: 48060
2008-03-09 00:29:42 +00:00
a1f25b0020
Teach SD some vector identities, allowing us to compile vec_set-9 into:
...
_test3:
movd %rdi, %xmm1
#IMPLICIT_DEF %xmm0
punpcklqdq %xmm1, %xmm0
ret
instead of:
_test3:
#IMPLICIT_DEF %rax
movd %rax, %xmm0
movd %rdi, %xmm1
punpcklqdq %xmm1, %xmm0
ret
This is still not ideal. There is no reason to two xmm regs.
llvm-svn: 48058
2008-03-08 23:43:36 +00:00
ad58828354
1) Improve comments.
...
2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48057
2008-03-08 22:59:52 +00:00
8a6ebd23a8
minor simplifications to this code, don't create a dead
...
SCALAR_TO_VECTOR on paths that end up not using it.
llvm-svn: 48056
2008-03-08 22:48:29 +00:00
35adf46967
This one looks easy, add a note.
...
llvm-svn: 48055
2008-03-08 22:32:39 +00:00
a76e23a935
move these to the appropriate file
...
llvm-svn: 48054
2008-03-08 22:28:45 +00:00
35e92c7bea
Not all users of a BB are Instructions any more.
...
llvm-svn: 48047
2008-03-08 07:48:41 +00:00
a53414fd79
Load the symbols first so that the interpreter constructor can find them when
...
it tries to initialize them.
llvm-svn: 48046
2008-03-08 02:49:45 +00:00
39b0ac4e59
Remove unused runPass methods.
...
llvm-svn: 48044
2008-03-08 01:43:56 +00:00
21a8f144a6
More ppc32 byval handling (bug fixes). Things
...
are looking pretty good now.
llvm-svn: 48043
2008-03-08 01:41:42 +00:00
95cf661534
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
...
llvm-svn: 48042
2008-03-08 00:58:38 +00:00
d2ab5fd713
Add support for calls with i128 return values on ppc64.
...
llvm-svn: 48041
2008-03-08 00:19:12 +00:00
d6951455e4
Something that kills a super-register also
...
kills the sub-register.
llvm-svn: 48038
2008-03-07 23:45:15 +00:00
4e97e94809
Fix a typo. It's causing consumer-typeset to miscompile. Perhaps more.
...
llvm-svn: 48035
2008-03-07 22:39:49 +00:00
968f32ce3d
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
...
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
llvm-svn: 48030
2008-03-07 20:49:02 +00:00
8d2ead2e34
Add support for lowering 128-bit shifts on ppc64.
...
llvm-svn: 48029
2008-03-07 20:36:53 +00:00
bfa252d402
Next bits of PPC byval handling. Basically functional
...
but there are bugs.
llvm-svn: 48028
2008-03-07 20:27:40 +00:00
20b5a2b037
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
...
llvm-svn: 48027
2008-03-07 20:18:24 +00:00
25ff7e217d
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
...
with 32 or 64-bit operands/results.
llvm-svn: 48026
2008-03-07 20:13:51 +00:00
39a3221e27
Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI.
...
llvm-svn: 48024
2008-03-07 20:12:54 +00:00
780b3ca64b
Update inliner to handle functions that return multiple values.
...
llvm-svn: 48020
2008-03-07 20:06:16 +00:00
c1969de3e9
fix 80 col violations
...
llvm-svn: 48019
2008-03-07 20:05:43 +00:00
3f13b6630a
add a pass that can extract all kinds of global values, not just functions. Update llvm-extract to use it and optionally extract a global variable if you want it too
...
llvm-svn: 48015
2008-03-07 19:51:57 +00:00
e8a3e74b6c
Clarify some important bits
...
llvm-svn: 48010
2008-03-07 18:34:50 +00:00
0074ea3ae7
Small cleanup: propagate thread-localness via generic routine.
...
No functionality change.
llvm-svn: 48009
2008-03-07 18:32:18 +00:00
d4defb00df
mark frem as expand for all legal fp types on x86, regardless of whether
...
we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
2008-03-07 06:36:32 +00:00
55bfd8c3f7
When setting the "unused" info, take into account something like this:
...
%r3<def> = OR %x3<kill>, %x3
We don't want to mark the %r3 as unused even though it's a sub-register of %x3.
llvm-svn: 48003
2008-03-06 23:22:43 +00:00
34173f0a43
80 col violation.
...
llvm-svn: 47998
2008-03-06 17:42:34 +00:00
636ab19205
some more spelling changes
...
llvm-svn: 47996
2008-03-06 10:51:21 +00:00
ad19df0687
fix typos
...
llvm-svn: 47994
2008-03-06 10:36:00 +00:00
a3cb090446
Constant fold SIGN_EXTEND_INREG with ashr not lshr.
...
llvm-svn: 47992
2008-03-06 08:20:51 +00:00
d0b62a1552
Don't try to simplify urem and srem using arithmetic rules that don't work
...
under modulo (overflow). Fixes PR1933.
llvm-svn: 47987
2008-03-06 06:48:30 +00:00
e9b690b7f1
Refine Cell's i64 constant generation code to cover more constants where the
...
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
llvm-svn: 47985
2008-03-06 04:02:54 +00:00
dcabdb1b38
gcc likes things spelled correctly
...
llvm-svn: 47981
2008-03-05 23:41:37 +00:00
26cabc447c
Skip, for now, callsites where use of sret argument is not dominated by callsite.
...
llvm-svn: 47980
2008-03-05 23:39:23 +00:00
0d235052d1
Next bit of PPC ByVal handling; call-site code seems
...
correct now.
llvm-svn: 47978
2008-03-05 23:31:27 +00:00
2609888f29
Missed patch from my last commit
...
llvm-svn: 47977
2008-03-05 23:21:39 +00:00
e43711d392
Resolve aliases to aliasees, where possible
...
llvm-svn: 47975
2008-03-05 23:08:47 +00:00
24f65c3ab7
Handle functions as targets during linking of aliases as well
...
llvm-svn: 47974
2008-03-05 23:08:16 +00:00
42f56b4838
- Fix support for "special" i64 immediates that can be loaded
...
using IL, ILA, et. al. v2i64 and i64 are now supported by
the select bits (SELB) instruction.
- Add missing comparison operations (testcase forthcoming)
- More multiclass refactoring.
llvm-svn: 47973
2008-03-05 23:02:02 +00:00
dac5fa94ef
Try hard to link aliases. Checks can be too strict by now.
...
llvm-svn: 47968
2008-03-05 22:22:46 +00:00
29b502e0e0
Fix a coalescer bug wrt how dead copy interval is shortened.
...
llvm-svn: 47966
2008-03-05 22:09:42 +00:00
3b1c95f885
Handle 'ret' with multiple values.
...
llvm-svn: 47965
2008-03-05 21:50:24 +00:00
c3d98074a9
Add Hybrid Cycle Detection to Andersen's analysis.
...
Patch by Curtis Dunham.
llvm-svn: 47959
2008-03-05 19:31:47 +00:00
8ee39c61f2
Clarify that CALLSEQ_START..END may not be nested,
...
and add some protection against creating such.
llvm-svn: 47957
2008-03-05 19:14:03 +00:00
7c08a01698
evan implemented this.
...
llvm-svn: 47948
2008-03-05 17:11:51 +00:00
2e13597f9d
Remember the source->dest mapping when copying aliases. This fixes PR2054
...
llvm-svn: 47945
2008-03-05 15:27:21 +00:00
12cee7195f
Clarify the state-of-the-art
...
llvm-svn: 47944
2008-03-05 15:11:00 +00:00
3ea44e4ee9
isTwoAddress = 1 -> Constraints.
...
llvm-svn: 47941
2008-03-05 08:19:16 +00:00
6ec7dc6bea
PSLLWri etc. are two-address instructions.
...
llvm-svn: 47940
2008-03-05 08:11:27 +00:00
2acd0c25f6
add a note
...
llvm-svn: 47939
2008-03-05 07:22:39 +00:00
78e9cab229
Generalize FP constant shrinking optimization to apply to any vt
...
except ppc long double. This allows us to shrink constant pool
entries for x86 long double constants, which in turn allows us to
use flds/fldl instead of fldt.
llvm-svn: 47938
2008-03-05 06:48:13 +00:00
3dc3899007
Improve comment, pass in the original VT so that we can shrink a long double constant
...
all the way to float, not stopping at double.
llvm-svn: 47937
2008-03-05 06:46:58 +00:00
3bd59641ac
Ignore debugging related instructions if they get this far.
...
llvm-svn: 47934
2008-03-05 02:34:36 +00:00
801bfb2cf7
Rather than asserting. Dump out the MI that we are not able to encode and abort.
...
llvm-svn: 47933
2008-03-05 02:08:03 +00:00
da7897c4e1
Codegen support for i128 UINT_TO_FP. This just fixes a
...
bug in r47928 (Int64Ty is the correct type for the constant
pool entry here) and removes the asserts, now that the code
is capable of handling i128.
llvm-svn: 47932
2008-03-05 02:07:31 +00:00
0a62cb44ce
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
...
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
llvm-svn: 47931
2008-03-05 01:30:59 +00:00
357061a74d
64bit CAS on 32bit x86.
...
llvm-svn: 47929
2008-03-05 01:15:49 +00:00
d9d874b0cd
Codegen support for i128 SINT_TO_FP.
...
llvm-svn: 47928
2008-03-05 01:08:17 +00:00
6325446666
Refactor code. Remove duplicated functions that basically do the same thing as
...
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
2008-03-05 00:59:57 +00:00
e516aa1127
Skip functions that return multiple values.
...
llvm-svn: 47924
2008-03-05 00:36:59 +00:00
b3ca38c1d5
Check struct return type first.
...
llvm-svn: 47922
2008-03-05 00:27:05 +00:00
3fcd946c26
Removed spurious EnablePPCRS check.
...
llvm-svn: 47918
2008-03-04 23:27:33 +00:00
85d41a1c44
Move PPC lowering functions into PPCTargetLowering
...
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
llvm-svn: 47917
2008-03-04 23:17:14 +00:00
1af20ad336
Use a command-line option to turn register scavenging on/off for PPC.
...
llvm-svn: 47915
2008-03-04 23:13:51 +00:00
ce556d908b
Print types for all ret operands.
...
llvm-svn: 47911
2008-03-04 22:05:14 +00:00
4566d885dd
Use while loop.
...
llvm-svn: 47909
2008-03-04 21:59:49 +00:00
b2fae1d13f
Revert SmallVector ctor variants.
...
llvm-svn: 47908
2008-03-04 21:54:56 +00:00
941ab37ea8
Use cast instead of dyn_cast.
...
Update test to use multiple return value directly, instead of relying on -sretpromotion.
llvm-svn: 47907
2008-03-04 21:45:28 +00:00
ea4cb89d34
Filter nested structs
...
llvm-svn: 47906
2008-03-04 21:32:09 +00:00
841322b32a
Handle multiple return values.
...
llvm-svn: 47904
2008-03-04 21:15:15 +00:00
4fee9f35b5
x86-64 atomics
...
llvm-svn: 47903
2008-03-04 21:13:33 +00:00
28179f764c
Properly populate lists of defined/undefined symbols in presence of aliases
...
llvm-svn: 47900
2008-03-04 20:16:11 +00:00
d72ade3b3b
Add alias with non-external aliasee to the list of exported symbols of the library.
...
llvm-svn: 47899
2008-03-04 20:15:35 +00:00
297ea0de75
Use appropriate index to get the result value.
...
llvm-svn: 47897
2008-03-04 19:22:54 +00:00
748c77f530
Skip sret attribute while preparing attribute list for
...
new function and new call sites.
llvm-svn: 47896
2008-03-04 19:12:58 +00:00
5dc63480db
Add FunctionType ctor variant that takes SmallVector params.
...
llvm-svn: 47895
2008-03-04 18:57:05 +00:00
ed6e4b0b7d
Increment counter that keeps track of total number of sret promoted.
...
llvm-svn: 47892
2008-03-04 17:48:11 +00:00
6bb36e686d
Skip declarations.
...
llvm-svn: 47890
2008-03-04 17:47:06 +00:00
5b69f3fa33
Process externally visible functions also. Later on code generator will do the right thing.
...
llvm-svn: 47889
2008-03-04 17:46:26 +00:00
ecce5af83d
Collect statistics.
...
llvm-svn: 47888
2008-03-04 17:44:37 +00:00
c62c2bb4d0
Some improvements related to the computation of heights, depths of SUnits.
...
The basic idea is that all these algorithms are computing the longest paths from the root node or to the exit node. Therefore the existing implementation that uses and iterative and potentially
exponential algorithm was changed to a well-known graph algorithm based on dynamic programming. It has a linear run-time.
llvm-svn: 47884
2008-03-04 11:19:43 +00:00
38caf77419
Refactor ExpandConstantFP so it can optimize load from constpool of types larger than f64 into extload from smaller types.
...
llvm-svn: 47883
2008-03-04 08:05:30 +00:00
59d58ab8c4
80 column violations.
...
llvm-svn: 47878
2008-03-04 03:20:06 +00:00
2ae707888b
Did I say 'e = getNumOperands()'? I meant --e, of course.
...
llvm-svn: 47875
2008-03-04 00:48:15 +00:00
567d2e5b57
Rename isOperand() to isOperandOf() (and other similar methods). It always confuses me.
...
llvm-svn: 47872
2008-03-04 00:41:45 +00:00
33ff36321e
Remove -always-fold-and-in-test.
...
llvm-svn: 47871
2008-03-04 00:40:35 +00:00
0e541ea730
Miscellaneous clean-ups based on Evan's feedback:
...
- Cleaned up how the prologue-epilogue inserter loops over the instructions.
- Instead of restarting the processing of an instruction if we remove an
implicit kill, just update the end iterator and make sure that the iterator
isn't incremented.
llvm-svn: 47870
2008-03-03 23:57:28 +00:00
e1c4f99549
Misc. APInt-ification in the DAGCombiner.
...
llvm-svn: 47869
2008-03-03 23:51:38 +00:00
10f34077f1
More APInt-ification.
...
llvm-svn: 47868
2008-03-03 23:35:36 +00:00
0e238dc813
Yet more APInt-ification.
...
llvm-svn: 47867
2008-03-03 22:37:52 +00:00
2fa65b7997
More APInt-ification.
...
llvm-svn: 47866
2008-03-03 22:22:56 +00:00
a986eea82f
Add support for lowering i64 SRA_PARTS and friends on x86-64.
...
llvm-svn: 47865
2008-03-03 22:22:09 +00:00
f2bbfa3ba0
More APInt-ification.
...
llvm-svn: 47864
2008-03-03 22:20:46 +00:00
632ea65072
This is the initial check-in for adding register scavenging to PPC. (Currently,
...
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
llvm-svn: 47863
2008-03-03 22:19:16 +00:00
7921ad0d67
Go through the machine instruction's operands to make sure that we're not
...
marking both a super- and sub-register as "killed". This removes implicit uses
that are marked as "killed".
llvm-svn: 47862
2008-03-03 22:14:33 +00:00
528083bc28
Make the register scavenger update the bookkeeping values for sub/super
...
registers.
llvm-svn: 47861
2008-03-03 22:12:25 +00:00
4836d58f89
Multiple instructions can be inserted when eliminating frame indexes. We need
...
the register scavenger to process all of those new instructions instead of just
the last one inserted.
llvm-svn: 47860
2008-03-03 22:11:16 +00:00
9d91785987
s/isReturnStruct()/hasStructRetAttr()/g
...
llvm-svn: 47857
2008-03-03 21:46:28 +00:00
83558f9f46
regenerate.
...
llvm-svn: 47849
2008-03-03 18:58:47 +00:00
c6b56c79aa
If a function uses multive values in ret instruction then it
...
is returning a struct value.
llvm-svn: 47848
2008-03-03 18:58:16 +00:00
b0faf89133
Preserve paramater attributes.
...
llvm-svn: 47847
2008-03-03 18:36:03 +00:00
e209be4985
Stub out a Path::GetMainExecutable call to find the path to the
...
main executable of a program. This needs to be implemented on windows.
llvm-svn: 47835
2008-03-03 02:55:43 +00:00
d51372aa96
another random note
...
llvm-svn: 47831
2008-03-02 19:29:42 +00:00
6b0a189225
add a note
...
llvm-svn: 47830
2008-03-02 19:27:34 +00:00
a70df9e2ee
Evan implemented these.
...
llvm-svn: 47828
2008-03-02 18:05:14 +00:00
bd0bb3f07f
Evan implemented this.
...
llvm-svn: 47827
2008-03-02 17:56:29 +00:00
c93b48caeb
add support for lvsl, fixing PR1481
...
llvm-svn: 47825
2008-03-02 08:54:27 +00:00
8fb4c98284
add support for the sse.cmp.* intrinsics, which fixes sse.isamax with the CBE.
...
llvm-svn: 47824
2008-03-02 08:47:13 +00:00
9044719798
refactor intrinsic handling code out into its own method.
...
llvm-svn: 47823
2008-03-02 08:29:41 +00:00
2541f1dac6
fix printing of undef vectors, this fixes "simple" and "build" in UnitTests/Vector.
...
Now they all pass.
llvm-svn: 47820
2008-03-02 08:14:45 +00:00
4c058b39e4
insertelement got the wrong operands.
...
llvm-svn: 47819
2008-03-02 08:10:16 +00:00
051709436e
Several changes:
...
* Simplify handling of byval, making it easier to understand and more
consistent. This fixes PR2065.
* Clean up and simplify handling of GEPs. I can actually understand it now!
* Implement support for GEP'ing into vectors, this fixes
SingleSource/UnitTests/Vector/build2 among others.
llvm-svn: 47818
2008-03-02 08:07:24 +00:00
9140fba6ad
Fix a bug I introduced in constant array and constant vector handling.
...
llvm-svn: 47816
2008-03-02 05:46:57 +00:00
7295bc15a0
implement shufflevector.
...
llvm-svn: 47815
2008-03-02 05:41:07 +00:00
f724e34ddc
Add a new ShuffleVectorInst::getMaskValue method.
...
llvm-svn: 47813
2008-03-02 05:28:33 +00:00
689d830b6d
implement extractelement.
...
llvm-svn: 47812
2008-03-02 03:57:08 +00:00
d9cc003b0d
implement insertelement.
...
llvm-svn: 47811
2008-03-02 03:52:39 +00:00
92d929c21d
respect isSigned for vector types, fixing sdiv of vectors etc.
...
llvm-svn: 47810
2008-03-02 03:41:23 +00:00
fe1083be61
print the attribute in the right place, this fixes function returning vectors.
...
llvm-svn: 47809
2008-03-02 03:39:43 +00:00
d861066d15
vector types are simple types. This fixes div/rem of vectors.
...
llvm-svn: 47807
2008-03-02 03:33:31 +00:00
b104be599a
Print vector types appropriately. This gets basic vector code working
...
(PR1126)
llvm-svn: 47806
2008-03-02 03:29:50 +00:00
c8d974a323
rename PT -> VT for VectorTypes.
...
llvm-svn: 47805
2008-03-02 03:18:46 +00:00
895aef4720
Print i32/i64 integer constants as 1u instead of ((unsigned int)1).
...
Use dyn_cast better.
llvm-svn: 47804
2008-03-02 03:16:38 +00:00
647c6642e7
Move pr717 to here.
...
llvm-svn: 47803
2008-03-02 02:51:40 +00:00
3cc9be0b59
Add an unwind_to field to basic blocks, making them Users instead of Values.
...
This is the first checkin for PR1269, the new EH infrastructure.
llvm-svn: 47802
2008-03-02 02:48:09 +00:00
20bcdba9ca
good catch anton
...
llvm-svn: 47800
2008-03-01 23:18:21 +00:00
f5c90ec12c
make CAS work
...
llvm-svn: 47799
2008-03-01 22:27:48 +00:00
d032c33300
all but CAS working on x86
...
llvm-svn: 47798
2008-03-01 21:52:34 +00:00
7f6e95a973
Print the name, not a pointer.
...
llvm-svn: 47796
2008-03-01 17:20:55 +00:00
0070dd1de3
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
...
llvm-svn: 47795
2008-03-01 13:37:02 +00:00
ffe0da0eb2
Fix PR2113 by verifying allocations.
...
llvm-svn: 47792
2008-03-01 09:01:57 +00:00
a683edb2d8
allow specified inline threshold to be negative, as the value is
...
itself sometimes negative.
llvm-svn: 47786
2008-03-01 08:09:51 +00:00
208cc8f1b9
Add MVT::is128BitVector and is64BitVector. Shrink
...
unaligned load/store code using them. Per review
of unaligned load/store vector patch.
llvm-svn: 47782
2008-03-01 03:40:57 +00:00
73bdf043a1
Refactor / clean up code; remove td list scheduler special tie breaker (no real benefit).
...
llvm-svn: 47779
2008-03-01 00:39:47 +00:00
e8ddaba169
Fix cut-n-pasto.
...
llvm-svn: 47777
2008-02-29 23:41:13 +00:00
4eedfd2421
Add pass to promote sret.
...
This pass transforms
%struct._Point = type { i32, i32, i32, i32, i32, i32 }
define internal void @foo(%struct._Point* sret %agg.result)
into
%struct._Point = type { i32, i32, i32, i32, i32, i32 }
define internal %struct._Point @foo()
This pass updates foo() clients appropriately to use
getresult instruction to extract return values.
This pass is not yet ready for prime time.
llvm-svn: 47776
2008-02-29 23:34:08 +00:00
0e8b146152
Use enumeration for preffered EH dwarf encoding reason
...
llvm-svn: 47770
2008-02-29 22:09:08 +00:00
26edb59d97
Don't fill eh frames even though these are text sections.
...
llvm-svn: 47765
2008-02-29 19:36:59 +00:00
Devang Patel