bbba76fc99
Add intrinsics to match mmx shift builtin's with immediate operand.
...
llvm-svn: 48569
2008-03-19 23:38:52 +00:00
b727960f78
Add comment.
...
llvm-svn: 48567
2008-03-19 23:05:52 +00:00
fbf53a4d1d
#if 1 .. #endif markers do not add any value.
...
llvm-svn: 48560
2008-03-19 22:24:25 +00:00
a90fdc4340
Remove dead options.
...
llvm-svn: 48556
2008-03-19 22:02:26 +00:00
718da668ab
PassInfo keep tracks whether a pass is an analysis pass or not.
...
llvm-svn: 48554
2008-03-19 21:56:59 +00:00
b9056838d2
Add support for multiple return values for the PPC target by
...
converting call result lowering to use the CallingConvLowering
infastructure.
llvm-svn: 48552
2008-03-19 21:39:28 +00:00
7da2bceb3b
Don't loose incoming argument registers. Fix documentation style.
...
llvm-svn: 48545
2008-03-19 16:39:45 +00:00
8fe9109469
Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.
...
llvm-svn: 48542
2008-03-19 08:30:06 +00:00
f5ec84c4f3
add some convenience methods for creating GEP instructions and
...
struct types. Patch by David Chisnall, with some tweaks.
llvm-svn: 48531
2008-03-19 05:06:05 +00:00
054817ce06
C bindings for Module-, Function-, and BasicBlock::iterator.
...
llvm-svn: 48528
2008-03-19 03:47:18 +00:00
56e9e57d28
Fixed a coalescer bug caused by a typo.
...
llvm-svn: 48526
2008-03-19 02:26:36 +00:00
265f780c22
C and Objective Caml bindings for the various getParent methods of the IR.
...
Based on Erick Tryzelaar's patch.
llvm-svn: 48523
2008-03-19 01:11:35 +00:00
44c0b4f754
Fix live variables issues:
...
1. If part of a register is re-defined, an implicit kill and an implicit def are added to denote read / mod / write. However, this should only be necessary if the register is actually read later. This is a performance issue.
2. If a sub-register is being defined, and it doesn't have a previous use, do not add a implicit kill to the last use of a super-register:
= EAX, AX<imp-use,kill>
...
AX =
In this case, EAX is live but AX is killed, this is wrong and will cause the coalescer to do bad things.
llvm-svn: 48521
2008-03-19 00:52:20 +00:00
af75ab8130
Do not use virtual function to identify an analysis pass.
...
llvm-svn: 48520
2008-03-19 00:48:41 +00:00
2f6ab65d77
On Darwin, GCC issues a ".globl" for something that has a "visibility protected"
...
attribute instead of ".protected".
llvm-svn: 48516
2008-03-18 23:38:12 +00:00
484064370a
Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it!
...
llvm-svn: 48515
2008-03-18 23:36:35 +00:00
efb4d9ef80
Temporarily revert r48491. It's breaking test/CodeGen/X86/xorl.ll.
...
llvm-svn: 48510
2008-03-18 22:29:51 +00:00
5fef9aea12
Fix PR 2160 by making sure arguments to external functions get marked as pointing to anything
...
llvm-svn: 48509
2008-03-18 22:22:53 +00:00
12c76db312
Make conversions of i8/i16 to ppcf128 work.
...
llvm-svn: 48493
2008-03-18 17:28:38 +00:00
08ef1b2bdb
Dial down gcc's warnings: don't use 0UL when 0U suffices (and when the
...
variables and methods themselves only use unsigned.)
llvm-svn: 48492
2008-03-18 16:55:06 +00:00
3e408d4d82
Target independent DAG transform to use truncate for field extraction + sign extend on targets where this is profitable. Passes nightly on x86-64.
...
llvm-svn: 48491
2008-03-18 16:46:39 +00:00
d096ec0a86
Rewrite code that propagate isDead information after a dead copy is coalesced. This remove some ugly spaghetti code and fixed a number of subtle bugs.
...
llvm-svn: 48490
2008-03-18 08:26:47 +00:00
864970e9b6
Identify Analysis pass.
...
Do not run analysis pass again if analysis info is still available.
This fixes PR1441.
llvm-svn: 48476
2008-03-18 00:39:19 +00:00
924ca7f01d
Update heuritics that estimates cost of call instructions.
...
llvm-svn: 48474
2008-03-17 23:41:20 +00:00
cf87e71053
Make Complex long long/double/long double work
...
in ppc64 mode.
llvm-svn: 48459
2008-03-17 17:11:08 +00:00
7d4152bda6
Check in some #ifdef'd out code switching call argument
...
lowering over to SparcCallingConv.td. We can't make the switch
yet because we can't say to pass f64 registers in 2 x i32 registers
with the td file yet.
llvm-svn: 48449
2008-03-17 06:58:37 +00:00
52f16deb65
minor cleanups
...
llvm-svn: 48448
2008-03-17 06:57:02 +00:00
24bc123e80
Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48447
2008-03-17 06:56:52 +00:00
488e645938
A first attempt at updating live intervals, with code lifted from
...
the coalescer. This doesn't really work, but gets us farther than
before.
llvm-svn: 48446
2008-03-17 06:08:26 +00:00
4eabbb8f11
remove dead code
...
llvm-svn: 48445
2008-03-17 06:04:10 +00:00
db26db2158
Switch sparc from using LowerCallTo to using LowerOperation(CALL) like
...
other targets. Use autogenerated calling conv to lower result of
calls.
llvm-svn: 48444
2008-03-17 06:01:07 +00:00
49b269d780
Start moving sparc to use SparcCallingConv.td, switching over
...
return lowering first. This fixes a bug where the top and bottom
of i64 values were returned in the wrong registers before.
llvm-svn: 48443
2008-03-17 05:41:48 +00:00
0a1762e374
split sparc lowering out into SparcISelLowering.{cpp|h} to follow
...
best practices.
llvm-svn: 48442
2008-03-17 03:21:36 +00:00
5c5597a572
refactor the LowerOperation code out to individual functions for
...
each lowering, which is 'best practice'.
llvm-svn: 48441
2008-03-17 02:52:07 +00:00
92dcf1e0c2
Next round of PPC32 ABI changes. Allow for gcc
...
behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be. Handle complex long long
and complex double (4 and 8 return regs).
llvm-svn: 48439
2008-03-17 02:13:43 +00:00
af8d3c6699
various rotate fun.
...
llvm-svn: 48438
2008-03-17 01:47:51 +00:00
9030ecec88
Add a couple missing SSE4 instructions
...
llvm-svn: 48430
2008-03-16 21:14:46 +00:00
ab4b7d36cd
C and Objective Caml bindings for the TargetData class.
...
llvm-svn: 48422
2008-03-16 20:08:03 +00:00
9a11a0174f
Add assert for non-hexadecimal radixes.
...
llvm-svn: 48421
2008-03-16 20:05:52 +00:00
82a0e74f43
C and Objective Caml bindings for several scalar transforms.
...
Patch originally by Erick Tryzelaar, but has been modified somewhat.
llvm-svn: 48419
2008-03-16 16:32:40 +00:00
878114bf16
C and Objective Caml bindings for PassManagers.
...
llvm-svn: 48413
2008-03-16 04:20:44 +00:00
d3d0ad3f58
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
...
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
ec7533b620
Remove isImplicitDef TargetInstrDesc flag.
...
llvm-svn: 48381
2008-03-15 00:19:36 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
6c6075e326
Expose Module::dump via C and Ocaml.
...
Patch by Erick Tryzelaar.
llvm-svn: 48379
2008-03-14 23:58:56 +00:00
858e6385f7
Do not generate special entries in the dwarf eh
...
table for nounwind calls.
llvm-svn: 48373
2008-03-14 21:36:24 +00:00
84aec09fdb
Fix PR2138. Apparently any modification to a std::multimap (including remove entries for a different key) can invalidate multimap iterators.
...
llvm-svn: 48371
2008-03-14 20:44:01 +00:00
bb8c2406dc
this was removed from the Unix side.
...
llvm-svn: 48370
2008-03-14 20:41:50 +00:00
94f57c56f9
Update comments; getPassName no longer uses RTTI.
...
llvm-svn: 48369
2008-03-14 18:27:04 +00:00
0dfd3f33f7
Implement the real calling convention for ppc32 Altivec:
...
vectors go at the end of the memory area, after all
non-vector parameters.
llvm-svn: 48364
2008-03-14 17:41:26 +00:00
5be52a6053
Fix some 80 col violations.
...
llvm-svn: 48361
2008-03-14 07:46:48 +00:00
96bdbd6c5d
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
...
llvm-svn: 48360
2008-03-14 07:39:27 +00:00
77c8da7f00
Add debugging stuff.
...
llvm-svn: 48359
2008-03-14 07:13:42 +00:00
477d0f5294
Add an issue that is preventing instcombine from doing a simplification.
...
llvm-svn: 48356
2008-03-14 06:00:19 +00:00
a06e4f3050
Simplify using getIntPtrConstant.
...
llvm-svn: 48355
2008-03-14 05:23:57 +00:00
68a930b33e
The inst combining of inttoptr into GEP with one index was using the bit size of
...
the type instead of the byte size. This was causing troublesome mis-compilations.
True to form, this took 2 days to find and is a one-line fix. :-P
llvm-svn: 48354
2008-03-14 05:12:19 +00:00
63eb03f800
Tabs -> spaces
...
Use getIntPtrConstant in a couple places to shorten stuff up
Handle splitting vector shuffles with undefs in the mask
llvm-svn: 48351
2008-03-14 00:53:31 +00:00
db443ca377
Livein copy scheduling fixes: do not coalesce physical register copies, correctly determine the safe location to insert the copies.
...
llvm-svn: 48348
2008-03-14 00:14:55 +00:00
eac0c96371
Use SDTNone instead of duplicating it.
...
llvm-svn: 48346
2008-03-13 23:07:40 +00:00
b72127ac4c
More APInt-ification.
...
llvm-svn: 48344
2008-03-13 22:13:53 +00:00
7a69e3aef3
Fix a bug in GVN that Duncan noticed, where we potentially need to insert a
...
pointer bitcast when performing return slot optimization.
llvm-svn: 48343
2008-03-13 22:07:10 +00:00
e21a68bca7
Undo tweak. It had no obvious benefit.
...
llvm-svn: 48341
2008-03-13 17:42:48 +00:00
af305d2342
Remove unused GetAddressOfSymbol()
...
Thanks Daniel Dunbar!
llvm-svn: 48340
2008-03-13 16:55:34 +00:00
57bb088542
Typo.
...
llvm-svn: 48337
2008-03-13 08:04:35 +00:00
8f8a8b28e9
Don't try to sink 3-address instruction if convertToThreeAddress created more than one instructions.
...
llvm-svn: 48336
2008-03-13 07:56:58 +00:00
21449c76bc
Remove an unused command line option.
...
llvm-svn: 48334
2008-03-13 06:38:28 +00:00
5c26bde55e
TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one.
...
llvm-svn: 48333
2008-03-13 06:37:55 +00:00
dd55d3f1b2
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
...
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
02e727ff88
Fix Path::GetMainExecutable on cygwin, patch by Sam Bishop.
...
llvm-svn: 48328
2008-03-13 05:22:05 +00:00
4dec91222a
remove extraneous namespace qualifier, PR2142
...
llvm-svn: 48327
2008-03-13 05:17:59 +00:00
c994c0295a
move a bunch of trivial methods to be inline.
...
llvm-svn: 48326
2008-03-13 05:00:21 +00:00
4d650c4bee
Various improvements suggested by Duncan
...
llvm-svn: 48325
2008-03-13 04:33:03 +00:00
7698bfbe16
Update -mem2reg to use succ_iterator instead of iterating across TerminatorInst
...
successors. This makes it support nounwind.
llvm-svn: 48320
2008-03-13 02:42:41 +00:00
4f610c0de1
Remove unused options.
...
llvm-svn: 48319
2008-03-13 02:41:34 +00:00
565df95a36
Eliminate a few unnecessary uses of dynamic_cast.
...
llvm-svn: 48318
2008-03-13 02:08:36 +00:00
1e9860a2ed
Fix a typo.
...
llvm-svn: 48317
2008-03-13 01:58:48 +00:00
1412f515c3
Don't redundantly clear std::vector members in destructors.
...
llvm-svn: 48316
2008-03-13 01:57:34 +00:00
73caf5ff10
Change PMTopLevelManager's PassManagers vector element type from
...
Pass* to PMDataManager*. PMDataManager is more specific than Pass,
so this more accurately describes the objects that are being stored.
This eliminates the need for several dynamic_casts to PMDataManager*.
It does introduce one dynamic_cast though, in dumpPasses(). Give
this one a comment describing why a dynamic_cast is being used.
llvm-svn: 48315
2008-03-13 01:48:32 +00:00
11eecd635c
Change PMStack::push to accept a PMDataManager* instead of
...
a Pass*. PMDataManager* is what it actually holds, so this
makes it clearer.
llvm-svn: 48314
2008-03-13 01:21:31 +00:00
399e1101ba
Refactor some code out of MachineSink into a MachineInstr query.
...
llvm-svn: 48311
2008-03-13 00:44:09 +00:00
6424bd0b11
Do not promote float params to double in varargs
...
calls here. This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.
llvm-svn: 48310
2008-03-12 23:40:01 +00:00
65e9d5f1a8
Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted:
...
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
%reg1031<def> = MOVPC32r 0
%reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
%reg1028<def> = MOV32rr %EAX
%reg1029<def> = MOV32rr %EDX
%reg1030<def> = MOV32rr %ECX
%reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
%reg1025<def> = MOV32rr %reg1029
%reg1026<def> = MOV32rr %reg1030
%reg1024<def> = MOV32rr %reg1028
The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.
With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
%reg1031<def> = MOVPC32r 0
%reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
%reg1024<def> = MOV32rr %EAX
%reg1025<def> = MOV32rr %EDX
%reg1026<def> = MOV32rr %ECX
%reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]
Much better!
llvm-svn: 48307
2008-03-12 22:19:41 +00:00
723849a17f
Initial soft-float support for LegalizeTypes. I rewrote
...
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
llvm-svn: 48305
2008-03-12 21:27:04 +00:00
34ae72c435
Change VirtRegMap's dump to dump to cerr, not DOUT, so that it
...
can be called from within a debuger without having -debug specified
on the command-line.
llvm-svn: 48298
2008-03-12 20:52:10 +00:00
bf68f9fd8d
Fix typos in comments.
...
llvm-svn: 48297
2008-03-12 20:50:04 +00:00
c54fe97f08
Fix typo.
...
llvm-svn: 48295
2008-03-12 20:35:19 +00:00
87de65fc29
Don't try to extract an i32 from an f64. This
...
getCopyToParts problem was noticed by the new
LegalizeTypes infrastructure. In order to avoid
this kind of thing in the future I've added a
check that EXTRACT_ELEMENT is only used with
integers. Once LegalizeTypes is up and running
most likely BUILD_PAIR and EXTRACT_ELEMENT can
be removed, in favour of using apints instead.
llvm-svn: 48294
2008-03-12 20:30:08 +00:00
8a923e7c28
Reimplement the parameter attributes support, phase #1 . hilights:
...
1. There is now a "PAListPtr" class, which is a smart pointer around
the underlying uniqued parameter attribute list object, and manages
its refcount. It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
ParamAttrsWithIndex's, no need to make a SmallVector of a specific
size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
dereferencing the pointer is simplified to just access the
PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
bit simpler.
Phase #2 will rename some stuff (e.g. PAListPtr) and do other less
invasive changes.
llvm-svn: 48289
2008-03-12 17:45:29 +00:00
6ff0b822b4
Improve the return slot optimization to be both more aggressive (not limited to sret parameters), and
...
safer (when the passed pointer might be invalid). Thanks to Duncan and Chris for the idea behind this,
and extra thanks to Duncan for helping me work out the trap-safety.
llvm-svn: 48280
2008-03-12 07:37:44 +00:00
99ee78ef63
Clean up my own mess.
...
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
llvm-svn: 48279
2008-03-12 07:02:50 +00:00
944b1c76ab
We also need to collect the VN IDs for the PHI instructions for later updating.
...
llvm-svn: 48278
2008-03-12 04:22:57 +00:00
70aaab6dc5
When we're determining what registers to coallesce, track the VNInfo IDs for the definitions that
...
feed the PHI instructions. We'll need these IDs in order to update LiveIntervals properly.
llvm-svn: 48277
2008-03-12 03:13:29 +00:00
e7b19035ed
when the bitcode reader is referencing a paramattr, make sure to bump its refcount.
...
llvm-svn: 48276
2008-03-12 02:25:52 +00:00
0903aef2ff
Total brain cramp.
...
llvm-svn: 48274
2008-03-12 02:05:05 +00:00
1f49988a7a
This is a simple fix for getting error messages from dlerror in
...
LoadLibraryPermanently. The current code modifies the value of a pointer
that is passed by value, so the caller never gets the message.
Patch by Julien Lerouge!
llvm-svn: 48270
2008-03-12 00:50:01 +00:00
0d98256c05
One more bit of Altivec parameter passing.
...
llvm-svn: 48269
2008-03-12 00:49:20 +00:00
2f22e3f690
Be backward compatible
...
llvm-svn: 48268
2008-03-12 00:49:19 +00:00
cc189b5606
Check multiple return values.
...
llvm-svn: 48267
2008-03-12 00:32:32 +00:00
b28456ef18
Implement Altivec passing to varargs functions on ppc.
...
llvm-svn: 48264
2008-03-12 00:22:17 +00:00
105cb3988b
Set NextMII after issuing a physical register spill.
...
llvm-svn: 48263
2008-03-12 00:14:07 +00:00
fa8667a2dd
Fix attribute handling.
...
llvm-svn: 48262
2008-03-12 00:07:03 +00:00
b398635456
Minor debug output bug.
...
llvm-svn: 48261
2008-03-12 00:02:46 +00:00
e6d90f5a95
Ultimately resolve aliases during linking, if possible
...
llvm-svn: 48259
2008-03-11 22:51:09 +00:00
e8fa50f63a
Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137
...
llvm-svn: 48257
2008-03-11 22:38:53 +00:00
24570836b2
Use PassManagerBase instead of FunctionPassManager for functions
...
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
llvm-svn: 48256
2008-03-11 22:29:46 +00:00
da7db7d9a1
Add helper for ultimate aliasee resoltion
...
llvm-svn: 48255
2008-03-11 22:28:56 +00:00
7358165c99
Handle multiple ret values.
...
llvm-svn: 48254
2008-03-11 22:24:29 +00:00
f6269f0914
Initialize.
...
llvm-svn: 48253
2008-03-11 22:08:21 +00:00
20af5a0fe7
Check to see if a two-entry PHI block can be simplified
...
before trying to merge the block into its predecessors.
This allows two-entry-phi-return.ll to be simplified
into a single basic block.
llvm-svn: 48252
2008-03-11 21:53:06 +00:00
2601d7ee50
Honour aliases visibility during asm emission
...
llvm-svn: 48249
2008-03-11 21:41:14 +00:00
db691cbd6d
Honour aliases visibility when reading from/writing to bitcode
...
llvm-svn: 48248
2008-03-11 21:40:17 +00:00
a3891365b5
Transfer physical register spill info when load / store folding happens.
...
llvm-svn: 48246
2008-03-11 21:34:46 +00:00
44b4c07cd1
Use the correct value for InSignBit.
...
llvm-svn: 48245
2008-03-11 21:29:43 +00:00
1351025a91
Initial codegen support for functions and calls with multiple return values.
...
llvm-svn: 48244
2008-03-11 21:11:25 +00:00
8abed80a69
Implement basic support for the 'f' register class constraint. This basically
...
works, but probably won't if you mix it with 't' or 'u' yet.
llvm-svn: 48243
2008-03-11 19:50:13 +00:00
7b27ccfd5e
coalesce away 80-bit floating point copies.
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llvm-svn: 48241
2008-03-11 19:30:09 +00:00
7930d8e775
convert a massive if statement to a switch.
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llvm-svn: 48240
2008-03-11 19:28:17 +00:00
120ad01fcb
start handling the 'f' x87 constraint.
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llvm-svn: 48239
2008-03-11 19:06:29 +00:00
70c238a1d8
Skip functions that return multiple values.
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llvm-svn: 48233
2008-03-11 18:04:06 +00:00
5663fe6613
Become multiple return value aware.
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Right now, the pass does not optimize tail recursions
involving multiple return values.
llvm-svn: 48228
2008-03-11 17:33:32 +00:00
e418de3023
Add TODO reminder.
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llvm-svn: 48227
2008-03-11 17:32:05 +00:00
d3a20c9e1e
Give PassManager and FunctionPassManager a common base class, with
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add(Pass *) as a pure virtual member function. This will allow all
the various addPassesTo* functions in LLVM to avoid hard-coding what
type of PassManager is used.
llvm-svn: 48226
2008-03-11 16:41:42 +00:00
dfdf2c0633
Fix typos in comments.
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llvm-svn: 48225
2008-03-11 16:18:48 +00:00
342e4104d3
Missed part of recommit.
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llvm-svn: 48224
2008-03-11 10:27:36 +00:00
aa7c2105de
Recommitting parts of r48130. These do not appear to cause the observed failures.
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llvm-svn: 48223
2008-03-11 10:09:17 +00:00
d54660aeed
Use TargetRegisterInfo::getPhysicalRegisterRegClass. Remove duplicated code.
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llvm-svn: 48221
2008-03-11 07:55:13 +00:00
d85667b89c
If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_).
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llvm-svn: 48220
2008-03-11 07:54:14 +00:00
e88a625ecd
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
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llvm-svn: 48218
2008-03-11 07:19:34 +00:00
5b59e372dc
In 32-bit mode, mark 64-bit GPR's as unallocatable.
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llvm-svn: 48217
2008-03-11 07:16:00 +00:00
b29f93613d
Some LegalizeTypes code factorization and minor
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enhancements.
llvm-svn: 48215
2008-03-11 06:41:14 +00:00
5c7bda440f
compile: double test() {}
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into:
_test:
fldz
ret
instead of:
_test:
subl $12, %esp
#IMPLICIT_DEF %xmm0
movsd %xmm0, (%esp)
fldl (%esp)
addl $12, %esp
ret
llvm-svn: 48213
2008-03-11 06:21:08 +00:00
a3860a2422
Fix the build on gcc 4.2.
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llvm-svn: 48212
2008-03-11 05:56:09 +00:00
a7a2075ab8
Initial multiple return values support.
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llvm-svn: 48210
2008-03-11 05:46:42 +00:00
1bd44363f2
Change the model for FP Stack return to use fp operands on the
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RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
llvm-svn: 48209
2008-03-11 03:23:40 +00:00
3e0ec65678
variadic instructions don't have operand info for variadic arguments.
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llvm-svn: 48208
2008-03-11 03:14:42 +00:00
d6819da453
Generalize ExpandIntToFP to handle the case where the operand is legal
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and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
llvm-svn: 48206
2008-03-11 01:59:03 +00:00
d3090bcfc8
If a register operand comes from the variadic part of a node, don't
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verify the register constraint matches what the instruction expects.
llvm-svn: 48205
2008-03-11 00:59:28 +00:00
850e143cbf
Temporarily revert 48175.
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llvm-svn: 48204
2008-03-11 00:27:34 +00:00
2591afca0a
Fix thinko: alias always defines new symbol. Even is aliasee itself is undefined.
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llvm-svn: 48203
2008-03-11 00:24:53 +00:00
10f7d850cf
More APInt-ification.
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llvm-svn: 48201
2008-03-11 00:11:06 +00:00
a4fa0ad30d
abort with an assert instead of a cerr to get line#
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llvm-svn: 48199
2008-03-10 23:56:08 +00:00
fc42961f18
Use utostr instead of a stringstream.
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llvm-svn: 48198
2008-03-10 23:55:07 +00:00
92275427e5
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
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- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
llvm-svn: 48197
2008-03-10 23:49:09 +00:00
2a3aeb1f72
Correctly clone FlaggedNodes.
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llvm-svn: 48196
2008-03-10 23:48:14 +00:00
2f3648b261
Initialize ArgTypes directly instead of manually copying in the elements.
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llvm-svn: 48195
2008-03-10 23:41:23 +00:00
830d86cab8
APInt-ify this.
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llvm-svn: 48194
2008-03-10 23:38:17 +00:00
de66dc88cd
Remove an unnecessary #include
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llvm-svn: 48193
2008-03-10 23:37:12 +00:00
7362d38391
Don't emit FP_REG_KILL into a block that just returns. Nothing
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can be live out of the block anyway, so it isn't needed.
llvm-svn: 48192
2008-03-10 23:34:12 +00:00
f4300950f1
Implement more support for fp-to-i128 and i128-to-fp conversions.
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llvm-svn: 48189
2008-03-10 23:03:31 +00:00
0fb187f81b
Disable prolog code that aligns the stack when a
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local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
llvm-svn: 48188
2008-03-10 22:59:46 +00:00
Evan Cheng