Commit Graph

146746 Commits

Author SHA1 Message Date
Kevin Enderby 6c1d2b4cb2 Add the error handling for Mach-O dyld compact lazy bind, weak bind and
rebase entry errors and test cases for each of the error checks.

Also verified with Nick Kledzik that a BIND_OPCODE_SET_ADDEND_SLEB
opcode is legal in a lazy bind table, so code that had that as an error
check was removed.

With MachORebaseEntry and MachOBindEntry classes now returning
an llvm::Error in all cases for malformed input the variables Malformed
and logic to set use them is no longer needed and has been removed
from those classes.

Also in a few places, removed the redundant Done assignment to true
when also calling moveToEnd() as it does that assignment.

This only leaves the dyld compact export entries left to have
error handling yet to be added for the dyld compact info.

llvm-svn: 298883
2017-03-27 20:09:23 +00:00
Matthew Simpson b8ff4a4a70 [LV] Transform truncations of non-primary induction variables
The vectorizer tries to replace truncations of induction variables with new
induction variables having the smaller type. After r295063, this optimization
was applied to all integer induction variables, including non-primary ones.
When optimizing the truncation of a non-primary induction variable, we still
need to transform the new induction so that it has the correct start value.
This should fix PR32419.

Reference: https://bugs.llvm.org/show_bug.cgi?id=32419
llvm-svn: 298882
2017-03-27 20:07:38 +00:00
Craig Topper 6ebeb7041e [APInt] Move operator=(uint64_t) inline as its pretty simple and is often used with small constants that the compiler can optimize.
While there recognize that we only need to clearUnusedBits on the single word case.

llvm-svn: 298881
2017-03-27 20:07:31 +00:00
Krzysztof Parzyszek 46a0392c61 [TableGen] Print #nnn as a name of an non-native reg unit with id nnn
When using -debug with -gen-register-info, tablegen will crash when
trying to print a name of a non-native register unit. This patch only
affects the debug information generated while running llvm-tblgen,
and has no impact on the compilable code coming out of it.

llvm-svn: 298875
2017-03-27 19:08:24 +00:00
Valery Pykhtin fb9905545c [AMDGPU] SISched: Detect dependency types between blocks
Patch by Axel Davy (axel.davy@normalesup.org)

Differential revision: https://reviews.llvm.org/D30153

llvm-svn: 298872
2017-03-27 18:22:39 +00:00
Bruno Cardoso Lopes 1856ceed82 [Support] Avoid concurrency hazard in signal handler registration
Several static functions from the signal API can be invoked
simultaneously; RemoveFileOnSignal for instance can be called indirectly
by multiple parallel loadModule() invocations, which might lead to
the assertion:

Assertion failed: (NumRegisteredSignals < array_lengthof(RegisteredSignalInfo) && "Out of space for signal handlers!"),
  function RegisterHandler, file /llvm/lib/Support/Unix/Signals.inc, line 105.

RemoveFileOnSignal calls RegisterHandlers(), which isn't currently
mutex protected, leading to the behavior above. This potentially affect
a few other users of RegisterHandlers() too.

rdar://problem/30381224

llvm-svn: 298871
2017-03-27 18:21:31 +00:00
Craig Topper 70d8ca9276 [APInt] Move operator&=(uint64_t) inline and use memset to clear the upper words.
This method is pretty new and probably isn't use much in the code base so this should have a negligible size impact. The OR and XOR operators are already inline.

llvm-svn: 298870
2017-03-27 18:16:17 +00:00
Ahmed Bougacha f0b22c471b [GlobalISel][AArch64] Extract a variable out of an NDEBUG block. NFC.
r298863 used PtrReg, but that's never defined in release builds. Fix it.

llvm-svn: 298869
2017-03-27 18:14:20 +00:00
Craig Topper e4c4668d3a [APInt] Use memset in setAllBits.
llvm-svn: 298867
2017-03-27 17:50:54 +00:00
Adrian Prantl e8450fdb48 Remove redundant check for nullptr.
llvm-svn: 298866
2017-03-27 17:36:31 +00:00
Adrian Prantl 035862b926 Remove unneccessary virtual destructor from DwarfExpression.
llvm-svn: 298865
2017-03-27 17:34:04 +00:00
Ahmed Bougacha f75782f9dc [GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode.
A majority of loads and stores at O0 access an alloca.

It's trivial to fold the G_FRAME_INDEX into the instruction; do it.

llvm-svn: 298864
2017-03-27 17:31:56 +00:00
Ahmed Bougacha 8a654085d0 [GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode.
We're not to the point of supporting the load/store patterns yet
(because they extensively use PatFrags).

But in the meantime, we can implement some of the simplest addressing
modes.

llvm-svn: 298863
2017-03-27 17:31:52 +00:00
Ahmed Bougacha 85a66a6d9f [GlobalISel][AArch64] Select store of zero to WZR/XZR.
These occur very frequently, and are quite trivial to catch.

llvm-svn: 298862
2017-03-27 17:31:48 +00:00
Valery Pykhtin ba3a4def29 [AMDGPU] SISched: Update colorEndsAccordingToDependencies
Patch by Axel Davy (axel.davy@normalesup.org)

Differential revision: https://reviews.llvm.org/D30150

llvm-svn: 298861
2017-03-27 17:26:40 +00:00
Craig Topper afc9e35343 [APInt] Move the >64 bit case for flipAllBits out of line.
This is more consistent with what we do for other operations. This shrinks the opt binary on my build by ~72k.

llvm-svn: 298858
2017-03-27 17:10:21 +00:00
Valery Pykhtin f70f683670 [AMDGPU] Fix SI scheduler LiveOut Refcount issue
Patch by Axel Davy (axel.davy@normalesup.org)

Differential revision: https://reviews.llvm.org/D30145

llvm-svn: 298857
2017-03-27 17:06:36 +00:00
Ahmed Bougacha 641cb203b6 [GlobalISel][AArch64] Select CBZ.
CBZ/CBNZ represent a substantial portion of all conditional branches.
Look through G_ICMP to select them.

We can't use tablegen yet because the existing patterns match an
AArch64ISD node.

llvm-svn: 298856
2017-03-27 16:35:31 +00:00
Ahmed Bougacha 2d29998f22 [GlobalISel] Add a 'getConstantVRegVal' helper.
Use it to compare immediate operands.

llvm-svn: 298855
2017-03-27 16:35:27 +00:00
Ahmed Bougacha c1cbcee170 [GlobalISel][AArch64] Use proper constant types in test. NFC.
llvm-svn: 298854
2017-03-27 16:35:23 +00:00
Dmitry Preobrazhensky c512d44845 [AMDGPU][MC] Fix for Bug 28207 + LIT tests
Enabled clamp and omod for v_cvt_* opcodes which have src0 of an integer type

Reviewers: vpykhtin, arsenm

Differential Revision: https://reviews.llvm.org/D31327

llvm-svn: 298852
2017-03-27 15:57:17 +00:00
Chad Rosier 862a41270f [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as not having side effects.
Among other things, this allows Machine LICM to hoist a costly 'mrs'
instruction from within a loop.

Differential Revision: http://reviews.llvm.org/D31151

llvm-svn: 298851
2017-03-27 15:52:38 +00:00
Yaxun Liu 1a14bfa022 [AMDGPU] Get address space mapping by target triple environment
As we introduced target triple environment amdgiz and amdgizcl, the address
space values are no longer enums. We have to decide the value by target triple.

The basic idea is to use struct AMDGPUAS to represent address space values.
For address space values which are not depend on target triple, use static
const members, so that they don't occupy extra memory space and is equivalent
to a compile time constant.

Since the struct is lightweight and cheap, it can be created on the fly at
the point of usage. Or it can be added as member to a pass and created at
the beginning of the run* function.

Differential Revision: https://reviews.llvm.org/D31284

llvm-svn: 298846
2017-03-27 14:04:01 +00:00
Anna Thomas f57ae33381 [InstCombine] Avoid incorrect folding of select into phi nodes when incoming element is a vector type
Summary:
We are incorrectly folding selects into phi nodes when the incoming value of a phi
node is a constant vector. This optimization is done in `FoldOpIntoPhi` when the
select condition is a phi node with constant incoming values.
Without the fix, we are miscompiling (i.e. incorrectly folding the
select into the phi node) when the vector contains non-zero
elements.
This patch fixes the miscompile and we will correctly fold based on the
select vector operand (see added test cases).

Reviewers: majnemer, sanjoy, spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31189

llvm-svn: 298845
2017-03-27 13:52:51 +00:00
Daniel Sanders 513c3e474d Correct OptionCategoryCompare() in the command line library.
Summary:
It should return <0, 0, or >0 for less-than, equal, and greater-than like
strcmp() (according to the history, it used to be implemented with
strcmp()) but it actually returned 0, or 1 for not-equal and equal.

Reviewers: qcolombet

Reviewed By: qcolombet

Subscribers: qcolombet, llvm-commits

Differential Revision: https://reviews.llvm.org/D30996

llvm-svn: 298844
2017-03-27 13:43:24 +00:00
Daniel Sanders 0848b23d53 [tablegen] Use categories on options that only matter to one emitter.
Summary:
The categories are emitted in a strange order in this patch due to a bug in the
CommandLine library.

Reviewers: ab

Reviewed By: ab

Subscribers: ab, llvm-commits

Differential Revision: https://reviews.llvm.org/D30995

llvm-svn: 298843
2017-03-27 13:15:13 +00:00
Justin Bogner 8444d106d5 ADT: Add range helpers for pointer_ and pointee_iterator
llvm-svn: 298841
2017-03-27 12:56:12 +00:00
Gadi Haber 89d5f9391a [X86][AVX2] bugzilla bug 21281 Performance regression in vector interleave in AVX2
This is a patch for an on-going bugzilla bug 21281 on the generated X86 code for a matrix transpose8x8 subroutine which requires vector interleaving. The generated code in AVX2 is currently non-optimal and requires 60 instructions as opposed to only 40 instructions generated for AVX1.
 The patch includes a fix for the AVX2 case where vector unpack instructions use less operations than the vector blend operations available in AVX2.
 In this case using vector unpack instructions is more efficient.

Reviewers:
zvi  
delena  
igorb  
craig.topper  
guyblank  
eladcohen  
m_zuckerman  
aymanmus  
RKSimon 

llvm-svn: 298840
2017-03-27 12:13:37 +00:00
Karl-Johan Karlsson bb6cf7378f [TableGen] Make CodeGenMapTable understand the namespace field of an instruction
Do not force the backends to use target name as namespace.

Original patch by Mattias Eriksson

Reviewers: stoklund, craig.topper

Reviewed By: stoklund

Subscribers: materi, llvm-commits

Differential Revision: https://reviews.llvm.org/D31322

llvm-svn: 298834
2017-03-27 07:13:44 +00:00
Craig Topper 1dd20e6544 [IR] Implement pairs of non-const and const methods using the const version instead of the non-const version. NFCI
This removes a const_cast of the this pointer.

llvm-svn: 298831
2017-03-27 05:47:03 +00:00
Craig Topper 1c78f4a0ff [IR] Share implementation for pairs of const and non-const methods using const_cast. NFCI
llvm-svn: 298830
2017-03-27 05:46:58 +00:00
Craig Topper 74fb7ac2e0 [IR] Share implementation of pairs of const and non-const methods in BasicBlock using the const version instead of the non-const version
Summary:
During post-commit review of a previous change I made it was pointed out that const casting 'this' is technically a bad practice. This patch re-implements all of the methods in BasicBlock that do this to use the const BasicBlock version and const_cast the return value instead.

I think there are still many other classes that do similar things. I may look at more in the future.

Reviewers: dblaikie

Reviewed By: dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31377

llvm-svn: 298827
2017-03-27 02:38:17 +00:00
Craig Topper 224b19d626 [IR] Make Instruction::isAssociative method inline. Add LLVM_READONLY to the static version.
llvm-svn: 298826
2017-03-26 23:23:29 +00:00
Davide Italiano a2c4e4b929 [Target] Remove some code probably copy/pasted from another backend.
llvm-svn: 298825
2017-03-26 21:45:04 +00:00
Davide Italiano 5c2aa5d3e4 [MachineScheduler] Reference the correct header.
llvm-svn: 298823
2017-03-26 21:27:21 +00:00
Sanjoy Das e4b073a4e8 Fix typo in comment; NFC
llvm-svn: 298819
2017-03-26 20:56:25 +00:00
Simon Pilgrim ca8bd25824 Fix signed/unsigned comparison warnings.
llvm-svn: 298813
2017-03-26 17:39:41 +00:00
Shoaib Meenai 7375448893 [llvm-readobj] Prefer ILT to IAT for reading COFF imports
We're seeing binutils ld produce binaries where the import address
table's NameRVA entry is actually a VA instead (i.e. it's already base
relocated), which llvm-readobj then chokes on. Both dumpbin and the
Windows loader are able to handle these binaries correctly, however, and
we can make llvm-readobj handle them correctly too by iterating the
import lookup table (which doesn't have a relocated NameRVA) rather than
the import address table.

The import lookup table and the import address table are supposed to be
identical on disk, and prior to r277298 the import lookup table would be
used by `llvm-readobj -coff-imports` anyway, so this shouldn't have any
functional change (except in the case of our malformed binaries). The
import lookup table can apparently be missing when using old Borland
linkers, so fall back to the import address table in that case.

Resolves PR31766.

Differential Revision: https://reviews.llvm.org/D31362

llvm-svn: 298812
2017-03-26 17:10:11 +00:00
Serge Pavlov b71bb80c2d [LoopUnroll] Remap references in peeled iteration
References in cloned blocks must be remapped prior to dominator
calculation.

Differential Revision: https://reviews.llvm.org/D31281

llvm-svn: 298811
2017-03-26 16:46:53 +00:00
Chandler Carruth de27a6dcfa [IR] Switch to more normal template parameter names ending in `T`
instead of `Ty`.

The `Ty` suffix is much more commonly used for LLVM `Type` variable
names, so this seemed like a particularly confusing collision.

llvm-svn: 298808
2017-03-26 14:24:06 +00:00
Simon Pilgrim 311c5ddb5b Fix signed/unsigned comparison warnings.
llvm-svn: 298807
2017-03-26 13:59:17 +00:00
Simon Pilgrim 92925ea701 [X86][SSE] Add computeKnownBitsForTargetNode support for (V)PSLL/(V)PSRL instructions
llvm-svn: 298806
2017-03-26 13:17:55 +00:00
Simon Pilgrim 049d9c921f [X86][AVX512F] Fix reg class for VMOVSSZrr/VMOVSSZrrk and VMOVSDZrr/VMOVSDZrrk
Fixed -verify-machineinstrs errors in fast-isel-select-sse.ll (one of many in PR27481)

The VMOVSSZrr/VMOVSSZrrk and VMOVSDZrr/VMOVSDZrrk instructions were assuming both source registers were V128X when the second is actually supposed to be FR32X/FR64X

Differential Revision: https://reviews.llvm.org/D31200

llvm-svn: 298805
2017-03-26 12:52:28 +00:00
Simon Pilgrim bc71539454 Fix MSVC signed/unsigned comparison warnings.
llvm-svn: 298804
2017-03-26 11:17:05 +00:00
Simon Pilgrim 544f750de6 Regenerate test
llvm-svn: 298803
2017-03-26 10:33:03 +00:00
Simon Pilgrim a2b81dc411 Regenerate test
The CHECK-DAG aren't necessary and get in the way of automated checks

llvm-svn: 298802
2017-03-26 10:31:37 +00:00
Simon Pilgrim 1d8235a022 Regenerate tests to remove duplicated checks
llvm-svn: 298801
2017-03-26 10:28:39 +00:00
Igor Breger 531a203a06 [GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
    Support G_FRAME_INDEX instruction selection.

    Reviewers: zvi, rovka, ab, qcolombet

    Reviewed By: ab

    Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank

    Differential Revision: https://reviews.llvm.org/D30980

llvm-svn: 298800
2017-03-26 08:11:12 +00:00
Joerg Sonnenberger fa7367428a Split the SimplifyCFG pass into two variants.
The first variant contains all current transformations except
transforming switches into lookup tables. The second variant
contains all current transformations.

The switch-to-lookup-table conversion results in code that is more
difficult to analyze and optimize by other passes. Most importantly,
it can inhibit Dead Code Elimination. As such it is often beneficial to
only apply this transformation very late. A common example is inlining,
which can often result in range restrictions for the switch expression.

Changes in execution time according to LNT:
SingleSource/Benchmarks/Misc/fp-convert +3.03%
MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk -11.20%
MultiSource/Benchmarks/Olden/perimeter/perimeter -10.43%
and a couple of smaller changes. For perimeter it also results 2.6%
a smaller binary.

Differential Revision: https://reviews.llvm.org/D30333

llvm-svn: 298799
2017-03-26 06:44:08 +00:00
Andrew Wilkins ebfe3a9df8 Add check for BSD when setting LIB_NAMES for GNU ld
Patch by Koop Mast and Alex Arslan!

Differential Revision: https://reviews.llvm.org/D28215

llvm-svn: 298798
2017-03-26 05:58:48 +00:00