Commit Graph

729 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 2fb5b31578 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155
2011-01-10 02:58:51 +00:00
Jakob Stoklund Olesen 1331a15b0c Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.
Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

llvm-svn: 123107
2011-01-09 03:05:53 +00:00
Jakob Stoklund Olesen 9beef41f2c Fix emergency spilling in LiveIntervals::spillPhysRegAroundRegDefsUses.
Always spill the full representative register at any point where any subregister
is live.

This fixes PR8620 which caused the old logic to get confused and not spill
anything at all.

The fundamental problem here is that the coalescer is too aggressive about
physical register coalescing. It sometimes makes it impossible to allocate
registers without these emergency spills.

llvm-svn: 119375
2010-11-16 19:55:14 +00:00
Jakob Stoklund Olesen e2b8858611 Fix PR8612 in the standard spiller, take two.
The live range of a register defined by an early clobber starts at the use slot,
not the def slot.

Except when it is an early clobber tied to a use operand. Then it starts at the
def slot like a standard def.

llvm-svn: 119305
2010-11-16 00:40:59 +00:00
Jakob Stoklund Olesen 97154f67d9 Revert "Fix PR8612 in the standard spiller as well."
This reverts r119183 which borke the buildbots.

llvm-svn: 119270
2010-11-15 21:51:51 +00:00
Jakob Stoklund Olesen 97825bcbfd Fix PR8612 in the standard spiller as well.
The live range of a register defined by an early clobber starts at the use slot,
not the def slot.

llvm-svn: 119183
2010-11-15 20:55:53 +00:00
Andrew Trick 89eb6a8b94 RABasic is nearly functionally complete. There are a few remaining
benchmarks hitting an assertion.
Adds LiveIntervalUnion::collectInterferingVRegs.
Fixes "late spilling" by checking for any unspillable live vregs among
all physReg aliases.

llvm-svn: 118701
2010-11-10 19:18:47 +00:00
Jakob Stoklund Olesen b7050233fb Teach MachineBasicBlock::print() to annotate instructions and blocks with
SlotIndexes when available.

llvm-svn: 117392
2010-10-26 20:21:46 +00:00
Owen Anderson 8ac477ffb5 Begin adding static dependence information to passes, which will allow us to
perform initialization without static constructors AND without explicit initialization
by the client.  For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve.  I hope to be able to relax
the latter requirement in the future.

llvm-svn: 116334
2010-10-12 19:48:12 +00:00
Jakob Stoklund Olesen 57feeed92f Replace FindLiveRangeContaining() with getVNInfoAt() in LiveIntervalAnalysis.
This helps hiding the LiveRange class which really should be private.

llvm-svn: 116244
2010-10-11 21:45:03 +00:00
Owen Anderson df7a4f2515 Now with fewer extraneous semicolons!
llvm-svn: 115996
2010-10-07 22:25:06 +00:00
Lang Hames 564956867e Removed VNInfo::isDefAccurate(). Def "accuracy" can be checked by testing whether LiveIntervals::getInstructionFromIndex(def) returns NULL.
llvm-svn: 114791
2010-09-25 12:04:16 +00:00
Jakob Stoklund Olesen bc71af341e Remove SlotIndex::PHI_BIT. It is no longer used by anything.
llvm-svn: 114779
2010-09-25 00:45:18 +00:00
Evan Cheng 16bfe5b0f5 PHI elimination shouldn't require machineloopinfo since it's used at -O0. Move the requirement to LiveIntervalAnalysis instead. Note this does not change the number of times machineloopinfo is computed.
llvm-svn: 111285
2010-08-17 21:00:37 +00:00
Jakob Stoklund Olesen 073cd8004a Remove trailing whitespace.
llvm-svn: 110944
2010-08-12 20:01:23 +00:00
Jakob Stoklund Olesen 0c18757c9d Oops. Don't normalize spill weights twice.
When the normalizeSpillWeights function was introduced, I forgot to remove this
normalization.

This change could affect register allocation. Hopefully for the better.

llvm-svn: 110119
2010-08-03 17:21:16 +00:00
Owen Anderson a57b97e7e7 Fix batch of converting RegisterPass<> to INTIALIZE_PASS().
llvm-svn: 109045
2010-07-21 22:09:45 +00:00
Jakob Stoklund Olesen 37c42a3d02 Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.
TII::isMoveInstr is going tobe completely removed.

llvm-svn: 108507
2010-07-16 04:45:42 +00:00
Jakob Stoklund Olesen b5c899d11b Fix small bug in isMoveInstr -> COPY translation
llvm-svn: 108013
2010-07-09 20:55:49 +00:00
Jakob Stoklund Olesen bd953d1805 Change TII::foldMemoryOperand API to require the machine instruction to be
inserted in a MBB, and return an already inserted MI.

This target API change is necessary to allow foldMemoryOperand to call
storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot
reference in a target independent way.

The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait
until COPY folding is actually implemented. Most targets only fold copies and
won't need to specialize this hook at all.

llvm-svn: 107991
2010-07-09 17:29:08 +00:00
Jakob Stoklund Olesen 00264624a9 Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879
2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen a1e883dcf6 Remove references to INSERT_SUBREG after de-SSA.
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

llvm-svn: 107878
2010-07-08 16:40:15 +00:00
Jakob Stoklund Olesen f0e551d4f4 Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.
Buildbot breakage.

llvm-svn: 107744
2010-07-07 00:32:25 +00:00
Jakob Stoklund Olesen e2d3067f6b Remove references to INSERT_SUBREG after de-SSA
llvm-svn: 107732
2010-07-06 23:40:35 +00:00
Jakob Stoklund Olesen 70ee3ecd33 Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.
INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.

llvm-svn: 107726
2010-07-06 23:26:25 +00:00
Jakob Stoklund Olesen 4c82a9e7d0 Detect and handle COPY in many places.
This code is transitional, it will soon be possible to eliminate
isExtractSubreg, isInsertSubreg, and isMoveInstr in most places.

llvm-svn: 107547
2010-07-03 00:04:37 +00:00
Benjamin Kramer a000002428 VNInfos don't need to be destructed anymore.
llvm-svn: 106943
2010-06-26 11:30:59 +00:00
Jakob Stoklund Olesen 55d738e2e1 Don't track kills in VNInfo. Use interval ends instead.
The VNInfo.kills vector was almost unused except for all the code keeping it
updated. The few places using it were easily rewritten to check for interval
ends instead.

The two new methods LiveInterval::killedAt and killedInRange are replacements.

This brings us down to 3 independent data structures tracking kills.

llvm-svn: 106905
2010-06-25 22:53:05 +00:00
Jakob Stoklund Olesen 9b659142a6 Remove the now unused LiveIntervals::getVNInfoSourceReg().
This method was always a bit too simplistic for the real world. It didn't really
deal with subregisters and such.

llvm-svn: 106781
2010-06-24 20:18:15 +00:00
Jakob Stoklund Olesen 7f894d8fdc Remove the -fast-spill option.
This code path has never really been used, and we are going to be handling
spilling through the Spiller interface in the future.

llvm-svn: 106777
2010-06-24 19:56:08 +00:00
Jakob Stoklund Olesen 45230239e4 Replace a big gob of old coalescer logic with the new CoalescerPair class.
CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.

This second attempt fixes some crashes that only occurred Linux.

llvm-svn: 106769
2010-06-24 18:15:01 +00:00
Jakob Stoklund Olesen 53ccab7d1c Verify that VNI kills are pointing to existing instructions.
In this case it is essential that the kill is real because the spiller will
decide to omit a spill if it thinks there is a later kill.

llvm-svn: 106751
2010-06-24 15:56:59 +00:00
Jakob Stoklund Olesen dbb58d2974 Revert "Replace a big gob of old coalescer logic with the new CoalescerPair class."
Whiny buildbots.

llvm-svn: 106710
2010-06-24 00:52:22 +00:00
Jakob Stoklund Olesen f38e6720cc Replace a big gob of old coalescer logic with the new CoalescerPair class.
CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.

llvm-svn: 106701
2010-06-24 00:12:39 +00:00
Jakob Stoklund Olesen 07f4fa8198 TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.

Fix it in LiveVariableAnalysis by adding the <undef> flag.

llvm-svn: 106333
2010-06-18 22:29:44 +00:00
Jakob Stoklund Olesen 207cd4bbd7 Allow a register to be redefined multiple times in a basic block.
LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.

Here is an example of chained INSERT_SUBREGs that we can handle now:

68      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
                register: %reg1040 +[70,134:0)
76      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
                register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0)  0@78-(134) 1@70-(78)
84      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
                register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0)  0@86-(134) 1@70-(78) 2@78-(86)
92      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
                register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0)  0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)

rdar://problem/8096390

llvm-svn: 106152
2010-06-16 21:29:40 +00:00
Jakob Stoklund Olesen 818e4df2b4 Use readsWritesVirtualRegister instead of counting uses and defs when inserting
spills and reloads.

This means that a partial define of a register causes a reload so the other
parts of the register are preserved.

The reload can be prevented by adding an <imp-def> operand for the full
register. This is already done by the coalescer and live interval analysis where
relevant.

llvm-svn: 105369
2010-06-03 00:07:47 +00:00
Evan Cheng 3858451e09 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen b4e1687270 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323
2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen 8e8e090301 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
This correctly handles partial redefines and undef uses.

llvm-svn: 104322
2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen 1f3801062d If the first definition of a virtual register is a partial redef, add an
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320
2010-05-21 16:32:16 +00:00
Nick Lewycky c53cc4f8bf Fix typo in comment.
llvm-svn: 104209
2010-05-20 03:30:09 +00:00
Evan Cheng 166a7993ba Yes, if the redef is a copy, update the old val# with the copy. But make sure to clear the copy field if the redef is not a copy.
llvm-svn: 103922
2010-05-17 01:47:47 +00:00
Chris Lattner 93cd0f1c89 improve portability to systems that don't have powf/modf (e.g. solaris 9)
patch by Evzen Muller!

llvm-svn: 103876
2010-05-15 17:10:24 +00:00
Evan Cheng e26e56e72b A partial re-def instruction may be a copy.
llvm-svn: 103850
2010-05-15 01:35:44 +00:00
Evan Cheng faef5d0281 Re-defined valno is always valno even for partial re-def's.
llvm-svn: 103410
2010-05-10 17:33:49 +00:00
Evan Cheng 38d9a6f805 Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.
80      %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
. . .
120     %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0

llvm-svn: 103102
2010-05-05 18:27:40 +00:00
Evan Cheng 4c908f4181 Teach PHI elimination to remove REG_SEQUENCE instructions and update references of the source operands with references of the destination with subreg indices. e.g.
%reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
%reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
=>
%reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...

PHI elimination now does more than phi elimination. It is really a de-SSA pass.

llvm-svn: 103039
2010-05-04 20:26:52 +00:00
Bob Wilson c936b56871 Print basic block numbers in live interval debug output. Since the rest of the
debug output is showing machine instructions, the IR-level basic block names
aren't very meaningful, and because multiple machine basic blocks may be
derived from one IR-level BB, they're also not unique.

llvm-svn: 102960
2010-05-03 21:38:11 +00:00
Evan Cheng a5a8f76cea - Really preserve dbg_value instructions when the register is spilled.
- Also, update dbg_value is the value is being re-matted from a frame slot, e.g. fixed slots for arguments.

llvm-svn: 102565
2010-04-28 23:52:26 +00:00
Evan Cheng c72d8a7dad Re-enable 102323 with fix: do not update dbg_value's with incorrect frame indices when the live interval are being re-materialized.
llvm-svn: 102361
2010-04-26 18:37:21 +00:00
Evan Cheng 5ad3cc1d5e Temporary disable spiller modifying dbg_value. It's breaking build.
llvm-svn: 102327
2010-04-26 08:24:07 +00:00
Evan Cheng ed69b382ea - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.

llvm-svn: 102323
2010-04-26 07:38:55 +00:00
Dan Gohman 9d2d053e11 Eliminate MachineBasicBlock::const_livein_iterator and make
MachineBasicBlock::livein_iterator a const_iterator, because
clients shouldn't ever be using the iterator interface to
mutate the livein set.

llvm-svn: 101147
2010-04-13 16:57:55 +00:00
Chris Lattner 2104b8d36e rename llvm::llvm_report_error -> llvm::report_fatal_error
llvm-svn: 100709
2010-04-07 22:58:41 +00:00
Benjamin Kramer 04c713dd45 Introduce SpecificBumpPtrAllocator, a wrapper for BumpPtrAllocator which allows
only a single type of object to be allocated. Use it to make VNInfo destruction
typesafe.

llvm-svn: 99919
2010-03-30 20:16:45 +00:00
Torok Edwin 8061bb141e Reapply r99881 with some fixes: only call destructor in releaseMemory!
llvm-svn: 99883
2010-03-30 11:17:48 +00:00
Torok Edwin a2d1dc42e1 Revert 99881, it brooke smooshlab's llvm-gcc-i386-darwin9.
llvm-svn: 99882
2010-03-30 10:25:08 +00:00
Torok Edwin ba6d13c0ea Introduce another Reset() method in BumpPtrAllocator that calls a destructor
on all objects it has allocated, if they are all of the same size and alignment.
Use this to destruct all VNInfos allocated in LiveIntervalAnalysis (PR6653).

valnos is not reliable for this purpose, as seen in r99400
(which still leaked, and sometimes caused double frees).

llvm-svn: 99881
2010-03-30 10:08:26 +00:00
Evan Cheng cbcccce420 Avoid being influenced by the presence of dbg_value instructions.
llvm-svn: 99879
2010-03-30 05:49:07 +00:00
Bob Wilson 4d87012eb3 Revert Edwin's change that is breaking MultiSource/Applications/ClamAV/clamscan.
--- Reverse-merging r99400 into '.':
D    test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
U    lib/CodeGen/LiveIntervalAnalysis.cpp

llvm-svn: 99419
2010-03-24 20:25:25 +00:00
Torok Edwin 4bbfdd41ea Fix memory leak in liveintervals: the destructor for VNInfos must be called,
otherwise the SmallVector it contains doesn't free its memory.
In most cases LiveIntervalAnalysis could get away by not calling the destructor,
because VNInfos are bumpptr-allocated, and smallvectors usually don't grow.
However when the SmallVector does grow it always leaks.

This is the valgrind shown leak from the original testcase:
==8206== 18,304 bytes in 151 blocks are definitely lost in loss record 164 of 164
==8206==    at 0x4A079C7: operator new(unsigned long) (vg_replace_malloc.c:220)
==8206==    by 0x4DB7A7E: llvm::SmallVectorBase::grow_pod(unsigned long, unsigned long) (in /home/edwin/clam/git/builds/defaul
t/libclamav/.libs/libclamav.so.6.1.0)
==8206==    by 0x4F90382: llvm::VNInfo::addKill(llvm::SlotIndex) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libcl
amav.so.6.1.0)
==8206==    by 0x5126B5C: llvm::LiveIntervals::handleVirtualRegisterDef(llvm::MachineBasicBlock*, llvm::ilist_iterator<llvm::M
achineInstr>, llvm::SlotIndex, llvm::MachineOperand&, unsigned int, llvm::LiveInterval&) (in /home/edwin/clam/git/builds/defau
lt/libclamav/.libs/libclamav.so.6.1.0)
==8206==    by 0x512725E: llvm::LiveIntervals::handleRegisterDef(llvm::MachineBasicBlock*, llvm::ilist_iterator<llvm::MachineI
nstr>, llvm::SlotIndex, llvm::MachineOperand&, unsigned int) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav
.so.6.1.0)
==8206==    by 0x51278A8: llvm::LiveIntervals::computeIntervals() (in /home/edwin/clam/git/builds/default/libclamav/.libs/libc
lamav.so.6.1.0)
==8206==    by 0x5127CB4: llvm::LiveIntervals::runOnMachineFunction(llvm::MachineFunction&) (in /home/edwin/clam/git/builds/de
fault/libclamav/.libs/libclamav.so.6.1.0)
==8206==    by 0x4DAE935: llvm::FPPassManager::runOnFunction(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclama
v/.libs/libclamav.so.6.1.0)
==8206==    by 0x4DAEB10: llvm::FunctionPassManagerImpl::run(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclama
v/.libs/libclamav.so.6.1.0)
==8206==    by 0x4DAED3D: llvm::FunctionPassManager::run(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclamav/.l
ibs/libclamav.so.6.1.0)
==8206==    by 0x4D8BE8E: llvm::JIT::runJITOnFunctionUnlocked(llvm::Function*, llvm::MutexGuard const&) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav.so.6.1.0)
==8206==    by 0x4D8CA72: llvm::JIT::getPointerToFunction(llvm::Function*) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav.so.6.1.0)

llvm-svn: 99400
2010-03-24 13:50:36 +00:00
Evan Cheng 403062313f Fix liveintervals handling of dbg_value instructions.
llvm-svn: 98686
2010-03-16 21:51:27 +00:00
Evan Cheng 8c4df8160e The check for coalescing a virtual register to a physical register, e.g.
cl = EXTRACT_SUBREG reg1024, 1, is overly conservative. It should check
for overlaps of vr's live interval with the super registers of the
physical register (ECX in this case) and let JoinIntervals() handle checking
the coalescing feasibility against the physical register (cl in this case).

llvm-svn: 98251
2010-03-11 08:20:21 +00:00
Dale Johannesen 8340cc0d6c Fix a bug in DEBUG_VALUE handling Devang ran into.
I'll get this loop right yet.

llvm-svn: 98155
2010-03-10 15:06:26 +00:00
Jakob Stoklund Olesen 115da88f01 Use methods to determine if a LiveInterval is spillable.
Don't accidentally produce unspillable intervals for deeply nested loops.

llvm-svn: 97496
2010-03-01 20:59:38 +00:00
Jakob Stoklund Olesen 38b76e27a7 Keep track of phi join registers explicitly in LiveVariables.
Previously, LiveIntervalAnalysis would infer phi joins by looking for multiply
defined registers. That doesn't work if the phi join is implicitly defined in
all but one of the predecessors.

llvm-svn: 96994
2010-02-23 22:43:58 +00:00
Jakob Stoklund Olesen c953acbd7f Always normalize spill weights, also for intervals created by spilling.
Moderate the weight given to very small intervals.

The spill weight given to new intervals created when spilling was not
normalized in the same way as the original spill weights calculated by
CalcSpillWeights. That meant that restored registers would tend to hang around
because they had a much higher spill weight that unspilled registers.

This improves the runtime of a few tests by up to 10%, and there are no
significant regressions.

llvm-svn: 96613
2010-02-18 21:33:05 +00:00
Dale Johannesen 1ccda7b7c4 When I rewrote this loop per Chris' preference I
changed its behavior.  Oops.

llvm-svn: 95811
2010-02-10 21:41:41 +00:00
Dale Johannesen f8b0e44584 Rewrite loop to suit Chris' preference.
llvm-svn: 95749
2010-02-10 01:31:26 +00:00
Dale Johannesen f8f9f55468 Skip DBG_VALUE many places in live intervals and
register coalescing.  This fixes many crashes and
places where debug info affects codegen (when
dbg.value is lowered to machine instructions, which
it isn't yet in TOT).

llvm-svn: 95739
2010-02-10 00:55:42 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Evan Cheng ea5c6be766 Run codegen dce pass for all targets at all optimization levels. Previously it's
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493
2010-02-06 09:07:11 +00:00
Dale Johannesen 7048797468 Ignore DEBUG_VALUE when building live intervals;
this makes the code work transparently the same
whether they're there or not.

llvm-svn: 94240
2010-01-22 22:38:21 +00:00
David Greene 1a51a211c6 Change errs() to dbgs().
llvm-svn: 92529
2010-01-04 22:49:02 +00:00
Lang Hames 4c052261de Changed slot index ranges for MachineBasicBlocks to be exclusive of endpoint.
This fixes an in-place update bug where code inserted at the end of basic blocks may not be covered by existing intervals which were live across the entire block. It is also consistent with the way ranges are specified for live intervals.

llvm-svn: 91859
2009-12-22 00:11:50 +00:00
Jakob Stoklund Olesen ec20a88a57 Reuse lowered phi nodes.
Tail duplication produces lots of identical phi nodes in different basic
blocks. Teach PHIElimination to reuse the join registers when lowering a phi
node that is identical to an already lowered node. This saves virtual
registers, and more importantly it avoids creating copies the the coalescer
doesn't know how to eliminate.

Teach LiveIntervalAnalysis about the phi joins with multiple uses.

This patch significantly reduces code size produced by -pre-regalloc-taildup.

llvm-svn: 91549
2009-12-16 18:55:53 +00:00
Evan Cheng c9a41c8b03 Coalesce insert_subreg undef, x first to avoid phase ordering issue.
llvm-svn: 91103
2009-12-11 06:01:00 +00:00
Jakob Stoklund Olesen 497161c40b Also attempt trivial coalescing for live intervals that end in a copy.
The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.

The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.

This patch is more conservative than r90502, and does not break
483.xalancbmk/i686. It still breaks the PowerPC bootstrap, so it is disabled
by default, and can be enabled with the -trivial-coalesce-ends option.

llvm-svn: 91049
2009-12-10 17:48:32 +00:00
Lang Hames 1ab2b49e6d Added a new "splitting" spiller.
When a call is placed to spill an interval this spiller will first try to
break the interval up into its component values. Single value intervals and
intervals which have already been split (or are the result of previous splits)
are spilled by the default spiller.

Splitting intervals as described above may improve the performance of generated
code in some circumstances. This work is experimental however, and it still
miscompiles many benchmarks. It's not recommended for general use yet.

llvm-svn: 90951
2009-12-09 05:39:12 +00:00
Bill Wendling f89986235d Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail.
llvm-svn: 90653
2009-12-05 07:30:23 +00:00
Jakob Stoklund Olesen ca9cf65455 Also attempt trivial coalescing for live intervals that end in a copy.
The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.

The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.

This patch takes care of a few more cases that r90163 missed.

llvm-svn: 90502
2009-12-04 00:16:04 +00:00
Jakob Stoklund Olesen 18c7cbd99b Clean up some loop logic.
llvm-svn: 90481
2009-12-03 20:49:10 +00:00
Evan Cheng 732351f732 Fix PR5391: support early clobber physical register def tied with a use (ewwww)
- A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber.
- If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range.
- Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature".

llvm-svn: 90269
2009-12-01 22:25:00 +00:00
Jakob Stoklund Olesen 020d8d4c63 New virtual registers created for spill intervals should inherit allocation hints from the original register.
This helps us avoid silly copies when rematting values that are copied to a physical register:

leaq	_.str44(%rip), %rcx
movq	%rcx, %rsi
call	_strcmp

becomes:

leaq	_.str44(%rip), %rsi
call	_strcmp

The coalescer will not touch the movq because that would tie down the physical register.

llvm-svn: 90163
2009-11-30 22:55:54 +00:00
Jakob Stoklund Olesen b4c14ebfbb More consistent labelling of basic blocks in debug output
llvm-svn: 89470
2009-11-20 18:54:59 +00:00
Jakob Stoklund Olesen 2bbeaa8774 Add MachineBasicBlock::getName, and use it in place of getBasicBlock()->getName.
Fix debug code that assumes getBasicBlock never returns NULL.

llvm-svn: 89428
2009-11-20 01:17:03 +00:00
Jakob Stoklund Olesen 520039fcb6 Remove the -early-coalescing option
llvm-svn: 89240
2009-11-18 20:36:47 +00:00
Evan Cheng ad7c6124e7 Hide a couple of options.
llvm-svn: 86522
2009-11-09 06:49:37 +00:00
Jakob Stoklund Olesen 4141d8ee92 Fix inverted conflict test in -early-coalesce.
A non-identity copy cannot be coalesced when the phi join destination register
is live at the copy site.

Also verify the condition that the PHI join source register is only used in
the PHI join. Otherwise the coalescing is invalid.

llvm-svn: 86322
2009-11-07 01:58:40 +00:00
Lang Hames 05fb9637f6 The Indexes Patch.
This introduces a new pass, SlotIndexes, which is responsible for numbering
instructions for register allocation (and other clients). SlotIndexes numbering
is designed to match the existing scheme, so this patch should not cause any
changes in the generated code.

For consistency, and to avoid naming confusion, LiveIndex has been renamed
SlotIndex.

The processImplicitDefs method of the LiveIntervals analysis has been moved
into its own pass so that it can be run prior to SlotIndexes. This was
necessary to match the existing numbering scheme.

llvm-svn: 85979
2009-11-03 23:52:08 +00:00
Evan Cheng ccc2e0cbda Trim unnecessary includes.
llvm-svn: 84597
2009-10-20 04:23:20 +00:00
Evan Cheng fa4bcaec7c If the physical register being spilled does not have an interval, spill its sub-registers instead.
llvm-svn: 84586
2009-10-20 01:31:09 +00:00
Dan Gohman 87b02d5bbc Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687
2009-10-09 23:27:56 +00:00
Dan Gohman e19c1810d7 isTriviallyReMaterializable checks the
TargetInstrDesc::isRematerializable flag, so it isn't necessary to do
this check in its callers.

llvm-svn: 83671
2009-10-09 21:02:10 +00:00
Dan Gohman 9b60992120 Replace some code for aggressive-remat with MachineInstr::isInvariantLoad, and
teach it how to recognize invariant physical registers.

llvm-svn: 83476
2009-10-07 17:47:20 +00:00
Lang Hames a7780905e7 Oops. Renamed remaining MachineInstrIndex references.
llvm-svn: 83255
2009-10-03 04:31:31 +00:00
Lang Hames 920301ecc5 Renamed MachineInstrIndex to LiveIndex.
llvm-svn: 83254
2009-10-03 04:21:37 +00:00
Daniel Dunbar f6dbd6f26e Remove unused variable.
llvm-svn: 82821
2009-09-25 23:26:56 +00:00
Dan Gohman e603710d11 Simplify a few more uses of reg_iterator.
llvm-svn: 82812
2009-09-25 22:26:13 +00:00
Dan Gohman 48b185d6f7 Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794
2009-09-25 20:36:54 +00:00
Evan Cheng 262f86ed90 Fix PR5024. LiveVariables physical register defs should *commit* only after all
of the defs are processed.
Also fix a implicit_def propagation bug: a implicit_def of a physical register
should be applied to uses of the sub-registers.

llvm-svn: 82616
2009-09-23 06:28:31 +00:00
Evan Cheng fccbd0afc6 Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information.
llvm-svn: 82436
2009-09-21 04:32:32 +00:00
Dale Johannesen a894053a9b When computing live intervals for earlyclobber operands,
we pushed the beginning of the interval back 1, so the
interval would overlap with inputs that die.  We were
also pushing the end of the interval back 1, though,
which means the earlyclobber didn't overlap with other
output operands.  Don't do this.  PR 4964.

llvm-svn: 82342
2009-09-20 00:36:41 +00:00
Daniel Dunbar 9367ec8644 Fix -Asserts warning.
llvm-svn: 81909
2009-09-15 20:31:12 +00:00
Evan Cheng a38ff3edae Another try at early partial coalescing. Identity phi source copies (their sources are defined by phi join def) are coalesced. And the phi join copy is backward copy propagated into the other copies.
Still miscompiling some tests. :-(

llvm-svn: 81849
2009-09-15 06:45:16 +00:00
Evan Cheng 7f789596f3 Add early coalescing to liveintervals. This is work in progress and is known to miscompute some tests. Read it at your own rish, I have aged 10 year while writing this.
The gist of this is if source of some of the copies that feed into a phi join is defined by the phi join, we'd like to eliminate them. However, if any of the non-identity source overlaps the live interval of the phi join then the coalescer won't be able to coalesce them. The early coalescer's job is to eliminate the identity copies by partially-coalescing the two live intervals.

llvm-svn: 81796
2009-09-14 21:33:42 +00:00
Lang Hames dad2da59ad Moved some more index operations over to LiveIntervals.
llvm-svn: 81605
2009-09-12 03:34:03 +00:00
Evan Cheng fe4d1e64d5 80 col violations.
llvm-svn: 81598
2009-09-12 02:01:07 +00:00
Lang Hames 3fffe62177 Replaces uses of unsigned for indexes in LiveInterval and VNInfo with
a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.

llvm-svn: 81040
2009-09-04 20:41:11 +00:00
Chris Lattner 1362602eb2 Change Pass::print to take a raw ostream instead of std::ostream,
update all code that this affects.

llvm-svn: 79830
2009-08-23 06:03:38 +00:00
Chris Lattner a6f074fb3a remove various std::ostream version of printing methods from
MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)

llvm-svn: 79813
2009-08-23 03:41:05 +00:00
Chris Lattner 1f28992886 remove a dead class.
llvm-svn: 79795
2009-08-23 00:42:42 +00:00
Bill Wendling dfcc42fa39 Convert DOUT to DEBUG(errs()...).
llvm-svn: 79752
2009-08-22 20:18:03 +00:00
Lang Hames 3b90d973b0 Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg.
llvm-svn: 78620
2009-08-10 23:43:28 +00:00
Evan Cheng 379429200e Turn some insert_subreg, extract_subreg, subreg_to_reg into implicit_defs.
llvm-svn: 78151
2009-08-05 03:53:14 +00:00
David Greene ec9bc28812 Re-apply LiveInterval index dumping patch, with fixes suggested by Bill
and others.

llvm-svn: 78003
2009-08-03 21:55:09 +00:00
Dan Gohman 0402315d41 Use setPreservesAll and setPreservesCFG in CodeGen passes.
llvm-svn: 77754
2009-07-31 23:37:33 +00:00
Daniel Dunbar 0dd5e1ed39 More migration to raw_ostream, the water has dried up around the iostream hole.
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019
2009-07-25 00:23:56 +00:00
Daniel Dunbar 8ef0735dd5 Move to raw_ostream.
llvm-svn: 76963
2009-07-24 09:53:24 +00:00
David Greene e88680e33e Constify the key in Mi2IndexMap.
llvm-svn: 76801
2009-07-22 21:56:14 +00:00
Chris Lattner 1eede6c635 revert r76602, 76603, and r76615, pending design discussions.
llvm-svn: 76646
2009-07-21 21:12:58 +00:00
David Greene ef1f36d3c7 Prefix IR dumps with LiveInterval indices when possible. This turns
this:

	%ESI<def> = MOV32rr %EDI<kill>
	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	%reg1027<def> = MOVZX64rr32 %ESI
	%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
	%RDI<def> = MOV64rr %RSP
	%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
	%RSP<def> = MOV64rr %RDI

into this:

4	%reg1024<def> = MOV32rr %EDI<kill>
12	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20	%reg1025<def> = MOVZX64rr32 %reg1024
28	%reg1026<def> = MOV64rr %reg1025<kill>
36	%reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44	%reg1027<def> = MOV64rr %reg1026<kill>
52	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60	%reg1028<def> = MOV64rr %RSP
68	%reg1029<def> = MOV64rr %reg1028<kill>
76	%reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84	%RSP<def> = MOV64rr %reg1029

This helps greatly when debugging register allocation and coalescing
problems.

llvm-svn: 76615
2009-07-21 18:56:32 +00:00
Evan Cheng f08b003bf0 Simplify the coalescer (finally!) by making LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands.
llvm-svn: 76223
2009-07-17 19:43:40 +00:00
Evan Cheng 357645efad Changed my mind. We now allow remat of instructions whose defs have subreg indices.
llvm-svn: 76100
2009-07-16 20:15:00 +00:00
Evan Cheng 84517443ca Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900
2009-07-16 09:20:10 +00:00
Torok Edwin fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Torok Edwin 56d0659726 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379
2009-07-11 20:10:48 +00:00
Torok Edwin ccb29cd290 Convert more assert(0)+abort() -> LLVM_UNREACHABLE,
and abort()/exit() -> llvm_report_error().

llvm-svn: 75363
2009-07-11 13:10:19 +00:00
Duncan Sands 45210aab86 Avoid compiler warnings if assertions turned off.
llvm-svn: 75267
2009-07-10 20:07:07 +00:00
Lang Hames dab7b06de9 Improved tracking of value number kills. VN kills are now represented
as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.

A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test 
condition has been updated to reflect this.

llvm-svn: 75097
2009-07-09 03:57:02 +00:00
Evan Cheng 2a5efe14a7 Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.

llvm-svn: 74601
2009-07-01 08:19:36 +00:00
Evan Cheng d379e896ff Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
llvm-svn: 74580
2009-07-01 01:59:31 +00:00
Evan Cheng 0dc101b897 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518
2009-06-30 08:49:04 +00:00
Chris Lattner c91e8c7464 When doing remat, don't consider uses of non-allocatable physregs. Patch
by Evan.

llvm-svn: 74370
2009-06-27 04:06:41 +00:00
Lang Hames 6b2c960cc4 More VNInfo tweaking, plus a little progress on intra-block splitting.
llvm-svn: 73750
2009-06-19 02:17:53 +00:00
Lang Hames 32270cc78e Improved PHI def marking, replaced some gotos with breaks.
llvm-svn: 73727
2009-06-18 22:01:47 +00:00
Lang Hames 16cab1935e VNInfo cleanup.
llvm-svn: 73634
2009-06-17 21:01:20 +00:00
Evan Cheng 085caf10be Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
llvm-svn: 73346
2009-06-14 20:22:55 +00:00
Lang Hames fc968ef687 Update to in-place spilling framework. Includes live interval scaling and trivial rewriter.
llvm-svn: 72729
2009-06-02 16:53:25 +00:00
Jeffrey Yasskin 7d287cb7ed LiveVariables::VarInfo contains an AliveBlocks BitVector, which has as many
entries as there are basic blocks in the function.  LiveVariables::getVarInfo
creates a VarInfo struct for every register in the function, leading to
quadratic space use.  This patch changes the BitVector to a SparseBitVector,
which doesn't help the worst-case memory use but does reduce the actual use in
very long functions with short-lived variables.

llvm-svn: 72426
2009-05-26 18:27:15 +00:00
Evan Cheng 210fc62a91 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.

llvm-svn: 70787
2009-05-03 18:32:42 +00:00
Evan Cheng 093e4c578d Fix PR4076. Correctly create live interval of physical register with two-address update.
llvm-svn: 70245
2009-04-27 20:42:46 +00:00
Evan Cheng 0f85bd368c Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass.
llvm-svn: 70213
2009-04-27 17:36:47 +00:00
Evan Cheng 1a99a5f501 It has finally happened. Spiller is now using live interval info.
This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue.

llvm-svn: 69743
2009-04-21 22:46:52 +00:00
Evan Cheng d67efaa847 Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g.
%reg1498<def> = MOV32rm %reg1024, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg1024, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg1024, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

=>

        %reg1498<def> = MOV32rm %reg2036, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg2037, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg2038, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

From linearscan's point of view, each of reg2036, 2037, and 2038 are separate registers, each is "killed" after a single use. The reloaded register is available and it's often clobbered right away. e.g. In thise case reg1498 is allocated EAX while reg2036 is allocated RAX. This means we end up with multiple reloads from the same stack slot in the same basic block.

Now linearscan recognize there are other reloads from same SS in the same BB. So it'll "downgrade" RAX (and its aliases) after reg2036 is allocated until the next reload (reg2037) is done. This greatly increase the likihood reloads from SS are reused.

This speeds up sha1 from OpenSSL by 5.8%. It is also an across the board win for SPEC2000 and 2006.

llvm-svn: 69585
2009-04-20 08:01:12 +00:00
Dan Gohman 1d50407932 Don't abort on an aliasing physical register that does not have
a live interval. This is needed for some upcoming subreg changes.

llvm-svn: 68956
2009-04-13 15:22:29 +00:00
Bob Wilson 51856173c8 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714
2009-04-09 17:16:43 +00:00
Dan Gohman ad3e549a53 Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.

This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.

Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.

Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.

Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.

Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.

llvm-svn: 68576
2009-04-08 00:15:30 +00:00
Owen Anderson 76a561f35e Don't assign a new stack slot if the pre-alloc splitter already assigned one.
llvm-svn: 67764
2009-03-26 18:53:38 +00:00
Evan Cheng f858466018 Fix PR3391 and PR3864. Reg allocator infinite looping.
llvm-svn: 67544
2009-03-23 18:24:37 +00:00
Evan Cheng 968c3b0d6e Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
llvm-svn: 67512
2009-03-23 08:01:15 +00:00
Sebastian Redl 8d5baa09f8 Fix the Win32 VS2008 build:
- Make type declarations match the struct/class keyword of the definition.
 - Move AddSignalHandler into the namespace where it belongs.
 - Correctly call functions from template base.
 - Some other small changes.
With this patch, LLVM and Clang should build properly and with far less noise under VS2008.

llvm-svn: 67347
2009-03-19 23:26:52 +00:00
Evan Cheng 1361cbbb0b Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.
llvm-svn: 67335
2009-03-19 20:30:06 +00:00
Evan Cheng f0bfc6a675 Fix how livein live intervals are handled. Previously it could end at MBB start. Sorry, no small test case possible.
llvm-svn: 66129
2009-03-05 03:34:26 +00:00
Evan Cheng b3783639cb Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register.
llvm-svn: 64082
2009-02-08 11:04:35 +00:00
Evan Cheng 76a2736c74 Exit with nice warnings when register allocator run out of registers.
llvm-svn: 63267
2009-01-29 02:20:59 +00:00
Evan Cheng c544cb0eca Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
llvm-svn: 62600
2009-01-20 19:12:24 +00:00
Evan Cheng f6768bd9cb The coalescer does not coalesce a virtual register to a physical register if any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away:
v1024 = EDI  // not killed
      =
      = EDI

One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead.

This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions.

llvm-svn: 61847
2009-01-07 02:08:57 +00:00
Evan Cheng 0869f78555 Fix PR3149. If an early clobber def is a physical register and it is tied to an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this.
172     %ECX<def> = MOV32rr %reg1039<kill>
180     INLINEASM <es:subl $5,$1
        sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
188     %EAX<def> = MOV32rr %EAX<kill>
196     %ECX<def> = MOV32rr %ECX<kill>
204     %ECX<def> = MOV32rr %ECX<kill>
212     %EAX<def> = MOV32rr %EAX<kill>
220     %EAX<def> = MOV32rr %EAX
228     %reg1039<def> = MOV32rr %ECX<kill>

The early clobber operand ties ECX input to the ECX def.

The live interval of ECX is represented as this:
%reg20,inf = [46,47:1)[174,230:0)  0@174-(230) 1@46-(47)

The right way to represent this is something like
%reg20,inf = [46,47:2)[174,182:1)[181:230:0)  0@174-(182) 1@181-230 @2@46-(47)

Of course that won't work since that means overlapping live ranges defined by two val#.

The workaround for now is to add a bit to val# which says the val# is redefined by a early clobber def somewhere. This prevents the move at 228 from being optimized away by SimpleRegisterCoalescing::AdjustCopiesBackFrom.

llvm-svn: 61259
2008-12-19 20:58:01 +00:00
Dan Gohman 9de2ac8e8b Clarify some comments.
llvm-svn: 60683
2008-12-08 04:53:23 +00:00
Evan Cheng 43c0891838 Reason #3 from 60595 doesn't hold true. If we can fold a PIC load from constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing.
llvm-svn: 60596
2008-12-05 17:41:31 +00:00
Evan Cheng 994faaf218 Fix comment.
llvm-svn: 60592
2008-12-05 17:00:16 +00:00
Dan Gohman d24be45d99 Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.
llvm-svn: 60586
2008-12-05 05:45:42 +00:00
Dan Gohman 69cc2cbbff Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
llvm-svn: 60487
2008-12-03 18:15:48 +00:00
Dan Gohman 3336b1f06b LiveRanges are represented as half-open ranges. Fix the findLiveInMBBs code
and the LiveInterval.h top-level comment and accordingly. This fixes blocks
having spurious live-in registers in boundary cases.

llvm-svn: 60092
2008-11-26 05:50:31 +00:00
Devang Patel cb181bb203 Silence unused variable warnings.
llvm-svn: 59841
2008-11-21 20:00:59 +00:00
Dan Gohman 8fed4ce0b8 Use find_first/find_next to iterate through all the set bits in a
BitVector, instead of manually testing each bit.

llvm-svn: 59246
2008-11-13 16:31:27 +00:00
Dan Gohman 5efcb61337 Remove some debugging code made redundant by the change to do
coalescing as a separate pass rather than inside of
LiveIntervalAnalysis.

llvm-svn: 59146
2008-11-12 17:09:23 +00:00
Evan Cheng 938e201528 - Rewrite code that update register live interval that's split.
- Create and update spill slot live intervals.
- Lots of bug fixes.

llvm-svn: 58367
2008-10-29 05:06:14 +00:00
David Greene b00b267bcc Fix PR2634. Create new virtual registers from spills early so that we
can give it the same stack slot as the spilled interval if it is folded.
This prevents the fold/unfold code from pointing to the wrong register.

llvm-svn: 58255
2008-10-27 17:38:59 +00:00
Evan Cheng 4bac4d0a16 Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now).
llvm-svn: 58068
2008-10-24 02:05:00 +00:00
Evan Cheng 2dadd3bbc6 By min, I mean max.
llvm-svn: 57766
2008-10-18 05:21:37 +00:00
Evan Cheng ac4e70d946 When creating intervals, leave min(1, numdefs) holes after each instruction.
llvm-svn: 57765
2008-10-18 05:18:55 +00:00
Owen Anderson 1d338fc6a4 Add an option to enable StrongPHIElimination, for ease of testing.
llvm-svn: 57259
2008-10-07 20:22:28 +00:00
Dan Gohman 0d1e9a8e04 Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006
2008-10-03 15:45:36 +00:00
Owen Anderson f4a36407c7 Fix a simple error in renumbering kill markaers, that took an inordinant amount of time to track down.
llvm-svn: 56889
2008-09-30 22:51:54 +00:00
Evan Cheng 9156bd2f48 Re-apply 56835 along with header file changes.
llvm-svn: 56848
2008-09-30 15:44:16 +00:00
Duncan Sands 2b9adce1d0 Revert commit 56835 since it breaks the build.
"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".

llvm-svn: 56837
2008-09-30 10:00:30 +00:00
Evan Cheng 9469049f7d If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
llvm-svn: 56835
2008-09-30 06:36:58 +00:00
Dale Johannesen c36660d756 Next round of earlyclobber handling. Approach the
RA problem by expanding the live interval of an
earlyclobber def back one slot.  Remove
overlap-earlyclobber throughout.  Remove 
earlyclobber bits and their handling from
live internals.

llvm-svn: 56539
2008-09-24 01:07:17 +00:00
Owen Anderson df8f1cb995 Fetch the starting index of the block when assigning intervals. This gets live-in indices
correct in the presence of things like EH labels.

llvm-svn: 56410
2008-09-21 20:43:24 +00:00
Dale Johannesen e519bd4183 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
and redo as linked list walk.  Logic moved into RA.
Per review feedback.

llvm-svn: 56326
2008-09-19 01:02:35 +00:00
Dale Johannesen f8610ebebc Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
2008-09-17 21:13:11 +00:00
Owen Anderson 82ab1e7280 Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
instruction.  Also, their valno's should have an unknown def.  This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.

llvm-svn: 56231
2008-09-15 22:00:38 +00:00
Dan Gohman 38453eebdc Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Owen Anderson 2a458775db Allow the fast-path spilling code to attempt folding, but still leaving out remat and splitting.
llvm-svn: 55012
2008-08-19 22:12:11 +00:00
Owen Anderson c75ae13566 The fast-path still needs to set kill markers and spill/restore points as appropriate.
With this patch, all of MultiSource/Applications and all of SPEC2000/2006 pass with
the SimpleSpiller and this fast-path enabled.

llvm-svn: 55000
2008-08-19 20:09:52 +00:00
Owen Anderson 442dc6fed0 Add a flag to enable the fast spilling path.
llvm-svn: 54958
2008-08-19 00:17:30 +00:00
Owen Anderson a57c57067d Fix a few more bugs:
1) Assign stack slots to new temporaries.
  2) Don't insert an interval into the return vector more than once.

llvm-svn: 54956
2008-08-18 23:41:04 +00:00
Owen Anderson 60f6b2cac0 Fix several bugs in the new fast-path:
1) Remove an incorrect assertion.
  2) Set the stack slot weight properly.
  3) Resize the VirtRegMap when needed.

llvm-svn: 54949
2008-08-18 21:20:32 +00:00
Owen Anderson e996a12f27 Clients of addIntervalForSpills expect the added intervals to be returned sorted by starting index.
llvm-svn: 54939
2008-08-18 19:52:22 +00:00
Owen Anderson 75e27d2402 Simplify the fast-patch interval spilling by using MachineRegisterInfo::reg_iterator.
llvm-svn: 54930
2008-08-18 18:38:12 +00:00
Owen Anderson cc9314ba32 Resurrect some ancient code to add spill ranges without attempting folding, remat, or splitting. This code has been updated to current APIs
in so far as it compiles and, in theory, works, but does not take advantage of recent advancements.  For instance, it could be improved by using
MachineRegisterInfo::use_iterator.

llvm-svn: 54924
2008-08-18 18:05:32 +00:00
Owen Anderson 706f6b7899 Expunge the last uses of std::map from LiveIntervals.
llvm-svn: 54766
2008-08-13 22:28:50 +00:00
Owen Anderson 767b5cc7fd Move r2iMap_ over to DenseMap from std::map.
llvm-svn: 54765
2008-08-13 22:08:30 +00:00
Owen Anderson 51f689a652 Make the allocation of LiveIntervals explicit, rather than holding them in the r2iMap_ by value. This will prevent references to them from being invalidated
if the map is changed.

llvm-svn: 54763
2008-08-13 21:49:13 +00:00
Owen Anderson d184929176 Oops, didn't mean to commit this.
llvm-svn: 54425
2008-08-06 20:58:38 +00:00
Owen Anderson 03dddbbed5 Only remap each VNInfo once when doing renumbering.
llvm-svn: 54420
2008-08-06 18:35:45 +00:00
Owen Anderson 7b5f535590 Value numbers whose def index is a special sentinel value should not be remapped.
llvm-svn: 54218
2008-07-30 17:42:47 +00:00
Owen Anderson e9a0bae238 More fixes for corner cases when remapping live range indices.
llvm-svn: 54186
2008-07-30 00:22:56 +00:00
Owen Anderson 2532e75933 Don't decrement the BB remap when we don't need to.
llvm-svn: 54173
2008-07-29 21:15:44 +00:00
Dan Gohman 804c95df52 Fold the useful features of alist and alist_node into ilist, and
a new ilist_node class, and remove them. Unlike alist_node,
ilist_node doesn't attempt to manage storage itself, so it avoids
the associated problems, including being opaque in gdb.

Adjust the Recycler class so that it doesn't depend on alist_node.
Also, change it to use explicit Size and Align parameters, allowing
it to work when the largest-sized node doesn't have the greatest
alignment requirement.

Change MachineInstr's MachineMemOperand list from a pool-backed
alist to a std::list for now.

llvm-svn: 54146
2008-07-28 21:51:04 +00:00
Dan Gohman 24b3ce1db6 Fix a typo in a comment.
llvm-svn: 54136
2008-07-28 18:43:51 +00:00
Owen Anderson 7a45b168ac Revert my previous patch. In retrospect, this is completely the wrong way to fix this problem.
llvm-svn: 54072
2008-07-25 23:06:59 +00:00
Owen Anderson 074f9db2fd Special cases are needed in renumbering when dealing with renumbering after a PHI has been removed. The interval previously defined
by the PHI needs to be extended to the beginning of its basic block, and the intervals that were inputs need to be trimmed to the end 
of their basic blocks.

llvm-svn: 54070
2008-07-25 22:32:01 +00:00
Owen Anderson 88499a3503 Properly remap live ranges whose end indices are the end of the function.
llvm-svn: 54061
2008-07-25 21:07:13 +00:00
Owen Anderson c7d53fd331 Make the remapping of interval indices (particularly ending indices) more robust.
This is tricky business, and will probably take a few more iterations to get
the last kinks out of it.

llvm-svn: 54043
2008-07-25 19:50:48 +00:00
Dan Gohman 394ec3ab5a Disable the new aggressive remat logic introduced in 54000; it causes some
regressions, such as PR2595. Also, there is a significant code-quality
issue in SPEC 464.h264ref and a few others.

llvm-svn: 54014
2008-07-25 15:08:37 +00:00
Dan Gohman 09b0448dbc Enable rematerialization of constants using AliasAnalysis::pointsToConstantMemory,
and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow
constants to be rematerialized in PIC mode -- the extra indirection is a
complication.

llvm-svn: 54000
2008-07-25 00:02:30 +00:00
Owen Anderson 50d393a68d Enable the insertion of empty indices into LiveInterals, thereby making renumbering possible.
llvm-svn: 53961
2008-07-23 21:37:49 +00:00
Owen Anderson 7c800ad977 Fix a compile-time regression introduced by my heuristic-changing patch. I forgot
to multiply the instruction count by a constant factor in a few places, which
caused the register allocator to require many more iterations.

llvm-svn: 53959
2008-07-23 19:47:27 +00:00
Owen Anderson 029182f3a3 Change the heuristics used in the coalescer, register allocator, and within
live intervals itself to use an instruction count approximation that is 
not affected by inserting empty indices.

llvm-svn: 53937
2008-07-22 22:46:49 +00:00
Evan Cheng a7a20c4946 Fix a memory leak in LiveIntervalAnalysis.
llvm-svn: 53779
2008-07-19 00:37:25 +00:00
Dan Gohman 0ece943845 Re-introduce LeakDetector support for MachineInstrs and MachineBasicBlocks.
Fix a leak that this turned up in LowerSubregs.cpp.
And, comment a leak in LiveIntervalAnalysis.cpp.

llvm-svn: 53746
2008-07-17 23:49:46 +00:00
Evan Cheng 2b3c52d5c4 Typos.
llvm-svn: 53504
2008-07-12 02:22:07 +00:00
Evan Cheng e0a352e8e7 Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g.
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.

llvm-svn: 53503
2008-07-12 01:56:02 +00:00
Evan Cheng e9ba28dd68 - Change the horrible N^2 isRegReDefinedByTwoAddr. Now callers must supply the operand index of def machineoperand and at most one full scan of non-implicit operands is needed.
- Change local register allocator to use the new isRegReDefinedByTwoAddr instead of reinventing the wheel.

llvm-svn: 53394
2008-07-10 07:35:43 +00:00
Dan Gohman 3b46030375 Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212
2008-07-07 23:14:23 +00:00
Evan Cheng 7d98a48f15 - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.

llvm-svn: 53097
2008-07-03 09:09:37 +00:00
Owen Anderson b55675e1db Remember which MachineOperand we were processing, so we don't have to scan the list to find it again later.
This speeds up live intervals from 0.37s to 0.30s on instcombine.

llvm-svn: 52745
2008-06-25 23:39:39 +00:00
Evan Cheng f593a65497 Undo spill weight tweak. Need to investigate the performance regressions.
llvm-svn: 52572
2008-06-21 06:45:54 +00:00
Owen Anderson 3c4ccc830e Revert my last patch, which was causing regression test failures.
llvm-svn: 52485
2008-06-19 05:29:34 +00:00
Evan Cheng 55bc848640 Minor spiller tweak to unfavor reload into load/store instructions.
llvm-svn: 52477
2008-06-19 01:16:17 +00:00
Owen Anderson 80ef880b98 Insert empty slots into the instruction numbering in live intervals, so that we can more easily
add new instructions.

llvm-svn: 52475
2008-06-19 00:10:49 +00:00
Evan Cheng f873ed1b10 Live-through live interval is [mbb start, mbb end+1].
llvm-svn: 52431
2008-06-17 20:13:36 +00:00
Owen Anderson 476e91ab75 Remove special case handling of empty MBBs now that we assign indices to them.
llvm-svn: 52345
2008-06-16 19:32:40 +00:00
Owen Anderson 773b2d3ac3 Re-enable empty block indexing by default, since it doesn't seem to have any
impact on code quality or compile time.

llvm-svn: 52329
2008-06-16 16:58:24 +00:00
Owen Anderson e546c55e59 Make indexing empty basic blocks an option for the moment.
llvm-svn: 52306
2008-06-16 07:10:49 +00:00
Owen Anderson d813091cde Assign indices to empty basic blocks. This will be necessary for StrongPHIElimination in the near future.
llvm-svn: 52300
2008-06-16 06:18:41 +00:00
Evan Cheng 6d7a144453 Refine stack slot interval weight computation.
llvm-svn: 52040
2008-06-06 07:54:39 +00:00
Owen Anderson 35e2dfe1cf Add a helper for constructing new live ranges that ended from an instruction to the end of its MBB.
llvm-svn: 52012
2008-06-05 17:15:43 +00:00
Evan Cheng 12a0222a01 Add a stack slot coloring pass. Not yet enabled.
llvm-svn: 51934
2008-06-04 09:18:41 +00:00
Owen Anderson 0908deccc2 Correctly handle removed instructions at the beginning of MBBs when renumbering.
llvm-svn: 51876
2008-06-02 17:36:36 +00:00
Owen Anderson 82fc4cdafb Make the renumbering correct in the face of deleted instructions that have been removed from the LiveIntervals maps.
llvm-svn: 51714
2008-05-29 23:01:22 +00:00
Bill Wendling bf5b228c32 Remove <iostream>.
llvm-svn: 51704
2008-05-29 21:29:39 +00:00
Owen Anderson d95dcd12c9 Revert part of my last patch that I didn't intend to commit yet.
llvm-svn: 51694
2008-05-29 18:35:21 +00:00
Owen Anderson 0178e95791 Renumbering needs to account for instruction slot offsets when performing lookups in the index maps.
llvm-svn: 51691
2008-05-29 18:15:49 +00:00
Owen Anderson 779b4180dc Remap VNInfo data as well when doing renumbering.
llvm-svn: 51658
2008-05-28 22:40:08 +00:00
Owen Anderson 4f8e1ad32a Factor the numbering computation into a separate method, and add the slightest attempt at some renumbering logic, which is currently unused.
llvm-svn: 51652
2008-05-28 20:54:50 +00:00
Evan Cheng 7c0db62a5e Revert 51440 as it breaks a bunch of PIC tests.
llvm-svn: 51513
2008-05-23 23:00:04 +00:00
David Greene 830487035e When rewriting defs and uses after spilling, don't set the weight of a
live interval to infinity if the instruction being rewritten is an
original remat def instruction.  We were only checking against the clone
of the remat def which doesn't actually appear in the IR at all.

llvm-svn: 51440
2008-05-22 21:16:33 +00:00
Evan Cheng c8b028daa4 Don't spill dead def.
llvm-svn: 51305
2008-05-20 08:10:37 +00:00
Dan Gohman d78c400b5b Clean up the use of static and anonymous namespaces. This turned up
several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017
2008-05-13 00:00:25 +00:00
Dan Gohman 6a2da37c0e Make several variable declarations static.
llvm-svn: 50696
2008-05-06 01:53:16 +00:00
Evan Cheng 8dc8a8d8af Empty basic block should have an empty range.
llvm-svn: 49800
2008-04-16 18:01:08 +00:00
Evan Cheng 499ffa9055 Use of implicit_def is not part of live interval. Create empty intervals for the uses when the live interval is being spilled.
llvm-svn: 49542
2008-04-11 17:53:36 +00:00
Evan Cheng c8eeb752a3 - More aggressively coalescing away copies whose source is defined by an implicit_def.
- Added insert_subreg coalescing support.

llvm-svn: 49448
2008-04-09 20:57:25 +00:00
Evan Cheng 20aed56504 - Treat a live range defined by an implicit_def as a zero-sized one.
- Eliminate an implicit_def when it's being spilled.

llvm-svn: 49166
2008-04-03 16:39:43 +00:00
Evan Cheng 985a0b51d7 Re-materialization is for uses only.
llvm-svn: 49053
2008-04-01 21:37:32 +00:00
Evan Cheng e4f77c69ac It's not safe to fold a load from GV stub or constantpool into a two-address use.
llvm-svn: 49002
2008-03-31 23:19:51 +00:00
Evan Cheng 73d7c3bfba The support for remat of instructions with a register operand is hackish, to say the least. Since the register operand guaranteed to be PIC base and that it is already live at all uses, we are making sure it will not be spilled after its uses are rematerialized for both performance and correctness reasons.
llvm-svn: 48976
2008-03-31 07:53:30 +00:00
Evan Cheng ec7533b620 Remove isImplicitDef TargetInstrDesc flag.
llvm-svn: 48381
2008-03-15 00:19:36 +00:00
Evan Cheng a3891365b5 Transfer physical register spill info when load / store folding happens.
llvm-svn: 48246
2008-03-11 21:34:46 +00:00
Evan Cheng e88a625ecd When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
llvm-svn: 48218
2008-03-11 07:19:34 +00:00
Evan Cheng 6325446666 Refactor code. Remove duplicated functions that basically do the same thing as
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.

llvm-svn: 47927
2008-03-05 00:59:57 +00:00
Evan Cheng 6d56368caf Spiller now remove unused spill slots.
llvm-svn: 47657
2008-02-27 03:04:06 +00:00
Bill Wendling d7a258d325 Rename PrintableName to Name.
llvm-svn: 47629
2008-02-26 21:47:57 +00:00
Bill Wendling c24ea4fb41 Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!

llvm-svn: 47625
2008-02-26 21:11:01 +00:00
Evan Cheng 548677022c All remat'ed loads cannot be folded into two-address code. Not just argument loads. This change doesn't really have any impact on codegen.
llvm-svn: 47557
2008-02-25 19:24:01 +00:00
Evan Cheng 589a9fb6dc Correctly determine whether a argument load can be folded into its uses.
llvm-svn: 47545
2008-02-25 08:50:41 +00:00
Evan Cheng 504c645b3e Rematerialization logic was overly conservative when it comes to loads from fixed stack slots.
llvm-svn: 47529
2008-02-23 03:38:34 +00:00
Evan Cheng 379682b0e5 If remating a machine instr with virtual register operand, make sure the vr is avaliable at all uses regardless of whether it would be folded.
llvm-svn: 47526
2008-02-23 02:14:42 +00:00
Evan Cheng e70afb021b Recognize loads of arguments as re-materializable first. Therefore if isReallyTriviallyReMaterializable() returns true it doesn't confuse it as a "normal" re-materializable instruction.
llvm-svn: 47520
2008-02-23 01:44:27 +00:00
Evan Cheng 4f5cb4cdac Fix spill weight updating bug.
llvm-svn: 47507
2008-02-23 00:33:04 +00:00
Evan Cheng c373911461 Enable re-materialization of instructions which have virtual register operands if
the definition of the operand also reaches its uses.

llvm-svn: 47475
2008-02-22 09:24:50 +00:00
Evan Cheng 911f6bd799 Clean up some spilling code using MachineRegisterInfo.
llvm-svn: 47416
2008-02-21 00:34:19 +00:00
Roman Levenstein 0b2c8858df New helper function getMBBFromIndex() that given an index in any instruction of an MBB returns a pointer the MBB. Reviewed by Evan.
llvm-svn: 47267
2008-02-18 09:35:30 +00:00
Evan Cheng 2ff2da89ab - Removing the infamous r2rMap_ and rep() method. Now the coalescer will update
register defs and uses after each successful coalescing.
- Also removed a number of hacks and fixed some subtle kill information bugs.

llvm-svn: 47167
2008-02-15 18:24:29 +00:00
Evan Cheng bb4b97f90e Fix a potential serious problem where kills belonging to the val# defined by a two-address instruction is also on the val# that defines the input.
llvm-svn: 47057
2008-02-13 09:06:18 +00:00
Dan Gohman 3a4be0fdef Rename MRegisterInfo to TargetRegisterInfo.
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
Evan Cheng f2bd1387b0 Forgot these files.
llvm-svn: 46896
2008-02-08 22:05:27 +00:00
Owen Anderson 2a8a485630 Move some functionality for adding flags to MachineInstr's into methods on MachineInstr rather than LiveVariables.
llvm-svn: 46295
2008-01-24 01:10:07 +00:00
Evan Cheng f2553ab84f Only remat loads from immutable stack slots.
llvm-svn: 45831
2008-01-10 08:24:38 +00:00
Evan Cheng 8b03bafd37 Simplify some code.
llvm-svn: 45830
2008-01-10 08:22:10 +00:00
Owen Anderson d445b8813f Don't use LiveVariables::VarInfo::DefInst.
llvm-svn: 45815
2008-01-10 03:12:54 +00:00
Chris Lattner 03ad885039 rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
2008-01-07 07:27:27 +00:00
Chris Lattner 769c86bf63 simplify some code using new predicates
llvm-svn: 45689
2008-01-07 05:40:58 +00:00
Chris Lattner a98c679de0 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674
2008-01-07 01:56:04 +00:00
Owen Anderson 0ec92e9d64 Update CodeGen for MRegisterInfo --> TargetInstrInfo changes.
llvm-svn: 45673
2008-01-07 01:35:56 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Bill Wendling 0c209430b4 Don't recalculate the loop info and loop dominators analyses if they're
preserved.

llvm-svn: 45596
2008-01-04 20:54:55 +00:00
Chris Lattner a10fff51d9 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467
2007-12-31 04:13:23 +00:00
Chris Lattner 6005589faf More cleanups for MachineOperand:
- Eliminate the static "print" method for operands, moving it
    into MachineOperand::print.
  - Change various set* methods for register flags to take a bool
    for the value to set it to.  Remove unset* methods.
  - Group methods more logically by operand flavor in MachineOperand.h

llvm-svn: 45461
2007-12-30 21:56:09 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng 6e68381e02 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
llvm-svn: 44960
2007-12-12 23:12:09 +00:00
Evan Cheng 303417d242 Switch over to MachineLoopInfo.
llvm-svn: 44838
2007-12-11 02:09:15 +00:00
Bill Wendling 3f19dfe794 Reverting 44702. It wasn't correct to rename them.
llvm-svn: 44727
2007-12-08 23:58:46 +00:00
Bill Wendling 2b07d8c5a0 Renaming:
isTriviallyReMaterializable -> hasNoSideEffects
  isReallyTriviallyReMaterializable -> isTriviallyReMaterializable

llvm-svn: 44702
2007-12-08 07:17:56 +00:00
Evan Cheng 8393dc7378 Turning simple splitting on. Start testing new coalescer heuristics as new llcbeta.
llvm-svn: 44660
2007-12-06 08:54:31 +00:00
Evan Cheng 7fc1d98353 Fix for PR1831: if all defs of an interval are re-materializable, then it's a preferred spill candiate.
llvm-svn: 44644
2007-12-06 00:01:56 +00:00
Evan Cheng 678b86d6ce MachineInstr can change. Store indexes instead.
llvm-svn: 44612
2007-12-05 10:24:35 +00:00
Evan Cheng 06353b48b5 If a split live interval is spilled again, remove the kill marker on its last use.
llvm-svn: 44611
2007-12-05 09:51:10 +00:00
Evan Cheng 64b3baaaea Clobber more bugs.
llvm-svn: 44610
2007-12-05 09:05:34 +00:00
Evan Cheng d7de56ac93 Fix kill info for split intervals.
llvm-svn: 44609
2007-12-05 08:16:32 +00:00
Evan Cheng 269dbd31d0 - Mark last use of a split interval as kill instead of letting spiller track it.
This allows an important optimization to be re-enabled.
- If all uses / defs of a split interval can be folded, give the interval a
  low spill weight so it would not be picked in case spilling is needed (avoid
  pushing other intervals in the same BB to be spilled).

llvm-svn: 44601
2007-12-05 03:22:34 +00:00
Evan Cheng d1badb960e Discard split intervals made empty due to folding.
llvm-svn: 44565
2007-12-04 00:32:23 +00:00
Evan Cheng 196faa9dc5 Typo
llvm-svn: 44532
2007-12-03 10:00:00 +00:00
Evan Cheng 85ef9834a6 Update kill info for uses of split intervals.
llvm-svn: 44531
2007-12-03 09:58:48 +00:00
Evan Cheng f45a1d623c Remove redundant foldMemoryOperand variants and other code clean up.
llvm-svn: 44517
2007-12-02 08:30:39 +00:00