Commit Graph

18288 Commits

Author SHA1 Message Date
Benjamin Kramer 15cd5a3f12 Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.
llvm-svn: 135126
2011-07-14 01:38:42 +00:00
Eli Friedman bc2ae1c865 Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate.
llvm-svn: 135120
2011-07-14 00:22:31 +00:00
Jim Grosbach a0958d7abf ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116
2011-07-14 00:18:13 +00:00
Jim Grosbach 56a20a492b DMB instalias needs the same predicate as the instruction.
llvm-svn: 135112
2011-07-14 00:10:26 +00:00
Jim Grosbach 44c3f08e85 ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
2011-07-13 23:40:38 +00:00
Jim Grosbach 199b683a6e Update comments. These are for assembler, too.
llvm-svn: 135107
2011-07-13 23:33:10 +00:00
Owen Anderson 651b230ca0 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
Bill Wendling d11ea81db0 Add code to handle a "frameless" unwind stack.
The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".

llvm-svn: 135103
2011-07-13 23:03:31 +00:00
Jim Grosbach 507ba77465 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
2011-07-13 22:59:38 +00:00
Jim Grosbach c5b4019a0d Revert 135093. Think-o.
llvm-svn: 135094
2011-07-13 22:06:11 +00:00
Jim Grosbach ccc207773d Correct range for thumb co-processor immediate
llvm-svn: 135093
2011-07-13 22:03:11 +00:00
Jim Grosbach 31756c2283 Range checking for CDP[2] immediates.
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes 9613b64916 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

llvm-svn: 135088
2011-07-13 21:36:51 +00:00
Bruno Cardoso Lopes 7ba479d22f The target specific node PANDN name is misleading. That happens because
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.

llvm-svn: 135087
2011-07-13 21:36:47 +00:00
Jim Grosbach ca7150b54d Cleanup Thumb co-processor instructions a bit.
Combine redundant base classes and such. No indended functional change.

llvm-svn: 135085
2011-07-13 21:35:10 +00:00
Eli Friedman 344ec79715 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
<rdar://problem/9763308>

llvm-svn: 135084
2011-07-13 21:29:53 +00:00
Jim Grosbach cabb48d511 Parameterize away the ARM T1Cop class.
llvm-svn: 135082
2011-07-13 21:17:59 +00:00
Jim Grosbach adb29b6dbb Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
2011-07-13 21:14:23 +00:00
Eli Friedman ef67e7d623 Refactor out checking for displacements on x86-64 addressing modes. No functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress.
Part of <rdar://problem/9763308>.

llvm-svn: 135079
2011-07-13 20:44:23 +00:00
Jim Grosbach e2f9840cdb Fix encoding for ARM BXJ instruction.
llvm-svn: 135077
2011-07-13 20:25:01 +00:00
Jim Grosbach 801d3ad1b2 Fix encoding of predicate bits on ARM BX_pred.
llvm-svn: 135076
2011-07-13 20:21:31 +00:00
Jim Grosbach 975b641ee8 Range checking for 16-bit immediates in ARM assembly.
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Evan Cheng 2d7faa5e3e Fix up TargetLoweringObjectFile ctors to properly initialize fields.
llvm-svn: 135068
2011-07-13 19:54:59 +00:00
Jim Grosbach e255be93a8 Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.

llvm-svn: 135066
2011-07-13 19:24:09 +00:00
Jim Grosbach c845e55374 Add tests for ARM parsing of 'BKPT' instruction.
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach bb24c595f7 Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

llvm-svn: 135055
2011-07-13 18:49:30 +00:00
Jim Grosbach 04afb071e1 Destination register operand is optional for ADC and SBC ARM.
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach 7dcd1354f1 Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Jim Grosbach 06210a28de 80 columns.
llvm-svn: 135047
2011-07-13 17:25:55 +00:00
Jim Grosbach 602aa90ab8 Update MCParsedAsmOperand debug methods.
Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.

llvm-svn: 135043
2011-07-13 15:34:57 +00:00
Jay Foad 57aa636794 Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.
llvm-svn: 135040
2011-07-13 10:26:04 +00:00
Evan Cheng 21e9051922 Add an entry.
llvm-svn: 135024
2011-07-13 01:33:00 +00:00
Bruno Cardoso Lopes 1021b4a9dd AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
llvm-svn: 135023
2011-07-13 01:15:33 +00:00
Bill Wendling ee6e776be2 Don't emit the FDE end label if the last thing emitted was a compact unwind and
not the FDE

llvm-svn: 135020
2011-07-13 00:49:09 +00:00
Eli Friedman 16323380cd Add an assert (which should never trigger) that triggers on a testcase I'm looking at.
llvm-svn: 135018
2011-07-13 00:44:29 +00:00
Evan Cheng f863e3fb73 Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317

llvm-svn: 135017
2011-07-13 00:42:17 +00:00
Bill Wendling 0402e8fe4b Assign variable before we test it.
llvm-svn: 135015
2011-07-13 00:23:39 +00:00
Bill Wendling ed3c44224b Fix obvious think-o.
llvm-svn: 135014
2011-07-13 00:20:09 +00:00
Bill Wendling 929b90ff32 Clean up the handling of an EBP/RBP unwind frame pointer. In particular, don't
assert when the frame pointer is -1 (i.e., the function is "frameless").

Still to do: "frameless" unwind information.

llvm-svn: 135013
2011-07-13 00:16:14 +00:00
Bill Wendling 5d11676eef There is a cyclic dependency between MC and Target if this method is out-of-line.
llvm-svn: 135006
2011-07-12 22:35:01 +00:00
Jay Foad b804a2b751 Second attempt at de-constifying LLVM Types in FunctionType::get(),
StructType::get() and TargetData::getIntPtrType().

llvm-svn: 134982
2011-07-12 14:06:48 +00:00
Tobias Grosser 6c3501d5c6 Remove IntegerType constness from TargetData
llvm-svn: 134978
2011-07-12 11:36:58 +00:00
Bill Wendling a78cd228c2 Revert r134893 and r134888 (and related patches in other trees). It was causing
an assert on Darwin llvm-gcc builds.

Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.

http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354

--- Reverse-merging r134893 into '.':
U    include/llvm/Target/TargetData.h
U    include/llvm/DerivedTypes.h
U    tools/bugpoint/ExtractFunction.cpp
U    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/ARM/ARMGlobalMerge.cpp
U    lib/Target/TargetData.cpp
U    lib/VMCore/Constants.cpp
U    lib/VMCore/Type.cpp
U    lib/VMCore/Core.cpp
U    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Instrumentation/ProfilingUtils.cpp
U    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G    include/llvm/DerivedTypes.h
U    include/llvm/Support/TypeBuilder.h
U    include/llvm/Intrinsics.h
U    unittests/Analysis/ScalarEvolutionTest.cpp
U    unittests/ExecutionEngine/JIT/JITTest.cpp
U    unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U    unittests/VMCore/PassManagerTest.cpp
G    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U    lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U    lib/VMCore/IRBuilder.cpp
G    lib/VMCore/Type.cpp
U    lib/VMCore/Function.cpp
G    lib/VMCore/Core.cpp
U    lib/VMCore/Module.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/Transforms/Utils/CloneFunction.cpp
G    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Utils/InlineFunction.cpp
U    lib/Transforms/Instrumentation/GCOVProfiling.cpp
U    lib/Transforms/Scalar/ObjCARC.cpp
U    lib/Transforms/Scalar/SimplifyLibCalls.cpp
U    lib/Transforms/Scalar/MemCpyOptimizer.cpp
G    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/Transforms/IPO/ArgumentPromotion.cpp
U    lib/Transforms/InstCombine/InstCombineCompares.cpp
U    lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U    lib/Transforms/InstCombine/InstCombineCalls.cpp
U    lib/CodeGen/DwarfEHPrepare.cpp
U    lib/CodeGen/IntrinsicLowering.cpp
U    lib/Bitcode/Reader/BitcodeReader.cpp

llvm-svn: 134949
2011-07-12 01:15:52 +00:00
Evan Cheng 58a98141d9 Most MCCodeEmitter's don't meed MCContext.
llvm-svn: 134922
2011-07-11 21:24:15 +00:00
Jim Grosbach a9a3f0a414 Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.

llvm-svn: 134903
2011-07-11 17:09:57 +00:00
Jim Grosbach 581da64241 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

llvm-svn: 134902
2011-07-11 16:48:36 +00:00
Jay Foad 7c57be3e2b De-constify Types in StructType::get() and TargetData::getIntPtrType().
llvm-svn: 134893
2011-07-11 09:56:20 +00:00
Jay Foad 56cc1530ee De-constify Types in FunctionType::get().
llvm-svn: 134888
2011-07-11 07:56:41 +00:00
Evan Cheng c5e6d2f519 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Cameron Zwarich 776403b642 Fix <rdar://problem/9751331>.
llvm-svn: 134882
2011-07-11 01:29:42 +00:00
Jakub Staszak 9b07c0ab6b Use BranchProbability instead of floating points in IfConverter.
llvm-svn: 134858
2011-07-10 02:58:07 +00:00
Chris Lattner b1ed91f397 Land the long talked about "type system rewrite" patch. This
patch brings numerous advantages to LLVM.  One way to look at it
is through diffstat:
 109 files changed, 3005 insertions(+), 5906 deletions(-)

Removing almost 3K lines of code is a good thing.  Other advantages
include:

1. Value::getType() is a simple load that can be CSE'd, not a mutating
   union-find operation.
2. Types a uniqued and never move once created, defining away PATypeHolder.
3. Structs can be "named" now, and their name is part of the identity that
   uniques them.  This means that the compiler doesn't merge them structurally
   which makes the IR much less confusing.
4. Now that there is no way to get a cycle in a type graph without a named
   struct type, "upreferences" go away.
5. Type refinement is completely gone, which should make LTO much MUCH faster
   in some common cases with C++ code.
6. Types are now generally immutable, so we can use "Type *" instead 
   "const Type *" everywhere.

Downsides of this patch are that it removes some functions from the C API,
so people using those will have to upgrade to (not yet added) new API.  
"LLVM 3.0" is the right time to do this.

There are still some cleanups pending after this, this patch is large enough
as-is.

llvm-svn: 134829
2011-07-09 17:41:24 +00:00
Evan Cheng 21a9772ac1 Revert accidental commit.
llvm-svn: 134800
2011-07-09 06:26:27 +00:00
Evan Cheng 91111d2706 Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795
2011-07-09 05:47:46 +00:00
Eli Friedman fe2088bb1f Really force on 64bit for 64-bit targets. Should fix remaining failures on unknown x86/non-x86 targets.
llvm-svn: 134773
2011-07-08 23:43:01 +00:00
Eli Friedman 5286833f4a Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets.
llvm-svn: 134768
2011-07-08 23:07:42 +00:00
Evan Cheng 45543ba4e8 Fix indentation.
llvm-svn: 134764
2011-07-08 22:49:55 +00:00
Evan Cheng 284b467d9f Add support for ARM / Thumb mode switching with .code 16 and .code 32.
llvm-svn: 134760
2011-07-08 22:36:29 +00:00
Jim Grosbach 39c67b5e08 Mark tBRIND as predicable.
llvm-svn: 134758
2011-07-08 22:33:49 +00:00
Evan Cheng 60fc0fca5c Restore old behavior. Always auto-detect features unless cpu or features are specified.
llvm-svn: 134757
2011-07-08 22:30:25 +00:00
Jim Grosbach 59a3ab6e46 Pseudo-ize tBRIND.
llvm-svn: 134755
2011-07-08 22:25:23 +00:00
Eli Friedman e2f76c4ade Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
llvm-svn: 134753
2011-07-08 22:16:47 +00:00
Jim Grosbach 7471937ad7 Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.

llvm-svn: 134746
2011-07-08 21:50:04 +00:00
Julien Lerouge 112fcc164a Add _allrem, _aullrem and _allmul to the runtime for MSVC.
http://llvm.org/bugs/show_bug.cgi?id=10305

llvm-svn: 134744
2011-07-08 21:40:25 +00:00
Cameron Zwarich f03fa189ca Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742
2011-07-08 21:39:21 +00:00
Evan Cheng 964cb5feb0 For non-x86 host, used generic as CPU name.
llvm-svn: 134741
2011-07-08 21:14:14 +00:00
Jim Grosbach d61ae786bd Pseudo-ize tBX_RET and tBX_RET_vararg.
llvm-svn: 134739
2011-07-08 21:10:35 +00:00
Benjamin Kramer debe69fb37 Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo.
Found by valgrind.

llvm-svn: 134738
2011-07-08 21:06:23 +00:00
Jim Grosbach cb1b0b7130 Shuffle productions around a bit.
No functional change.

llvm-svn: 134737
2011-07-08 21:04:05 +00:00
Jim Grosbach 204c128f66 Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.
llvm-svn: 134734
2011-07-08 20:39:19 +00:00
Jim Grosbach 4af8647e17 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
llvm-svn: 134732
2011-07-08 20:32:21 +00:00
Benjamin Kramer dbdff47cb3 Silence compiler warning.
llvm-svn: 134730
2011-07-08 20:18:13 +00:00
Jim Grosbach 3840c90f73 Add more info to FIXME.
llvm-svn: 134729
2011-07-08 20:18:11 +00:00
Jim Grosbach 166cd88645 Move Thumb tail call pseudos to Thumb.td file.
Fix a FIXME.

llvm-svn: 134727
2011-07-08 20:13:35 +00:00
Evan Cheng 22e9d8f40e TargetAsmParser doesn't need reference to Target.
llvm-svn: 134721
2011-07-08 19:33:14 +00:00
Jim Grosbach dbfb29d6c0 Use ARMPseudoExpand for ARM tail calls.
llvm-svn: 134719
2011-07-08 18:50:22 +00:00
Jim Grosbach 7ddc1d709f Shuffle productions around a bit.
No functional change.

llvm-svn: 134714
2011-07-08 18:26:27 +00:00
Jim Grosbach 2dfe8e3ccd Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712
2011-07-08 18:15:12 +00:00
Chandler Carruth f21cebf6dd Add CMake support for the new TableGen file introduced in r134705.
llvm-svn: 134707
2011-07-08 17:54:08 +00:00
Jim Grosbach 95dee40343 Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705
2011-07-08 17:40:42 +00:00
Evan Cheng 4d1ca96bfc Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678
2011-07-08 01:53:10 +00:00
Akira Hatanaka f9a85356bc Raise assertion when MachineOperand has unexpected target flag.
llvm-svn: 134671
2011-07-08 00:42:35 +00:00
Akira Hatanaka 8ccd65842d Make sure variable Kind is assigned a value to suppress warning.
llvm-svn: 134668
2011-07-08 00:26:25 +00:00
Nick Lewycky 9badf60203 Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!

llvm-svn: 134665
2011-07-08 00:19:27 +00:00
Eric Christopher 7a2a0f80de Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.

Fixes PR9675 and rdar://9740801

llvm-svn: 134664
2011-07-08 00:04:56 +00:00
Akira Hatanaka 9c6028f98e Lower MachineInstr to MC Inst and print to .s files.
llvm-svn: 134661
2011-07-07 23:56:50 +00:00
Eric Christopher 719c29702f Handle fpcr register.
Part of PR10299 and rdar://9740322

llvm-svn: 134653
2011-07-07 22:54:12 +00:00
Eric Christopher 9721396dab Add support for the X86 'l' constraint.
Fixes PR10149 and rdar://9738585

llvm-svn: 134648
2011-07-07 22:29:07 +00:00
Akira Hatanaka 28d6677a53 Remove unnecessary newline.
llvm-svn: 134645
2011-07-07 22:06:18 +00:00
Evan Cheng 13bcc6c1c7 Add Mode64Bit feature and sink it down to MC layer.
llvm-svn: 134641
2011-07-07 21:06:52 +00:00
Bill Wendling 1a423d8b35 Move a function out-of-line.
llvm-svn: 134640
2011-07-07 21:05:13 +00:00
Akira Hatanaka 9f6f6f6ecc Rather than having printMemOperand change the way memory operands are printed
based on a modifier, split it into two functions.

llvm-svn: 134637
2011-07-07 20:54:20 +00:00
Akira Hatanaka 77a9e6e7df Define class MipsMCInstLower.
llvm-svn: 134633
2011-07-07 20:24:54 +00:00
Akira Hatanaka ddd1265316 Change visibility of MipsAsmPrinter.
llvm-svn: 134630
2011-07-07 20:10:52 +00:00
Akira Hatanaka 04da3658c6 Define class MipsMCSymbolRefExpr.
llvm-svn: 134629
2011-07-07 19:27:22 +00:00
Akira Hatanaka 9d1936a270 Simplify MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134628
2011-07-07 19:13:09 +00:00
Evan Cheng 6dbe713a49 Rewrite comment in English.
llvm-svn: 134627
2011-07-07 19:09:06 +00:00
Evan Cheng 1834f5dcb6 Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
llvm-svn: 134626
2011-07-07 19:05:12 +00:00
Akira Hatanaka 2e766ed2f8 Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
2011-07-07 18:57:00 +00:00
Akira Hatanaka ac4db9251b Add missing return statement.
llvm-svn: 134622
2011-07-07 18:27:36 +00:00