6120962d7d
Add XCore intrinsic for setpsc.
...
llvm-svn: 127821
2011-03-17 18:42:05 +00:00
c871eff3f5
Add XCore intrinsics for setclk, setrdy.
...
llvm-svn: 127761
2011-03-16 21:56:00 +00:00
d4346f2388
Add checkevent intrinsic to check if any resources owned by the current thread
...
can event.
llvm-svn: 127741
2011-03-16 18:34:00 +00:00
5f1a26ea39
On the XCore the scavenging slot should be closest to the SP.
...
llvm-svn: 127680
2011-03-15 15:10:11 +00:00
3a68eb150b
Add XCore intrinsics for getps, setps, setsr and clrsr.
...
llvm-svn: 127678
2011-03-15 13:45:47 +00:00
1885d21700
Fix mistyped CHECK lines.
...
llvm-svn: 127366
2011-03-09 22:07:31 +00:00
62f759791a
Be nice to Xcore and the XMOS assembler and avoid quoting section names
...
that contain only letters, digits and the characters "_" and ".".
llvm-svn: 127028
2011-03-04 20:03:14 +00:00
852ab890b5
Bug#9033: For the ELF assembler output, always quote the section name.
...
llvm-svn: 126963
2011-03-03 22:31:08 +00:00
42f52e737e
Add XCore intrinsic for eeu instruction.
...
llvm-svn: 126384
2011-02-24 13:39:18 +00:00
bfa5cc0e08
Add XCore intrinsic for clre instruction.
...
llvm-svn: 126322
2011-02-23 18:52:05 +00:00
4995b05f56
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
...
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
llvm-svn: 126320
2011-02-23 18:35:59 +00:00
2c610aa3ed
Add XCore intrinsic for the setv instruction.
...
llvm-svn: 126315
2011-02-23 16:46:37 +00:00
aab96995f6
Add XCore intrinsic for settw instruction.
...
llvm-svn: 126313
2011-02-23 14:45:03 +00:00
1ae65c7cb8
Add XCore intrinsics for various instructions on ports.
...
llvm-svn: 126132
2011-02-21 18:23:30 +00:00
d9dde78c27
Add intrinsic for setc instruction on the XCore.
...
llvm-svn: 125186
2011-02-09 13:22:12 +00:00
a31b9c2f7c
Add XCore intrinsics for resource instructions.
...
llvm-svn: 124794
2011-02-03 13:14:25 +00:00
8607a67d37
Add support for trampolines on the XCore.
...
llvm-svn: 124722
2011-02-02 14:57:41 +00:00
272e084bca
Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.
...
llvm-svn: 124587
2011-01-31 17:41:44 +00:00
ec517cdf24
Update tests.
...
llvm-svn: 123591
2011-01-16 18:02:57 +00:00
c24048a718
If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.
...
llvm-svn: 121059
2010-12-06 22:39:26 +00:00
f3e9a48584
Enable machine sinking critical edge splitting. e.g.
...
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
%z = select i1 %c, double %a, double %y
ret double %z
}
Was:
_foo:
divsd LCPI0_0(%rip), %xmm0
testb $1, %dil
jne LBB0_2
movaps %xmm1, %xmm0
LBB0_2:
ret
Now:
_foo:
testb $1, %dil
je LBB0_2
divsd LCPI0_0(%rip), %xmm0
ret
LBB0_2:
movaps %xmm1, %xmm0
ret
This avoids the divsd when early exit is taken.
rdar://8454886
llvm-svn: 114372
2010-09-20 22:52:00 +00:00
4fee6f3bdd
Start function numbering at 0.
...
llvm-svn: 101638
2010-04-17 16:29:15 +00:00
f118f9788b
Split big test into multiple directories to cater to
...
those who don't build all targets.
llvm-svn: 100688
2010-04-07 20:43:35 +00:00
9efbbcbe45
fix AsmPrinter::GetBlockAddressSymbol to always return a unique
...
label instead of trying to form one based on the BB name (which
causes collisions if the name is empty). This fixes PR6608
llvm-svn: 98495
2010-03-14 17:53:23 +00:00
4780109254
Add dag combine to simplify lmul(x, 0, a, b)
...
llvm-svn: 98258
2010-03-11 16:26:35 +00:00
54a2c32670
Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit
...
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.
llvm-svn: 98168
2010-03-10 18:12:27 +00:00
1a396d53ed
Fold add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if the intermediate
...
results are unused elsewhere.
llvm-svn: 98157
2010-03-10 16:19:31 +00:00
f57aea3d38
Prefer LMUL to MACCU as LMUL has no tied operands.
...
llvm-svn: 98153
2010-03-10 13:27:10 +00:00
0012bc1e41
Custom lower (S|U)MUL_LOHI -> MACC(S|U)
...
llvm-svn: 98152
2010-03-10 13:20:07 +00:00
54dfa01adc
Lower add (mul a, b), c into MACCU / MACCS nodes which translate
...
directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.
llvm-svn: 98150
2010-03-10 11:41:08 +00:00
e35eabdd69
Convert test to FileCheck.
...
llvm-svn: 98148
2010-03-10 11:24:03 +00:00
c420c4cb4e
In cases where the carry / borrow unused converted ladd / lsub
...
to an add or a sub.
llvm-svn: 98059
2010-03-09 16:34:25 +00:00
f4e76cf44d
Add DAG combine for ladd / lsub.
...
llvm-svn: 98057
2010-03-09 16:07:47 +00:00
333300e0df
Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy.
...
Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.
llvm-svn: 97226
2010-02-26 16:44:51 +00:00
f578196968
Lower BR_JT on the XCore to a jump into a series of jump instructions.
...
llvm-svn: 96942
2010-02-23 13:25:07 +00:00
cc9a6f0580
convert the last 3 targets to use EmitFunctionBody() now that
...
it has before/end body hooks.
lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp | 49 ++-----------
lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp | 87 ++++++------------------
lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp | 56 +++------------
test/CodeGen/XCore/ashr.ll | 2
4 files changed, 48 insertions(+), 146 deletions(-)
llvm-svn: 94741
2010-01-28 06:22:43 +00:00
fb4193625a
Delete useless trailing semicolons.
...
llvm-svn: 92740
2010-01-05 17:55:26 +00:00
3bd09434a6
Add XCore support for indirectbr / blockaddress.
...
llvm-svn: 89273
2009-11-18 23:20:42 +00:00
d5f2745965
Add XCore support for arbitrary-sized aggregate returns.
...
llvm-svn: 88802
2009-11-14 19:33:35 +00:00
4e13316bf9
Add some peepholes for signed comparisons using ashr X, X, 32.
...
llvm-svn: 83549
2009-10-08 15:38:17 +00:00
c8054d90fb
Eliminate more uses of llvm-as and llvm-dis.
...
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
2349fb4d45
Add support for mergeable sections back into the XCore backend.
...
llvm-svn: 79368
2009-08-18 21:14:31 +00:00
934d61648b
Put data with relocations in the same sections as data without relocations.
...
llvm-svn: 79351
2009-08-18 17:58:17 +00:00
94a2c1acae
Update getSectionForConstant() to to allow mergable sections to be nulled out
...
if not supported by the ELF subtarget.
llvm-svn: 79249
2009-08-17 16:37:11 +00:00
93980d68e4
use XCore-specific section with xcore specific cp/dp flags to restore
...
support for globals going into the appropriate sections with the flags.
This hopefully finishes unbreaking the previous behavior that I broke before.
llvm-svn: 79079
2009-08-15 06:09:35 +00:00
bbb772ace9
Add extra SEXT pattern.
...
llvm-svn: 77920
2009-08-02 22:45:24 +00:00
4d2c0f9008
switch off of 'Section' onto MCSection. We're not properly using
...
MCSection subclasses yet, but this is a step in the right direction.
llvm-svn: 77708
2009-07-31 18:48:30 +00:00
fc39e417a8
Add tests for handling of globals and tls on the XCore. These currently fail
...
but pass when run against r76652.
llvm-svn: 76923
2009-07-24 00:38:20 +00:00
0cceec520c
Combine an unaligned store of unaligned load into a memmove.
...
llvm-svn: 75908
2009-07-16 12:50:48 +00:00
bfdc557c8a
Expand unaligned 32 bit loads from an address which is a constant
...
offset from a 32 bit aligned base as follows:
ldw low, base[offset >> 2]
ldw high, base[(offset >> 2) + 1]
shr low_shifted, low, (offset & 0x3) * 8
shl high_shifted, high, 32 - (offset & 0x3) * 8
or result, low_shifted, high_shifted
Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.
llvm-svn: 75902
2009-07-16 10:42:35 +00:00
25b33cb035
Custom lower unaligned 32 bit stores and loads into libcalls. This is
...
a big code size win since before they were expanding to upto 16
instructions.
llvm-svn: 75901
2009-07-16 10:21:18 +00:00
a8edd048c2
Fix pattern for LD16S_3r, add basic tests to check load / store instructions
...
are being properly selected.
llvm-svn: 75797
2009-07-15 17:06:59 +00:00
57489b0658
Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs.
...
llvm-svn: 75788
2009-07-15 15:46:56 +00:00
a5b9645c4b
Split the Add, Sub, and Mul instruction opcodes into separate
...
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.
For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.
This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt
llvm-svn: 72897
2009-06-04 22:49:04 +00:00
9030c35eb4
Fix for PR4235: to build a floating-point value from integer parts,
...
build an integer and cast that to a float. This fixes a crash
caused by trying to split an f32 into two f16's.
This changes the behavior in test/CodeGen/XCore/fneg.ll because that
testcase now triggers a DAGCombine which converts the fneg into an integer
operation. If someone is interested, it's probably possible to tweak
the test to generate an actual fneg.
llvm-svn: 72162
2009-05-20 06:02:09 +00:00
1e7da23983
testcase for PR3898
...
llvm-svn: 69473
2009-04-18 20:49:22 +00:00
6de96a1b5d
Add the private linkage.
...
llvm-svn: 62279
2009-01-15 20:18:42 +00:00
40119780a8
Don't fold address calculations which use negative offsets into
...
the ADDRspii addressing mode.
llvm-svn: 62258
2009-01-15 11:32:30 +00:00
4359325ba8
Add pseudo instructions to the XCore for (load|store|load address) of a
...
frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.
This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.
llvm-svn: 62238
2009-01-14 18:26:46 +00:00
feece7edab
Add support for ISD::TRAP to the XCore backend
...
llvm-svn: 60479
2008-12-03 10:59:16 +00:00
1315f80ea8
Reapply r59464, this time using the correct type
...
when softening FNEG.
llvm-svn: 59513
2008-11-18 09:15:03 +00:00
e0d5e67c98
Revert r59464. It was causing this failure:
...
Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/dg.exp ...
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll
Failed with signal(SIGABRT) at line 1
while running: llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll | llc -march=xcore > fneg.ll.tmp1.s
Assertion failed: (VT.isFloatingPoint() && "Cannot create integer FP constant!"), function getConstantFP, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/SelectionDAG.cpp, line 913.
0 llc 0x0092115c _ZN4llvm3sys18RemoveFileOnSignalERKNS0_4PathEPSs + 844
1 libSystem.B.dylib 0x9217809b _sigtramp + 43
2 ??? 0xffffffff 0x0 + 4294967295
3 libSystem.B.dylib 0x921f0ec2 raise + 26
4 libSystem.B.dylib 0x9220047f abort + 73
5 libSystem.B.dylib 0x921f2063 __assert_rtn + 101
6 llc 0x005a5b0a _ZN4llvm12SelectionDAG13getConmake[1]: *** [check-local] Error 1
make: *** [check] Error 2
llvm-svn: 59487
2008-11-18 01:49:24 +00:00
f046b50ecd
Add soft float support for a bunch more operations. Original
...
patch by Richard Osborne, tweaked and extended by your humble
servant.
llvm-svn: 59464
2008-11-17 20:52:38 +00:00
6751b4a604
Don't produce ADDC/ADDE when expanding SHL unless they are legal
...
for the target. This fixes PR3080.
llvm-svn: 59450
2008-11-17 17:34:31 +00:00
5fe5933909
[XCore] Fix expansion of 64 bit add/sub. Don't custom expand
...
these operations if ladd/lsub are not available on the current
subtarget.
llvm-svn: 59305
2008-11-14 15:59:19 +00:00
d16b37efae
Add XCore intrinsics for getid (returns thread id) and bitrev (reverses
...
bits in a word).
llvm-svn: 59296
2008-11-14 10:12:16 +00:00
86d68a492a
Add basic test for XCore backend
...
llvm-svn: 58841
2008-11-07 11:24:12 +00:00
Richard Osborne