f152df1e6b
Rename LowerSubregs to ExpandPostRAPseudos.
...
I'll fix the file contents in the next commit.
This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I
am going to add a hook so targets can expand more pseudo-instructions
after register allocation.
Many targets have pseudo-instructions that assist the register
allocator. They can be expanded after register allocation, before PEI
and PostRA scheduling.
llvm-svn: 140469
2011-09-25 16:46:00 +00:00
f550fa9173
Sort CMakeLists.txt.
...
llvm-svn: 140465
2011-09-24 22:06:35 +00:00
c2deabd202
Implement Duncan's suggestion to use the result of getSetCCResultType if it is legal
...
(this is always the case for scalars), otherwise use the promoted result type.
Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled.
llvm-svn: 140464
2011-09-24 19:48:19 +00:00
77426a754b
[Vector-Select] Address one of the problems in 10902.
...
When generating the trunc-store of i1's, we need to use the vector type and not
the scalar type.
This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when
running with -promote-elements.
llvm-svn: 140463
2011-09-24 18:32:19 +00:00
7d7ee0c3ac
Add .td file.
...
llvm-svn: 140446
2011-09-24 01:40:18 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
...
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
55cf2ed148
Only run MF.verify() with EXPENSIVE_CHECKS=1.
...
llvm-svn: 140441
2011-09-24 01:11:19 +00:00
9b92e2be30
sys::Process: Add a SetWorkingDirectory method.
...
llvm-svn: 140433
2011-09-23 23:23:36 +00:00
8b2fe2f744
LSR minor bug fix in RateRegister.
...
No test case. Noticed by inspection and I doubt it ever affects the
outcome of the overall heuristic, let alone final codegen.
llvm-svn: 140431
2011-09-23 23:05:19 +00:00
3bb99bc957
Verify that terminators follow non-terminators.
...
This exposes a -segmented-stacks bug.
llvm-svn: 140429
2011-09-23 22:45:39 +00:00
8a15a5aa93
PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.
...
llvm-svn: 140428
2011-09-23 22:41:57 +00:00
4916840eb8
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
...
llvm-svn: 140426
2011-09-23 22:25:02 +00:00
2056d15bd9
Also match negative offsets for addrmode3 and addrmode5.
...
Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
llvm-svn: 140425
2011-09-23 22:10:33 +00:00
b0b865d658
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
...
llvm-svn: 140422
2011-09-23 21:57:50 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
...
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
ffa8428acf
Revert r140412. This affects more instructions than intended.
...
llvm-svn: 140413
2011-09-23 21:02:01 +00:00
7591d0c363
Thumb2 register-shifted-register loads cannot target the PC or the SP.
...
llvm-svn: 140412
2011-09-23 21:00:32 +00:00
d6af2c62b4
Implement N32/64 calling convention. Patch by Liu.
...
llvm-svn: 140401
2011-09-23 19:08:15 +00:00
ceb55e72de
Make FGR64RegisterClass available if target is Mips64.
...
llvm-svn: 140397
2011-09-23 18:28:39 +00:00
77709a6793
Add definitions of 64-bit register files. Add code for returning Mips64's sets of
...
callee-saved registers and reserved registers.
llvm-svn: 140395
2011-09-23 18:11:56 +00:00
71d32c980d
PTX: Fix parameter order bug
...
llvm-svn: 140394
2011-09-23 17:59:11 +00:00
24e45cabbc
Fix a couple of 80 column violations.
...
patch contributed by Jia Liu!
llvm-svn: 140391
2011-09-23 17:24:41 +00:00
6e84a68023
PTX: Cleanup unused code in PTXMachineFunctionInfo
...
llvm-svn: 140390
2011-09-23 17:15:53 +00:00
0f1af22183
PTX: Fix another 80-column violation
...
llvm-svn: 140387
2011-09-23 16:50:35 +00:00
37f35f0083
PTX: Handle function call return values
...
llvm-svn: 140386
2011-09-23 16:48:41 +00:00
ae191ef63b
Fix 80 column violations.
...
Original patch by Liu.
llvm-svn: 140385
2011-09-23 16:28:10 +00:00
a54fd541c2
Implement Chris's suggestion of legalizing the various SSE and AVX
...
hadd/hsub intrinsics into the new fhadd/fhsub X86 node.
llvm-svn: 140383
2011-09-23 16:10:22 +00:00
6c23d2ee55
PTX: Start fixing function calls
...
llvm-svn: 140378
2011-09-23 14:31:12 +00:00
edc6bf474d
PTX: Remove PTX calling convention files
...
llvm-svn: 140377
2011-09-23 14:18:27 +00:00
f2b540e815
[PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns
...
From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
lib/Target/PTX/PTXInstrInfo.td | 165 ++++++++++++++++++++----------
lib/Target/PTX/PTXIntrinsicInstrInfo.td | 88 +++++++++++------
2 files changed, 167 insertions(+), 86 deletions(-)
llvm-svn: 140376
2011-09-23 14:18:24 +00:00
b823e41bf4
PTX: Generalize handling of .param types
...
llvm-svn: 140375
2011-09-23 14:18:22 +00:00
2f82cc61af
PTX: Cleanup unused code in the PTXMFInfoExtract pass
...
llvm-svn: 140374
2011-09-23 14:18:19 +00:00
b461176cfb
Tweak the handling of MERGE_VALUES nodes: remove the need for
...
DecomposeMERGE_VALUES to "know" that results are legalized in
a particular order, by passing it the number of the result
being legalized (the type legalization core provides this, it
just needs to be passed on).
llvm-svn: 140373
2011-09-23 13:59:22 +00:00
57e30726ad
Vector-Select: Address one of the problems in pr10902. Add handling for the
...
integer-promotion of CONCAT_VECTORS.
Test: test/CodeGen/X86/widen_shuffle-1.ll
This patch fixes the above tests (when running in with -promote-elements).
llvm-svn: 140372
2011-09-23 09:33:24 +00:00
42fe6bd5f2
Add definitions of 64-bit int registers.
...
llvm-svn: 140366
2011-09-23 02:33:15 +00:00
61bbcce84a
Do not rely on the enum values of argument registers A0-A3 being consecutive.
...
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
llvm-svn: 140363
2011-09-23 00:58:33 +00:00
64a4bf1788
PR10989: Don't print .hidden on Windows.
...
llvm-svn: 140356
2011-09-23 00:13:02 +00:00
87c844cdf8
PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)
...
llvm-svn: 140355
2011-09-22 23:41:28 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
...
complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
adea3f0c01
Add new files to CMake.
...
llvm-svn: 140352
2011-09-22 23:20:48 +00:00
e83e1b2d2c
Fix SimplifySelectCC to add newly created nodes to the DAGCombiner
...
worklist, as it may be possible to perform further optimization on them.
llvm-svn: 140349
2011-09-22 23:01:29 +00:00
f05864ad7d
Add support for GR32 <-> FR32 cross class copies.
...
We already support GR64 <-> VR128 copies. All of these copies break
partial register dependencies by zeroing the high part of the target
register.
llvm-svn: 140348
2011-09-22 22:45:24 +00:00
fbf0fba9f4
Update CMake build.
...
llvm-svn: 140347
2011-09-22 22:38:34 +00:00
6cca67fc4a
Start stubbing out MCModule and MCAtom, which provide an API for accessing the rich disassembly of a complete object or executable.
...
These are very much a work in progress, and not really useful yet.
llvm-svn: 140345
2011-09-22 22:32:22 +00:00
e92e5ee81f
Constrain register classes instead of emitting copies.
...
Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.
Normally, these copies are handled by the coalescer. This saves some
coalescer work.
llvm-svn: 140340
2011-09-22 21:39:34 +00:00
0f36544c08
Add a MinNumRegs argument to MRI::constrainRegClass().
...
The function will refuse to use a register class with fewer registers
than MinNumRegs. This can be used by clients to avoid accidentally
increase register pressure too much.
The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.
llvm-svn: 140339
2011-09-22 21:39:31 +00:00
0e4fcb8e3b
Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
...
floating point add/sub of appropriate shuffle vectors. Does not
synthesize the 256 bit AVX versions because they work differently.
llvm-svn: 140332
2011-09-22 20:15:48 +00:00
f9b785f185
PR10987: add a missed safety check to isSafePHIToSpeculate in scalarrepl.
...
llvm-svn: 140327
2011-09-22 18:56:30 +00:00
56acf840f1
Print parentheses in next line.
...
llvm-svn: 140325
2011-09-22 18:29:29 +00:00
Jakob Stoklund Olesen