4 Commits

Author	SHA1	Message	Date
Matthias Braun	e40d89ef9b	ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 ... Re-apply r241926 with an additional check that r13 and r15 are not used for LDRD/STRD. See http://llvm.org/PR24190. This also already includes the fix from r241951. Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 242742	2015-07-21 00:18:59 +00:00
Matthias Braun	731e359e70	Revert "ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2" ... This reverts commit r241926. This caused http://llvm.org/PR24190 llvm-svn: 242735	2015-07-20 23:17:20 +00:00
Matthias Braun	e4ba6b8c24	ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 ... Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 241926	2015-07-10 18:28:49 +00:00
Tim Northover	8cda34f5e7	ARM: simplify and extend byval handling ... The main issue being fixed here is that APCS targets handling a "byval align N" parameter with N > 4 were miscounting what objects were where on the stack, leading to FrameLowering setting the frame pointer incorrectly and clobbering the stack. But byval handling had grown over many years, and had multiple layers of cruft trying to compensate for each other and calculate padding correctly. This only really needs to be done once, in the HandleByVal function. Elsewhere should just do what it's told by that call. I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits byvals with the correct C ABI alignment), which simplified HandleByVal. rdar://20095672 llvm-svn: 231959	2015-03-11 18:54:22 +00:00