Commit Graph

384818 Commits

Author SHA1 Message Date
oToToT 14a7296c01
[clang][clangd] Avoid inconsistent target creation
As proposed in D97109, I tried to make target creation consistent in `clang` and `clangd` by replacing the original procedure with a single function introduced in D97493.

This also helps `clangd` works with CUDA, OpenMP, etc.

Reviewed By: kadircet

Differential Revision: https://reviews.llvm.org/D98128
2021-04-06 23:23:34 +08:00
Erik Pilkington b660abc80d [ObjC] Add a command line flag that disables recognition of objc_direct for testability
Programmers would like to be able to test direct methods by calling them from a
different linkage unit or mocking them, both of which are impossible. This
patch adds a flag that effectively disables the attribute, which will fix this
when enabled in testable builds. rdar://71190891

Differential revision: https://reviews.llvm.org/D95845
2021-04-06 11:17:01 -04:00
Konstantin Zhuravlyov 844012940e AMDGPU: Add isBranch=1 to SOPP branch instructions
Differential Revision: https://reviews.llvm.org/D99955
2021-04-06 10:59:30 -04:00
Philip Reames 52ecd94cfb Remove last remnants of PR49607 migration [NFC]
The key change (4f5e92c) to switch gc.result and gc.relocate to being readnone landed nearly two weeks ago, and we haven't seen any fallout.  Time to remove the code added to make reverting easy.
2021-04-06 07:56:55 -07:00
Abhina Sreeskantharajan 23929af383 [Windows] Turn off text mode correctly in Rewriter to stop CRLF translation
I incorrectly changed the RewriteTestAction::ExecuteAction's file to binary instead of the proper RewriteIncludesAction::BeginSourceFileAction in https://reviews.llvm.org/rGbc5d4bcc2deb71ab647270c9754a83484b3d6f87. In the original commit, I actually changed RewriteIncludesAction::BeginSourceFileAction in https://reviews.llvm.org/rGfdb640ea30d416368b76b68b106deda580c6aced. This should fix the issue @aganea is facing.

Reviewed By: aganea

Differential Revision: https://reviews.llvm.org/D99837
2021-04-06 10:49:09 -04:00
Jan Svoboda fb6a5237aa Revert "[IR] Ignore bitcasts of function pointers which are only used as callees in callbase instruction"
This reverts commit 167ea67d

This causes a bunch of build failures:
* http://lab.llvm.org:8011/#/builders/121/builds/6287
* http://green.lab.llvm.org/green/job/clang-stage1-RA/19915
2021-04-06 16:33:28 +02:00
Benjamin Kramer ce4acb01b3 Avoid unused variable warning in Release builds 2021-04-06 16:25:19 +02:00
Jay Foad efc7bf27f5 [AMDGPU] SIFoldOperands: use MachineRegisterInfo::hasOneNonDBGUser
NFC.
2021-04-06 15:23:58 +01:00
Jay Foad 005dcd196e [AMDGPU] SIFoldOperands: use range-based loops and make_early_inc_range
NFC.
2021-04-06 15:23:58 +01:00
Jay Foad ce9cca6c3a [AMDGPU] SIFoldOperands: rename tryFoldInst to tryFoldCndMask
This follows the pattern of the other tryFold* functions. NFC.
2021-04-06 15:23:58 +01:00
Jay Foad cf4f5292f6 [AMDGPU] SIFoldOperands: use getVRegDef instead of getUniqueVRegDef
We are in SSA so getVRegDef is equivalent but simpler. NFC.
2021-04-06 15:23:58 +01:00
Simon Pilgrim ccb361af6c [llvm-symbolizer] Don't use the same 'OutputStyle' name for the enum type and instance. NFCI.
This was causing some buildbot problems, e.g. http://lab.llvm.org:8011/#/builders/110/builds/2306
2021-04-06 15:21:48 +01:00
Jay Foad e9608a84d8 [AMDGPU][SDag] Add IMG init also for image_gather4 instructions
This fixes an oversight in D99747 which moved the IMG init code from
SIAddIMGInit to AdjustInstrPostInstrSelection, but did not set the
hasPostISelHook flag on gather4 instructions.

Differential Revision: https://reviews.llvm.org/D99953
2021-04-06 14:47:20 +01:00
Kerry McLaughlin 7344f3d39a [LoopVectorize] Add strict in-order reduction support for fixed-width vectorization
Previously we could only vectorize FP reductions if fast math was enabled, as this allows us to
reorder FP operations. However, it may still be beneficial to vectorize the loop by moving
the reduction inside the vectorized loop and making sure that the scalar reduction value
be an input to the horizontal reduction, e.g:

  %phi = phi float [ 0.0, %entry ], [ %reduction, %vector_body ]
  %load = load <8 x float>
  %reduction = call float @llvm.vector.reduce.fadd.v8f32(float %phi, <8 x float> %load)

This patch adds a new flag (IsOrdered) to RecurrenceDescriptor and makes use of the changes added
by D75069 as much as possible, which already teaches the vectorizer about in-loop reductions.
For now in-order reduction support is off by default and controlled with the `-enable-strict-reductions` flag.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D98435
2021-04-06 14:45:34 +01:00
Simon Pilgrim 88c2454057 [InstCombine] Add PR38929 test case
Fold (~x & y) | ~(x | y) --> ~x
2021-04-06 14:42:30 +01:00
Simon Pilgrim 1dcb5b5e89 [X86] Improve optimizeCompareInstr for signed comparisons after ANDN instructions
Extend D94856 to handle 'andn' instructions as well
2021-04-06 14:16:16 +01:00
Roman Lebedev 849d372943
[NFC][Clang] Speculative fix for builtins-ppc-quadword-noi128.c 2021-04-06 16:15:23 +03:00
Roman Lebedev 31d219d299
[InstCombine] Fold `((X - Y) - Z)` to `X - (Y + Z)` (PR49858)
https://alive2.llvm.org/ce/z/67w-wQ

We prefer `add`s over `sub`, and this particular xform
allows further folds to happen:

Fixes https://bugs.llvm.org/show_bug.cgi?id=49858
2021-04-06 15:58:14 +03:00
Roman Lebedev 5ab489d9ae
[NFC][InstCombine] Add tests for '((X - Y) - Z)' pattern (PR49858) 2021-04-06 15:58:14 +03:00
Simon Pilgrim 5efe9efdad [X86] Add ANDN test case for PR48768
D94856 covered the BMI cases where we had existing tests, this adds a missing ANDN test case
2021-04-06 13:52:20 +01:00
Raphael Isemann bdfee7d5e1 [lldb][NFC] Fix misleading indentation in Cocoa.cpp 2021-04-06 14:30:47 +02:00
Jay Foad 0bf4836dc4 [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
Simon Pilgrim e07a9b38a6 [InstCombine] Add PR45984 test case
Fold (a ^ b) | ~(a | b) --> ~(a & b)
2021-04-06 13:05:29 +01:00
Alex Zinenko 7dc7790ec5 [mlir] Fix support for lowering non-32-bit affine reductions.
The existing implementation was always creating 32-bit constants for
floating-point and integer reductions regardless of the actual type, which
resulted in invalid IR being generated for any types other than f32 and i32
when lowering affine.parallel to SCF. Use the actual type instead.

Reviewed By: chelini

Differential Revision: https://reviews.llvm.org/D99942
2021-04-06 14:00:15 +02:00
Jay Foad 6fec0a34ce [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
Simon Pilgrim b8aba76a4e LoopFlatten - CanWidenIV - Fix uninitialized variable warnings and use for-range loop. NFCI.
Fix static analysis uninitialized variable warnings, and use for-range loop iteration across WideIVs array.
2021-04-06 12:24:20 +01:00
Simon Pilgrim 2901dc7575 Don't directly dereference getAs<> casts to avoid potential null dereferences. NFCI.
Replace with castAs<> which asserts the cast is valid.

Fixes a number of static analyzer warnings.
2021-04-06 12:24:19 +01:00
Abhina Sreeskantharajan 82b3e28e83 [SystemZ][z/OS][Windows] Add new OF_TextWithCRLF flag and use this flag instead of OF_Text
Problem:
On SystemZ we need to open text files in text mode. On Windows, files opened in text mode adds a CRLF '\r\n' which may not be desirable.

Solution:
This patch adds two new flags

  - OF_CRLF which indicates that CRLF translation is used.
  - OF_TextWithCRLF = OF_Text | OF_CRLF indicates that the file is text and uses CRLF translation.

Developers should now use either the OF_Text or OF_TextWithCRLF for text files and OF_None for binary files. If the developer doesn't want carriage returns on Windows, they should use OF_Text, if they do want carriage returns on Windows, they should use OF_TextWithCRLF.

So this is the behaviour per platform with my patch:

z/OS:
OF_None: open in binary mode
OF_Text : open in text mode
OF_TextWithCRLF: open in text mode

Windows:
OF_None: open file with no carriage return
OF_Text: open file with no carriage return
OF_TextWithCRLF: open file with carriage return

The Major change is in llvm/lib/Support/Windows/Path.inc to only set text mode if the OF_CRLF is set.
```
  if (Flags & OF_CRLF)
    CrtOpenFlags |= _O_TEXT;
```

These following files are the ones that still use OF_Text which I left unchanged. I modified all these except raw_ostream.cpp in recent patches so I know these were previously in Binary mode on Windows.
./llvm/lib/Support/raw_ostream.cpp
./llvm/lib/TableGen/Main.cpp
./llvm/tools/dsymutil/DwarfLinkerForBinary.cpp
./llvm/unittests/Support/Path.cpp
./clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
./clang/lib/Frontend/CompilerInstance.cpp
./clang/lib/Driver/Driver.cpp
./clang/lib/Driver/ToolChains/Clang.cpp

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D99426
2021-04-06 07:23:31 -04:00
Aaron Ballman 65c22acfa4 Silence -Woverloaded-virtual warnings from generated code; NFC 2021-04-06 07:19:07 -04:00
Kerry McLaughlin 857b8a73da [LoopVectorize] Change the identity element for FAdd
Changes getRecurrenceIdentity to always return a neutral value of -0.0 for FAdd.

Reviewed By: dmgreen, spatel

Differential Revision: https://reviews.llvm.org/D98963
2021-04-06 12:13:43 +01:00
Florian Hahn a6b06b785c [VPlan] Print VPValue operands for VPWidenPHI if possible.
For VPWidenPHIRecipes that model all incoming values as VPValue
operands, print those operands instead of printing the original PHI.

D99294 updates recipes of reduction PHIs to use the VPValue for the
incoming value from the loop backedge, making use of this new printing.
2021-04-06 12:11:21 +01:00
Dmitry Preobrazhensky 3eadcb86ab [AMDGPU][MC][GFX9] Corrected SMEM decoding
Corrected SMEM decoding when IMM=0 and OFFSET>127

Fixed bug 49819 (https://bugs.llvm.org/show_bug.cgi?id=49819)

Differential Revision: https://reviews.llvm.org/D99804
2021-04-06 14:10:46 +03:00
Dominik Montada b78e883fd8 [CMake] Fix Python 3 lookup when building LLVM with tests
Remove the find_package(Python3 ...) call from Tooling/CMakeLists.txt as
it would override the python 3 version determined in llvm/CMakeLists.txt.
This call did not respect the LLVM_MINIMUM_PYTHON_VERSION.

This fixes the check-all target when building LLVM on a system where the
default python version is not the minimum required version for running tests.

Reviewed By: serge-sans-paille

Differential Revision: https://reviews.llvm.org/D99715
2021-04-06 13:09:06 +02:00
Martin Storsjö 476e087939 [LLDB] Fix building for aarch64 windows after d6d3d21cd1
Differential Revision: https://reviews.llvm.org/D99847
2021-04-06 14:03:42 +03:00
Simon Pilgrim 201877d572 [CostModel][X86] Improve accuracy of vXi8 multiply reduction costs
After rG47321c311bdbe0145b9bf45d822185c37b19fa50 we promote vXi8 reductions to vXi16 to create a much faster PMULLW mul reduction, followed by a (free) truncation. This avoids the high cost of repeated vXi8 multiplications (which extend+multiply+truncate to/from vXi16 types....).

Fixes the missing vXi8 mul reduction vectorization in PR42674 (Comment #20) 'mul16' test case.
2021-04-06 11:53:22 +01:00
Jay Foad 6eb5b06ecf [AMDGPU] Regenerate checks to fix prefixes broken in D96340. NFC. 2021-04-06 11:43:53 +01:00
Alexander Belyaev f6ee97d827 [rt] Update DIPrinter usage in 'sanitizer_symbolize.cpp`.
These changes were required after
5f57793c4f

Differential Revision: https://reviews.llvm.org/D99937
2021-04-06 12:31:47 +02:00
David Spickett 34f8a7f93c [lsan][test] Disable many_tls_keys_pthread.cpp on AArch64
Partially reverts 04dbb63400.

This test requires 9be8f8b34d
which is/has been reverted a few times but this test was
left enabled.

Currently that change is reverted and this test is failing:
http://lab.llvm.org:8011/#/builders/7/builds/2327
2021-04-06 11:28:02 +01:00
Zakk Chen f2a3601aa5 [RISCV][Clang] Add all RVV Fixed-Point Arithmetic intrinsic functions.
Reviewed By: HsiangKai

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D99610
2021-04-06 03:12:45 -07:00
Zakk Chen fe252b509e [RISCV][Clang] Add more RVV Integer intrinsic functions.
Support below instructions.
1. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
2. Vector Integer Comparison Instructions
3. Vector Widening Integer Multiply-Add Instructions

Reviewed By: HsiangKai

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D99528
2021-04-06 03:11:28 -07:00
Zakk Chen f720c22e77 [RISCV][Clang] Add RVV Widening Integer Extension intrinsic functions.
Reviewed By: HsiangKai

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D99527
2021-04-06 03:10:14 -07:00
Zakk Chen 0a18ea01f1 [RISCV][Clang] Add RVV vnsra, vnsrl and vwmul intrinsic functions.
Reviewed By: craig.topper

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D99525
2021-04-06 03:07:36 -07:00
Zakk Chen 66c05609e0 [RISCV][Clang] Add some RVV Integer intrinsic functions.
1. Rename RVVBinBuiltin to RVVOutputOp1Builtin because it is not related
to the number of operand.
2. Add RVV Integer instuctions which use RVVOutputOp1Builtin.

Reviewed By: craig.topper

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D99524
2021-04-06 03:07:36 -07:00
David Spickett f8f4d8f87b [lldb] Improve CPUInfo test predicate
Use a with block for reading the cpuinfo file.

When loading the file fails (or we're not on Linux)
return an empty string. Since all the callers are
going to do "x in self.getCPUInfo()".

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D99729
2021-04-06 10:46:47 +01:00
Thomas Preud'homme 638d70be6b [test, AArch64] Fix use of var defined in CHECK-NOT
LLVM test CodeGen/AArch64/aarch64-tbz.ll tries to check for the absence
of a sequence of instructions with several CHECK-NOT with one of those
directives using a variable defined in another. However CHECK-NOT are
checked independently so that is using a variable defined in a pattern
that should not occur in the input.

This commit removes the definition and uses of variable to check each
line independently, making the check stronger than the current one. It
also removes unnecessary regex match for labels.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D99602
2021-04-06 10:45:08 +01:00
Simon Pilgrim 2fc761aac9 [PhaseOrdering] Add PR45687 test coverage
This is a mixture of instcombine/simplfycfg/instcombine to recognise and then remove the abs pattern
2021-04-06 10:31:42 +01:00
madhur13490 167ea67d76 [IR] Ignore bitcasts of function pointers which are only used as callees in callbase instruction
This patch enhances hasAddressTaken() to ignore bitcasts as a
callee in callbase instruction. Such bitcast usage doesn't really take
the address in a useful meaningful way.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D98884
2021-04-06 09:23:46 +00:00
Simon Pilgrim ddbb58736a [KnownBits] Rename KnownBits::computeForMul to KnownBits::mul. NFCI.
As promised in D98866
2021-04-06 10:11:41 +01:00
Balázs Kéri bee4813789 [clang][Checkers] Fix PthreadLockChecker state cleanup at dead symbol.
It is possible that an entry in 'DestroyRetVal' lives longer
than an entry in 'LockMap' if not removed at checkDeadSymbols.
The added test case demonstrates this.

Reviewed By: NoQ

Differential Revision: https://reviews.llvm.org/D98504
2021-04-06 11:15:29 +02:00
Sjoerd Meijer d5f1131c81 [AArch64] Default to zero-cycle-zeroing FP registers
It is generally beneficial to prefer "movi d0, #0" over "fmov s0, wzr" as this
is most efficient across all cores; it is recognised as a zeroing idiom. For
newer cores, fmov instructions can also be eliminated early and there is no
difference with movi, but some implementations lack this so is not true for
other/older cores. Thus this standardises on using movi as this should always
gives the same or better performance than the fmov with wzr.

Differential Revision: https://reviews.llvm.org/D99586
2021-04-06 09:47:50 +01:00