Commit Graph

21527 Commits

Author SHA1 Message Date
Bill Wendling fed6c220ec Revert "Resurrect r191017 " GVN proceeds in the presence of dead code" plus a fix to PR17307 & 17308."
This causes PR17852.

This reverts commit d93e8a06b2ca09ab18f390cd514b7443e2e571f7.

Conflicts:
	test/Transforms/GVN/cond_br2.ll

llvm-svn: 194348
2013-11-10 07:34:34 +00:00
Nadav Rotem 5ba1c6ced8 SimplifyCFG has a heuristics for out-of-order processors that decides when it is worthwhile to merge branches. It tries to estimate if the operands of the instruction that we want to hoist are ready. This commit marks function arguments as 'ready' because they require no calculation. This boosts libquantum and a few other workloads from the testsuite.
llvm-svn: 194346
2013-11-10 04:13:31 +00:00
Matt Arsenault ba035bce21 Resolve TODO in test now that filecheck has multiple check prefixes.
llvm-svn: 194344
2013-11-10 02:16:47 +00:00
Matt Arsenault 13df462691 Allow multiple check prefixes in FileCheck.
This is useful if you want to run multiple variations
of a single test, and the majority of check lines
should be the same.

llvm-svn: 194343
2013-11-10 02:04:09 +00:00
Matt Arsenault 5bcefabcda Teach MergeFunctions about address spaces
llvm-svn: 194342
2013-11-10 01:44:37 +00:00
Matt Arsenault 0fb71e545c Use variable for register name in test
llvm-svn: 194338
2013-11-10 00:57:17 +00:00
Reed Kotler 45c5927c5c Mostly finish up constant islands port for Mips for load constants.
Still need to finish the branch part. Still lots more review of the code,
clean up and testing. 

llvm-svn: 194337
2013-11-10 00:09:26 +00:00
Akira Hatanaka d1c58ed8a7 [mips] Make sure there is a chain edge dependency between loads that read
formal arguments on the stack and stores created afterwards. We need this to
ensure tail call optimized function calls do not write over the argument area
of the stack before it is read out.
 

llvm-svn: 194309
2013-11-09 02:38:51 +00:00
Juergen Ributzka 87ed906b2e [Stackmap] Materialize the jump address within the patchpoint noop slide.
This patch moves the jump address materialization inside the noop slide. This
enables patching of the materialization itself or its complete removal. This
patch also adds the ability to define scratch registers that can be used safely
by the code called from the patchpoint intrinsic. At least one scratch register
is required, because that one is used for the materialization of the jump
address. This patch depends on D2009.

Differential Revision: http://llvm-reviews.chandlerc.com/D2074

Reviewed by Andy

llvm-svn: 194306
2013-11-09 01:51:33 +00:00
Juergen Ributzka 9969d3e6e8 [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.
The idea of the AnyReg Calling Convention is to provide the call arguments in
registers, but not to force them to be placed in a paticular order into a
specified set of registers. Instead it is up tp the register allocator to assign
any register as it sees fit. The same applies to the return value (if
applicable).

Differential Revision: http://llvm-reviews.chandlerc.com/D2009

Reviewed by Andy

llvm-svn: 194293
2013-11-08 23:28:16 +00:00
Jim Grosbach 2fca51d3b4 X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()
On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.

rdar://15406518

llvm-svn: 194285
2013-11-08 22:33:06 +00:00
Quentin Colombet b06a0ed4b0 [VirtRegMap] Fix for PR17825. Do not ignore noreturn definitions when setting
isPhysRegUsed if the unwind information is required.
Indeed, the runtime may need a correct stack to be able to unwind the call.

llvm-svn: 194271
2013-11-08 18:14:17 +00:00
Tim Northover 93bcc66e73 ARM: fold prologue/epilogue sp updates into push/pop for code size
ARM prologues usually look like:
    push {r7, lr}
    sub sp, sp, #4

If code size is extremely important, this can be optimised to the single
instruction:
    push {r6, r7, lr}

where we don't actually care about the contents of r6, but pushing it subtracts
4 from sp as a side effect.

This should implement such a conversion, predicated on the "minsize" function
attribute (-Oz) since I've yet to find any code it actually makes faster.

llvm-svn: 194264
2013-11-08 17:18:07 +00:00
Artyom Skrobov 202ff08f97 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
llvm-svn: 194263
2013-11-08 16:25:50 +00:00
Artyom Skrobov d2116a4ef7 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
llvm-svn: 194262
2013-11-08 16:17:14 +00:00
Artyom Skrobov e686cec7d4 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
llvm-svn: 194261
2013-11-08 16:16:30 +00:00
Zoran Jovanovic 2914d2d980 Test for microMIPS trap instructions.
llvm-svn: 194258
2013-11-08 14:55:31 +00:00
NAKAMURA Takumi 0d82bac470 llvm-ar: Let opening a directory failed in llvm-ar.
Linux cannot open directories with open(2), although cygwin and *bsd can.

Motivation: The test, Object/directory.ll, had been failing with --target=cygwin on Linux. XFAIL was improper for host issues.
llvm-svn: 194257
2013-11-08 12:35:56 +00:00
Matheus Almeida a3bac16950 [mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.

llvm-svn: 194255
2013-11-08 10:43:11 +00:00
Artyom Skrobov 8653443902 [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
llvm-svn: 194253
2013-11-08 09:16:31 +00:00
David Majnemer bd4fef4a89 IR: Do not canonicalize constant GEPs into an out-of-bounds array access
Summary:
Consider a GEP of:
i8* getelementptr ({ [2 x i8], i32, i8, [3 x i8] }* @main.c, i32 0, i32 0, i64 0)

If we proceeded to GEP the aforementioned object by 8, would form a GEP of:
i8* getelementptr ({ [2 x i8], i32, i8, [3 x i8] }* @main.c, i32 0, i32 0, i64 8)

Note that we would go through the first array member, causing an
out-of-bounds accesses.  This is problematic because we might get fooled
if we are trying to evaluate loads using this GEP, for example, based
off of an object with a constant initializer where the array is zero.

This fixes PR17732.

Reviewers: nicholas, chandlerc, void

Reviewed By: void

CC: llvm-commits, echristo, void, aemerson

Differential Revision: http://llvm-reviews.chandlerc.com/D2093

llvm-svn: 194220
2013-11-07 22:15:53 +00:00
Zoran Jovanovic c18b6d1083 Support for microMIPS trap instructions 1.
llvm-svn: 194205
2013-11-07 14:35:24 +00:00
Vincent Lejeune 4f3751f2af R600: Fix LowerUDIVREM
llvm-svn: 194153
2013-11-06 17:36:04 +00:00
Benjamin Kramer 9e9773d46d Add test case for PR12377, it was fixed by r194116.
llvm-svn: 194147
2013-11-06 11:55:41 +00:00
Vladimir Medic 4c29985cd0 Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
llvm-svn: 194145
2013-11-06 11:27:05 +00:00
Peter Zotov 578267fb73 [OCaml] Impement Llvm_irreader, bindings to LLVM assembly parser
llvm-svn: 194138
2013-11-06 09:21:25 +00:00
Peter Zotov d10ae6c527 [OCaml] Implement Llvm.string_of_llvalue
llvm-svn: 194136
2013-11-06 09:21:08 +00:00
Jiangning Liu f4226f1d7b Implement AArch64 Neon instruction set Perm.
llvm-svn: 194123
2013-11-06 03:35:27 +00:00
Jiangning Liu a50e22ca4f Implement AArch64 Neon instruction set Bitwise Extract.
llvm-svn: 194118
2013-11-06 02:25:49 +00:00
Andrew Trick 34e2f0c4ea Rewrite SCEV's backedge taken count computation.
Patch by Michele Scandale!

Rewrite of the functions used to compute the backedge taken count of a
loop on LT and GT comparisons.

I decided to split the handling of LT and GT cases becasue the trick
"a > b == -a < -b" in some cases prevents the trip count computation
due to the multiplication by -1 on the two operands of the
comparison. This issue comes from the conservative computation of
value range of SCEVs: taking the negative SCEV of an expression that
have a small positive range (e.g. [0,31]), we would have a SCEV with a
fullset as value range.

Indeed, in the new rewritten function I tried to better handle the
maximum backedge taken count computation when MAX/MIN expression are
used to handle the cases where no entry guard is found.

Some test have been modified in order to check the new value correctly
(I manually check them and reasoning on possible overflow the new
values seem correct).

I finally added a new test case related to the multiplication by -1
issue on GT comparisons.

llvm-svn: 194116
2013-11-06 02:08:26 +00:00
Andrew Trick 6664df12fb Slightly change the way stackmap and patchpoint intrinsics are lowered.
MorphNodeTo is not safe to call during DAG building. It eagerly
deletes dependent DAG nodes which invalidates the NodeMap. We could
expose a safe interface for morphing nodes, but I don't think it's
worth it. Just create a new MachineNode and replaceAllUsesWith.

My understaning of the SD design has been that we want to support
early target opcode selection. That isn't very well supported, but
generally works. It seems reasonable to rely on this feature even if
it isn't widely used.

llvm-svn: 194102
2013-11-05 22:44:04 +00:00
Tim Northover f02287db27 ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

llvm-svn: 194094
2013-11-05 21:36:02 +00:00
Jiangning Liu d7c52676f6 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
llvm-svn: 194085
2013-11-05 17:42:05 +00:00
Michael Gottesman 24b2f6fdda [objc-arc] Convert the one directional retain/release relation assert to a conditional check + fail.
Due to the previously added overflow checks, we can have a retain/release
relation that is one directional. This occurs specifically when we run into an
additive overflow causing us to drop state in only one direction. If that
occurs, we should bail and not optimize that retain/release instead of
asserting.

Apologies for the size of the testcase. It is necessary to cause the additive
cfg overflow to trigger.

rdar://15377890

llvm-svn: 194083
2013-11-05 16:02:40 +00:00
Alp Toker a2f1b8d238 Provide a test input for opt
This was only working previously due to a quirk in the way lit
concatenates script commands.

llvm-svn: 194078
2013-11-05 13:57:34 +00:00
Peter Zotov 28f6876ecc [OCaml] (PR16318) Add missing argument to Llvm.const_intcast
llvm-svn: 194065
2013-11-05 11:56:20 +00:00
Peter Zotov ce7a91b277 [OCaml] (PR11717) Make declare_qualified_global respect address argument
Original patch by Jonathan Ragan-Kelley

llvm-svn: 194064
2013-11-05 11:56:13 +00:00
Reed Kotler 0f007fc4ce Fix r194019 as requested by Eric Christopher.
Submit the basic port of the rest of ARM constant islands code to Mips. 
Two test cases are added which reflect the next level of functionality:
constants getting moved to water areas that are out of range from the
initial placement at the end of the function and basic blocks being split to
create water when none exists that can be used. There is a bunch of this
code that is not complete and has been marked with IN_PROGRESS. I will
finish cleaning this all up during the next week or two and submit the
rest of the test cases. I have elminated some code for dealing with
inline assembly because to me it unecessarily complicates things and
some of the newer features of llvm like function attributies and builtin
assembler give me better tools to solve the alignment issues created
there. Also, for Mips16 I even have the option of not doing constant
islands in the present of inline assembler if I chose. When everything
has been completed I will summarize the port and notify people that
are knowledgable regarding the ARM Constant Islands code so they can
review it in it's entirety if they wish.

llvm-svn: 194053
2013-11-05 08:14:14 +00:00
Hao Liu d6b40b51c7 Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043
2013-11-05 03:39:32 +00:00
Kevin Qin 97f6aaa8ad Implemented aarch64 neon intrinsic vcopy_lane with float type.
llvm-svn: 194041
2013-11-05 02:03:59 +00:00
Yuchen Wu f3e653e9a6 Revert "Added basic unit test for llvm-cov."
This reverts commit 9cacd131c22b888303cb88e9a3235b2d7b2f19a1.

llvm-svn: 194039
2013-11-05 01:56:26 +00:00
Yuchen Wu 0b8e9a1480 Added basic unit test for llvm-cov.
This test compares the output of llvm-cov against a coverage file
generated by gcov.

llvm-svn: 194038
2013-11-05 01:56:23 +00:00
NAKAMURA Takumi 5267613e3a Revert r194019 to r194021, "Submit the basic port of the rest of ARM constant islands code to Mips."
It broke -Asserts build.

llvm-svn: 194026
2013-11-04 23:14:36 +00:00
Tim Northover ace0bd4d33 AArch64: use default asm operand printing when modifier inapplicable
If an inline assembly operand has multiple constraints (e.g. "Ir" for immediate
or register) and an operand modifier (E.g. "w" for "print register as wN") then
we need to decide behaviour when the modifier doesn't apply to the constraint.

Previousely produced some combination of an assertion failure and a fatal
error. GCC's behaviour appears to be to ignore the modifier and print the
operand in the default way. This patch should implement that.

llvm-svn: 194024
2013-11-04 23:04:07 +00:00
Reed Kotler 3fe68871da Add the test case that goes with the previous submission for constant
islands. I forgot to add it to svn on that patch. Ooops.

llvm-svn: 194020
2013-11-04 22:13:41 +00:00
Eric Christopher 542c8d934d Check for both styles of clobbers, those produced by dragonegg and
those produced by clang for the inline asm bswap conversion.

Modified from a patch by Chris Smowton.

llvm-svn: 194016
2013-11-04 21:41:21 +00:00
Matt Arsenault a8e894405c Fix another constant folding address space place I missed.
This fixes an assertion failure with a different sized address space.

llvm-svn: 194014
2013-11-04 20:46:52 +00:00
Matt Arsenault 243140f2fd Scalarize select vector arguments when extracted.
When the elements are extracted from a select on vectors
or a vector select, do the select on the extracted scalars
from the input if there is only one use.

llvm-svn: 194013
2013-11-04 20:36:06 +00:00
Cameron McInally d80f7d34de Add support for AVX512 masked vector blend intrinsics.
llvm-svn: 194006
2013-11-04 19:14:56 +00:00
Manman Ren 289ef7d992 Rename testing case to use - instead of _.
llvm-svn: 194001
2013-11-04 18:52:06 +00:00