1432ef864e
This void is implicit in C++.
...
llvm-svn: 78848
2009-08-12 22:10:57 +00:00
1f8c7a76f7
Fix counting of Post-RA scheduling stalls. Improve debug output.
...
llvm-svn: 78843
2009-08-12 21:47:46 +00:00
b4c6965da3
Added RegisterCoalescer to required passes for PBQP.
...
llvm-svn: 78840
2009-08-12 21:04:53 +00:00
1c0e13fe66
Use WriteAsOperand to print BasicBlock names.
...
llvm-svn: 78838
2009-08-12 20:56:56 +00:00
12dad639b5
Make AsmWriter more careful with formatted_raw_ostream so that
...
it doesn't leave the underlying stream in unbuffered mode when
the stream was originally buffered.
Also, change WriteAsOperand back to plain raw_ostream. This
lets it work for either formatted_raw_ostream or plain
raw_ostream, so that it doesn't have to force a buffer flush
on a plain raw_ostream.
llvm-svn: 78837
2009-08-12 20:56:03 +00:00
4b35448360
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
...
llvm-svn: 78835
2009-08-12 20:51:55 +00:00
d95c962d52
Use PadToColumn instead of tabs.
...
llvm-svn: 78834
2009-08-12 18:55:32 +00:00
aceb935add
Fix a few more places to use PadToColumn instead of tabs. And fix
...
the basic block label printing to check whether a block has a name
before printing a comment character and whitespace for it.
llvm-svn: 78830
2009-08-12 18:47:05 +00:00
aee7e49c50
PredCC is meant to be 2 bits wide, like PredCC1.
...
llvm-svn: 78829
2009-08-12 18:35:50 +00:00
942d2857ef
Use PadToColumn instead of tabs for aligning comments. Fix one place
...
that emitted unnecessary whitespace outside of VerboseAsm mode.
llvm-svn: 78828
2009-08-12 18:32:22 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
54be785be7
Add attempted idiotproofing comment per review.
...
llvm-svn: 78825
2009-08-12 18:04:11 +00:00
c02f3d866f
improve win32 path support, patch by Baptiste Lepilleur!
...
llvm-svn: 78823
2009-08-12 17:47:06 +00:00
34c08bbbf9
Fix a nondeterministic bug in APInt::roundToDouble;
...
when !isSingleWord() but getActiveBits() is small,
we were using the pointer value instead of the low
word of the integer value.
llvm-svn: 78821
2009-08-12 17:42:34 +00:00
3cfc6463c9
Add catch block handling to SjLj exception handling.
...
llvm-svn: 78817
2009-08-12 17:38:44 +00:00
e274526d78
Make LLVM Assembly dramatically easier to read by aligning the comments,
...
using formatted_raw_ostream's PadToColumn.
Before:
bb1: ; preds = %bb
%2 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
%3 = getelementptr double* %p, i64 %2 ; <double*> [#uses=1]
%4 = load double* %3, align 8 ; <double> [#uses=1]
%5 = fmul double %4, 1.100000e+00 ; <double> [#uses=1]
%6 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
%7 = getelementptr double* %p, i64 %6 ; <double*> [#uses=1]
After:
bb1: ; preds = %bb
%2 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
%3 = getelementptr double* %p, i64 %2 ; <double*> [#uses=1]
%4 = load double* %3, align 8 ; <double> [#uses=1]
%5 = fmul double %4, 1.100000e+00 ; <double> [#uses=1]
%6 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
%7 = getelementptr double* %p, i64 %6 ; <double*> [#uses=1]
Several tests required whitespace adjustments.
llvm-svn: 78816
2009-08-12 17:23:50 +00:00
25cae66713
Fix TableGen warnings. This partly reverts my previous change to this file,
...
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
llvm-svn: 78815
2009-08-12 17:04:56 +00:00
09b311f42f
Fix a missing newline (now that Value*'s operator<< doesn't append one).
...
llvm-svn: 78814
2009-08-12 16:48:27 +00:00
957d0587b6
change CBE to just get TAI now, instead of TM to get TAI.
...
llvm-svn: 78813
2009-08-12 16:41:44 +00:00
4ac2f639cd
Transform -X/C to X/-C, implementing a README.txt entry.
...
llvm-svn: 78812
2009-08-12 16:37:02 +00:00
908da3d97e
Optimize (x/C)*C to x if the division is exact.
...
llvm-svn: 78811
2009-08-12 16:33:09 +00:00
43103abef0
Update instcombine's debug output to account for Value*'s operator<<
...
not appending its own newline.
llvm-svn: 78810
2009-08-12 16:28:31 +00:00
5476cfdb15
Remove a bunch more now-unnecessary Context arguments.
...
llvm-svn: 78809
2009-08-12 16:23:25 +00:00
6b490ce4c7
Eliminate a bunch of now unnecessary explicit Context variables.
...
llvm-svn: 78808
2009-08-12 16:04:34 +00:00
bcbae01797
CMake: Added asm file to x86_64 MSVC build.
...
llvm-svn: 78807
2009-08-12 15:54:28 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
9a6cf91261
Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple
...
pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
llvm-svn: 78802
2009-08-12 07:22:17 +00:00
8268cc9c77
the x86 version of the name is x86-64, not x86_64. Handle this properly
...
in getArchTypeForLLVMName.
llvm-svn: 78799
2009-08-12 06:45:02 +00:00
e0971bc29f
add support for mingw64 target triples.
...
llvm-svn: 78797
2009-08-12 06:32:10 +00:00
ee01029811
Move immediate constant predicate templates from the Blackfin target to MathExtras.h
...
llvm-svn: 78793
2009-08-12 06:22:07 +00:00
553c9f35a7
add a couple of helpers to the Triple class for decoding
...
the darwin version string. This should help consolidate
the variety of weird functions we have scattered around the
codebase that do stuff like this.
llvm-svn: 78792
2009-08-12 06:19:40 +00:00
bb2af3555c
Shrink Thumb2 movcc instructions.
...
llvm-svn: 78790
2009-08-12 05:17:19 +00:00
81348021b1
Remove another Darwin assembler workaround.
...
llvm-svn: 78779
2009-08-12 02:07:19 +00:00
fd10869d4b
80 col violation.
...
llvm-svn: 78778
2009-08-12 02:03:03 +00:00
608d92c943
Remove an Darwin assembler workaround.
...
llvm-svn: 78777
2009-08-12 01:56:42 +00:00
1e6c2a1c17
Shrink ADDS, ADC, RSB, and SUBS.
...
llvm-svn: 78776
2009-08-12 01:49:45 +00:00
2a767c0d26
This logic was accidentally inverted in r78767.
...
llvm-svn: 78773
2009-08-12 01:44:20 +00:00
f7912edba5
Factor out the code for finding an available register for use
...
in breaking an anti-dependence into a separate function.
llvm-svn: 78767
2009-08-12 01:33:27 +00:00
f042eadd1e
Add missing chain operands for VLD* and VST* instructions.
...
Set "mayLoad" and "mayStore" on the load/store instructions.
llvm-svn: 78761
2009-08-12 00:49:01 +00:00
117c9e8497
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first.
...
llvm-svn: 78759
2009-08-12 00:36:31 +00:00
76733748e1
Simplify this code, and use an in-bounds GEP.
...
llvm-svn: 78755
2009-08-12 00:32:55 +00:00
2b083cf989
prune #include
...
llvm-svn: 78749
2009-08-11 23:07:27 +00:00
b9c1d6c86e
prune #includage.
...
llvm-svn: 78748
2009-08-11 23:06:16 +00:00
96db1abb77
fix CodeGen/PowerPC/2007-01-15-AsmDialect.ll, fallout from r78742
...
llvm-svn: 78747
2009-08-11 23:03:40 +00:00
1e9097e36a
change the -x86-asm-syntax=intel/att flag to be in X86TAI
...
instead of X86 Subtarget. This elimianates dependencies on
X86Subtarget from X86TAI.
llvm-svn: 78746
2009-08-11 23:01:09 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
...
llvm-svn: 78745
2009-08-11 23:00:31 +00:00
97868fe1b9
second half of commit.
...
llvm-svn: 78744
2009-08-11 22:52:15 +00:00
63d5be8a7b
pass "is64Bit" flag into PPC TAI ctors instead of a whole targetmachine.
...
llvm-svn: 78743
2009-08-11 22:51:34 +00:00
e655521a28
eliminate asmflavor from subtarget, PPCTAI is the only client
...
and each callee knows that it returns.
llvm-svn: 78742
2009-08-11 22:49:34 +00:00
abdcbc7ef2
Change the asmprinter to print the comment character before the
...
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character. This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character. This also allows hoisting the darwin stuff up to the
shared TAI class.
llvm-svn: 78737
2009-08-11 22:39:40 +00:00
fd5defed1d
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
...
llvm-svn: 78736
2009-08-11 22:38:43 +00:00
54075a78b4
factorize more darwin TAI stuff. Note that this gives
...
darwin/arm support for .no_dead_strip
llvm-svn: 78734
2009-08-11 22:31:42 +00:00
526bcd461a
X86/AsmParser: Mark MOV64GSrm, MOV64FSrm, GS_MOV32rm, FS_MOV32rm as codegen only.
...
llvm-svn: 78733
2009-08-11 22:24:40 +00:00
6747b39ca5
factorize darwin ProtectedDirective and SetDirective.
...
llvm-svn: 78732
2009-08-11 22:22:44 +00:00
c4f8ea4ccb
Add 'isCodeGenOnly' bit to Instruction .td records.
...
- Used to mark fake instructions which don't correspond to an actual machine
instruction (or are duplicates of a real instruction). This is to be used for
"special cases" in the .td files, which should be ignored by things like the
assembler and disassembler. We still need a good solution to handle pervasive
duplication, like with the Int_ instructions.
- Set the bit on fake "mov 0" style instructions, which allows turning an
assembler matcher warning into a hard error.
- -2 FIXMEs.
llvm-svn: 78731
2009-08-11 22:17:52 +00:00
d832c8e87c
all darwin targets have .space and .zerofill, pull up.
...
llvm-svn: 78730
2009-08-11 22:17:31 +00:00
f710f71839
eliminate template from arm TAI
...
llvm-svn: 78729
2009-08-11 22:14:59 +00:00
374d5770f0
fix a bug I introduced in r78724 that caused failures in:
...
CodeGen/X86/dll-linkage.ll & CodeGen/X86/mingw-alloca.ll
llvm-svn: 78728
2009-08-11 22:12:58 +00:00
7faf1fd9a0
move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate
...
template in PPC backend for TAI.
llvm-svn: 78727
2009-08-11 22:06:07 +00:00
c6daf8f17c
Fix warnings.
...
llvm-svn: 78725
2009-08-11 21:59:30 +00:00
0909918514
eliminate the X86TargetAsmInfo template.
...
llvm-svn: 78724
2009-08-11 21:57:08 +00:00
f0e62eb78f
Added ADD instructions with rAX as one parameter to the Intel instruction
...
tables.
llvm-svn: 78721
2009-08-11 21:26:06 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
...
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
e431871851
llvm-mc/AsmParser: Allow target to specific a comment delimiter, which will be
...
used to strip hard coded comments out of .td assembly strings.
llvm-svn: 78716
2009-08-11 20:59:47 +00:00
dbae4db67a
Optimize exact sdiv by a constant power of 2 to ashr.
...
llvm-svn: 78714
2009-08-11 20:47:47 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
2c30970b22
pass the TargetTriple down from each target ctor to the
...
LLVMTargetMachine ctor. It is currently unused.
llvm-svn: 78711
2009-08-11 20:42:37 +00:00
67e5ea2726
now that JumpTableDirective can differentate picness itself, MIPS TAI
...
no longer needs a targetmachine to initialize itself.
llvm-svn: 78710
2009-08-11 20:32:51 +00:00
fe27130454
split "JumpTableDirective" (an existing hack) into a PIC and nonPIC
...
version. This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.
The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.
llvm-svn: 78709
2009-08-11 20:30:58 +00:00
d5a9179685
"TAI::JumpTableDirective" is always null for current arm targets, simplify
...
the code based on this and make it fall through better.
llvm-svn: 78708
2009-08-11 20:29:57 +00:00
77ad32ab0e
Add convenience functions for creating nsw add operators.
...
llvm-svn: 78707
2009-08-11 20:20:39 +00:00
221a2c711d
Don't set the isexact flag if an sdiv operator has been folded into
...
something else.
llvm-svn: 78702
2009-08-11 19:56:00 +00:00
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
...
llvm-svn: 78701
2009-08-11 19:42:21 +00:00
919fe2bd2f
Simplify ConstantExpr::getInBoundsGetElementPtr and fix a possible crash, if
...
constant folding eliminated the GEP instruction.
- clang was hitting this on its test suite (for x86_64, at least).
llvm-svn: 78698
2009-08-11 18:28:09 +00:00
270968279b
Revert 78680 until I figure out why it completely broke things.
...
llvm-svn: 78697
2009-08-11 18:11:15 +00:00
5c310be0ff
Link NamedMDNodes.
...
llvm-svn: 78696
2009-08-11 18:01:24 +00:00
50c09d0ca3
Add convenience functions for creating inbounds GEPs.
...
llvm-svn: 78695
2009-08-11 17:57:01 +00:00
92492f2f8e
Use DEBUG macro for debug output.
...
llvm-svn: 78694
2009-08-11 17:56:42 +00:00
5d47e93532
add a trivial line # cache to SourceMgr to make repeated queries to
...
FindLineNumber much faster when in sequence.
llvm-svn: 78693
2009-08-11 17:49:14 +00:00
78c3bcb582
Make LLVMContext and LLVMContextImpl classes instead of structs.
...
llvm-svn: 78690
2009-08-11 17:45:13 +00:00
5c13812e2f
Remove some unnecessary LoadInst constructors, missed during Twinification.
...
llvm-svn: 78689
2009-08-11 17:38:47 +00:00
ebd694bb0a
Add some debug output.
...
llvm-svn: 78687
2009-08-11 17:35:23 +00:00
4bdbad7ebf
Use isa instead of dyn_cast when the result is only converted to bool.
...
llvm-svn: 78685
2009-08-11 17:20:16 +00:00
1d5350c08f
fix GetInstSizeInBytes for eh_sjlj_setjmp
...
llvm-svn: 78683
2009-08-11 17:08:15 +00:00
58f4d89a10
Add convenience functions for creating exact sdiv operators, and
...
use them in CreatePtrDiff.
llvm-svn: 78682
2009-08-11 17:05:24 +00:00
ab2460c066
move some 32-bit instrs to x86instrinfo.td
...
llvm-svn: 78680
2009-08-11 16:58:39 +00:00
eda08015ee
This void is implicit in C++.
...
llvm-svn: 78678
2009-08-11 16:03:08 +00:00
7c50c9bd63
Tidy #includes.
...
llvm-svn: 78677
2009-08-11 16:02:12 +00:00
aa3fb65349
Simplify this code. The case where one class is GR64RegClass and the
...
other is a subclass of it is effectively handled by the prior tests.
llvm-svn: 78676
2009-08-11 15:59:48 +00:00
5211b0128b
Fix a typo in an assertion string.
...
llvm-svn: 78671
2009-08-11 15:53:15 +00:00
a72f856aa4
Don't assume that external global variables are aligned at their preferred
...
alignment. Only the minimum alignment guaranteed by the ABI may be assumed.
llvm-svn: 78668
2009-08-11 15:50:03 +00:00
c7c2bc9663
Remove unnecessary throw() specifications; LLVM doesn't use exceptions.
...
llvm-svn: 78667
2009-08-11 15:35:57 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
...
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
74eb9e7bfd
Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header.
...
llvm-svn: 78665
2009-08-11 15:26:27 +00:00
38484ceec9
Remove unnecessary casts.
...
llvm-svn: 78664
2009-08-11 15:15:10 +00:00
e02f9ba9b1
Add const qualifiers.
...
llvm-svn: 78663
2009-08-11 15:13:43 +00:00
806845daec
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
...
llvm-svn: 78659
2009-08-11 09:37:40 +00:00
3606467709
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
...
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
llvm-svn: 78658
2009-08-11 08:52:18 +00:00
d4d352c663
80 column violation.
...
llvm-svn: 78657
2009-08-11 08:47:46 +00:00
70ede4843c
Change llvm-c's ordering of contexts to make it consistent.
...
llvm-svn: 78656
2009-08-11 07:46:16 +00:00
192d7c0752
Cosmetic changes.
...
llvm-svn: 78655
2009-08-11 07:36:14 +00:00
6e62e93a8d
Adding a blank line back.
...
llvm-svn: 78654
2009-08-11 07:32:58 +00:00
4d4a2e09a9
Link metadata.
...
llvm-svn: 78652
2009-08-11 06:46:31 +00:00
c5aa8c6d29
Remove dead metadata.
...
llvm-svn: 78651
2009-08-11 06:31:57 +00:00
b39a5aa794
Rebuild RegScavenger::DistanceMap each time it is needed.
...
The register scavenger maintains a DistanceMap that maps MI pointers to their
distance from the top of the current MBB. The DistanceMap is built
incrementally in forward() and in bulk in findFirstUse(). It is used by
scavengeRegister() to determine which candidate register has the longest
unused interval.
Unfortunately the DistanceMap contents can become outdated. The first time
scavengeRegister() is called, the DistanceMap is filled to cover the MBB. If
then instructions are inserted in the MBB (as they always are following
scavengeRegister()), the recorded distances are too short. This causes bad
behaviour in the included test case where a register use /after/ the current
position is ignored because findFirstUse() thinks is is /before/ the current
position. A "using an undefined register" assertion follows promptly.
The fix is to build a fresh DistanceMap at the top of scavengeRegister(), and
discard it after use. This means that DistanceMap is no longer needed as a
RegScavenger member variable, and forward() doesn't need to update it.
The fix then discloses issue number two in the same test case: The candidate
search in scavengeRegister() finds a CSR that has been saved in the prologue,
but is currently unused. It would be both inefficient and wrong to spill such
a register in the emergency spill slot. In the present case, the emergency
slot restore is placed immediately before the normal epilogue restore, leading
to a "Redefining a live register" assertion.
Fix number two: When scavengerRegister() stumbles upon an unused register that
is overwritten later in the MBB, return that register early. It is important
to verify that the register is defined later in the MBB, otherwise it might be
an unspilled CSR.
llvm-svn: 78650
2009-08-11 06:25:12 +00:00
0c04f2b454
Fix a -Asserts warning.
...
- Since the function is never called in NDEBUG mode, just dropped the DEBUG()
uses here.
llvm-svn: 78649
2009-08-11 06:22:47 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
...
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
71527c1493
llvm-mc/X86: Parse '*' correctly (in the way the matcher expects).
...
llvm-svn: 78642
2009-08-11 05:00:25 +00:00
dd4103b55b
Fixed more problems caused by 78142.
...
Passing of indirect arguments starts after return value on the callee's frame.
llvm-svn: 78635
2009-08-11 01:51:55 +00:00
f20236ac83
Replace DOUT.
...
llvm-svn: 78634
2009-08-11 01:44:26 +00:00
741a9c7bf6
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
...
llvm-svn: 78632
2009-08-11 01:15:26 +00:00
2cd5da8300
Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsic
...
arguments that are vectors of any size and element type.
llvm-svn: 78631
2009-08-11 01:14:02 +00:00
5cfb60ffc7
Added the x86 INT instructions; both the special-case INT 3 and the general-case
...
INT i8. These instructions are only for interpretation by disassemblers, not
for emission, so they do not as yet have patterns.
llvm-svn: 78630
2009-08-11 01:09:06 +00:00
b80734bb15
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
...
llvm-svn: 78629
2009-08-11 01:07:38 +00:00
9382d5ac05
Add stdlib.h
...
llvm-svn: 78627
2009-08-11 00:20:00 +00:00
693e36a3e8
SjLj based exception handling unwinding support. This patch is nasty, brutish
...
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
llvm-svn: 78625
2009-08-11 00:09:57 +00:00
475f8a4fa2
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
...
llvm-svn: 78622
2009-08-10 23:56:04 +00:00
3b90d973b0
Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg.
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llvm-svn: 78620
2009-08-10 23:43:28 +00:00
9d26c85bdc
Fix a bug in the DAGCombiner's handling of multiple linked
...
MERGE_VALUES nodes. Replacing the result values with the
operands in one MERGE_VALUES node may cause another
MERGE_VALUES node be CSE'd with the first one, and bring
its uses along, so that the first one isn't dead, as this
code expects. Fix this by iterating until the node is
really dead. This fixes PR4699.
llvm-svn: 78619
2009-08-10 23:43:19 +00:00
733a64db57
Fix a bug where DAGCombine was producing an illegal ConstantFP
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node after legalize, and remove the workaround code from the
ARM backend.
llvm-svn: 78615
2009-08-10 23:15:10 +00:00
9b4ea1c474
Remove MDNode from ValueMap when MDNode is destroyed.
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llvm-svn: 78612
2009-08-10 22:59:46 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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llvm-svn: 78610
2009-08-10 22:56:29 +00:00
d91dceea0f
Whitespace, 80-column, and isTwoAddress -> Constraints = "" changes.
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No functional change.
llvm-svn: 78608
2009-08-10 22:37:37 +00:00
2c6c743039
Rename MDNodeSet as MDNodes.
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llvm-svn: 78607
2009-08-10 22:31:31 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
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llvm-svn: 78604
2009-08-10 22:17:39 +00:00
148e9f0d3f
Do not rely on magic "llvm.dbg.*" global variable name to find debug info.
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PIC16 developers, please verify.
llvm-svn: 78603
2009-08-10 22:11:20 +00:00
d0658efdca
Keep track of DIType.
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llvm-svn: 78602
2009-08-10 22:09:58 +00:00
eddff647ac
Remove a bunch of debugging code that was slowing PBQP down by 25% or so.
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llvm-svn: 78601
2009-08-10 21:49:45 +00:00
458c91732c
Fix up whitespace, remove commented out code.
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llvm-svn: 78600
2009-08-10 21:48:58 +00:00
e4f79d140d
llvm-mc/AsmParser: Disambiguate i64i8imm.
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llvm-svn: 78598
2009-08-10 21:06:41 +00:00
aeb1feb67a
llvm-mc/AsmParser: Allow .td users to redefine the names of the methods to call
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on target specific operands for testing class membership and converting to
MCInst operands.
llvm-svn: 78597
2009-08-10 21:00:45 +00:00
009ac1ae04
Rename ConvertType to ConvertConstant to avoid a name conflict on llvm-gcc.
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llvm-svn: 78596
2009-08-10 20:56:46 +00:00
3e77df2bcd
SimpleValueType-ify a few more methods on TargetLowering.
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llvm-svn: 78595
2009-08-10 20:46:15 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
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llvm-svn: 78594
2009-08-10 20:25:59 +00:00
246617857f
Continue the SimpleValueType-ification.
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llvm-svn: 78593
2009-08-10 20:18:46 +00:00
0afe2cc097
llvm-mc/AsmMatcher: Fix thinko, Mem isn't a subclass of Imm.
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llvm-svn: 78587
2009-08-10 19:08:02 +00:00
0bdbee14cd
We are not using FoldingSet for metadata uniquing anymore.
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llvm-svn: 78585
2009-08-10 18:59:07 +00:00
c30530d105
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
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llvm-svn: 78584
2009-08-10 18:56:59 +00:00
17410a4b92
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record
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structure.
llvm-svn: 78581
2009-08-10 18:41:10 +00:00
850e0f9e7e
g++ 4.0 doesn't have std::vector::data.
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llvm-svn: 78579
2009-08-10 18:27:33 +00:00
13234f83ac
Change the MDNode uniquing to a ValueMap, at Devang's request.
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llvm-svn: 78577
2009-08-10 18:16:08 +00:00
6c20391d38
split MachO section handling stuff out to its out .h/.cpp file.
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llvm-svn: 78576
2009-08-10 18:15:01 +00:00
fbcafd4c6c
arm only needs to emit one .align directive for hidden nlp's, not one
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per pointer.
llvm-svn: 78574
2009-08-10 18:02:16 +00:00
292472d3d3
make sure that arm nonlazypointers are aligned properly
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llvm-svn: 78573
2009-08-10 18:01:34 +00:00
ec64b73712
Fix a weird ppc64-specific link error during an llvm-gcc build:
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ld: bad offset (0x00000091) for lo14 instruction pic-base fix-up in ___popcountdi2 from libgcc/./_popcountsi2_s.o
The problem is that the non lazy symbol pointers need to be 8 byte aligned
on ppc64 and .section doesn't have an implicit alignment like ".non_lazy_symbol_pointer"
does.
llvm-svn: 78572
2009-08-10 17:58:51 +00:00
7b01bf6125
fix some warnings for the MSVC build, by Yonggang Luo!
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llvm-svn: 78571
2009-08-10 17:35:42 +00:00
b717091e69
Make this comment more closely reflect the code.
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llvm-svn: 78569
2009-08-10 16:50:32 +00:00
f354b6ef90
Add support for printing loop structure information in asm comments.
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This definitely slows down asm output so put it under an -asm-exuberant
flag.
This information is useful when doing static analysis of performance
issues.
llvm-svn: 78567
2009-08-10 16:38:07 +00:00
62e053b790
Checkpoint scheduling itinerary changes.
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llvm-svn: 78564
2009-08-10 15:56:13 +00:00
6021b4dccc
Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
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llvm-svn: 78563
2009-08-10 15:55:25 +00:00
5bb93ce769
Watch out for empty BB.
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llvm-svn: 78562
2009-08-10 08:10:13 +00:00
8a640ae504
rev, rev16, and revsh do not set CPSR.
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llvm-svn: 78561
2009-08-10 07:58:45 +00:00
f16a1d5b79
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
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llvm-svn: 78560
2009-08-10 07:20:37 +00:00
1f5bee14a1
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
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llvm-svn: 78559
2009-08-10 06:57:42 +00:00
092b701a2c
Add support for folding loads / stores into 16-bit moves used by Thumb2.
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llvm-svn: 78558
2009-08-10 06:32:05 +00:00
55c014a9f3
80 col violation.
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llvm-svn: 78557
2009-08-10 05:51:48 +00:00
f5b73869f2
Use tMOVgpr2gpr instead of t2MOVr.
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llvm-svn: 78556
2009-08-10 05:49:43 +00:00
1bf60c257c
Add support for a user supplied pointer argument to llvm_install_error_handler.
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llvm-svn: 78553
2009-08-10 03:36:26 +00:00
9b3484dd14
Move ConstantExpr handling to ResolveConstantExpr method and also
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add support for PtrToInt, Add, Mul.
llvm-svn: 78552
2009-08-10 03:32:40 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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llvm-svn: 78550
2009-08-10 02:37:24 +00:00
5b4c308f0c
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
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llvm-svn: 78549
2009-08-10 02:06:53 +00:00
cb307a27bf
Make the big switch: Change MCSectionMachO to represent a section *semantically*
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instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
llvm-svn: 78547
2009-08-10 01:39:42 +00:00
6e046f4291
Use abs64 instead abs; some platforms don't have a 64-bit abs overload. Noticed by Yonggang Luo!
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llvm-svn: 78543
2009-08-09 22:37:07 +00:00
d461c1c559
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
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llvm-svn: 78540
2009-08-09 19:17:19 +00:00
f4c2eee251
always end a section with \n on elf.
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llvm-svn: 78534
2009-08-09 15:31:10 +00:00
8e33cb2de1
llvm-mc/AsmParser: Implement user defined super classes.
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- We can now discriminate SUB32ri8 from SUB32ri, for example.
llvm-svn: 78530
2009-08-09 07:20:21 +00:00
447c4ab91d
Extend comment on ParserMatchClass .td field, and add some missing
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classes for X86.
llvm-svn: 78524
2009-08-09 06:00:04 +00:00
c32aa060bd
llvm-mc/AsmParser: Define match classes in the .td file.
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-2 FIXMEs.
llvm-svn: 78523
2009-08-09 05:18:30 +00:00
591105c540
sink the 'name' and 'isdirective' state out of MCSection into its derived classes.
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This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-)
llvm-svn: 78517
2009-08-08 23:39:42 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
3219d85f16
add a note about dead zero extends.
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llvm-svn: 78511
2009-08-08 22:46:59 +00:00
1cb9396f4f
1. Make MCSection an abstract class.
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2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
llvm-svn: 78510
2009-08-08 22:41:53 +00:00
7dfa9f2e56
Add crc32 instruction and intrinsics. Add a new class of prefix
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bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.
New test.
llvm-svn: 78508
2009-08-08 21:55:08 +00:00
e2dc8a46e9
Add support for READCYCLECOUNTER in Blackfin back-end.
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llvm-svn: 78506
2009-08-08 21:42:22 +00:00
26cc5b78d0
add new PIC16Section class, this time hopefully not breaking the build :)
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llvm-svn: 78505
2009-08-08 21:37:01 +00:00
66f4f54e8a
llvm-mc/AsmMatcher: Switch token matching to use the new string matcher.
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Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.
llvm-svn: 78504
2009-08-08 21:22:41 +00:00
59410aaea6
Revert r78501, it doesn't build.
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--- Reverse-merging r78501 into '.':
U lib/Target/PIC16/PIC16TargetObjectFile.cpp
D lib/Target/PIC16/PIC16Section.h
llvm-svn: 78503
2009-08-08 21:12:40 +00:00
4a4e4487fc
make PIC16 create its own custom MCSection.
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llvm-svn: 78501
2009-08-08 20:55:25 +00:00
245fdfb9c3
make target-specific TLOF impls (except PIC16) create target-specific
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MCSection instances.
llvm-svn: 78500
2009-08-08 20:52:13 +00:00
5a9bc50fa8
stub out PECOFF/MachO/ELF MCSection classes
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llvm-svn: 78499
2009-08-08 20:50:49 +00:00
c9ea8fddb2
eliminate TargetLoweringObjectFileSparc in favor of a TAI hook.
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A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.
llvm-svn: 78498
2009-08-08 20:43:12 +00:00
dc6bccbaa6
Don't build illegal ops in DAGCombiner::SimplifyBinOpWithSameOpcodeHands().
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Blackfin supports and/or/xor on i32 but not on i16. Teach
DAGCombiner::SimplifyBinOpWithSameOpcodeHands to not produce illegal nodes
after legalize ops.
llvm-svn: 78497
2009-08-08 20:42:17 +00:00
36d04ec972
give pic16 a target-specific section creation name too
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llvm-svn: 78496
2009-08-08 20:23:47 +00:00
ce7d14032b
now that getOrCreateSection is all object-file specific,
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give the impls an object-file-specific name. In the future
they can take different arguments etc.
llvm-svn: 78495
2009-08-08 20:22:20 +00:00
302041d5c9
sink getOrCreateSection down into all the object file implementations,
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now that they create *all* the sections.
llvm-svn: 78494
2009-08-08 20:14:13 +00:00
2f140834cf
Some ProfileInfo cleanups.
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- Part of optimal static profiling patch sequence by Andreas Neustifter.
llvm-svn: 78485
2009-08-08 18:59:03 +00:00
003a1b1c1d
Add a basic static ProfileInfo provider (ProfileEstimatorPass).
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- Part of optimal static profiling patch sequence by Andreas Neustifter.
llvm-svn: 78484
2009-08-08 18:44:18 +00:00
f6448f57e6
Use reloc_absolute_word_sext relocation for X86::MOV64(ri/mi)32 instructions,
...
since they are in 64 bit mode with i64immSExt32 imms. JIT is not affected since
it handles both word absolute relocations in the same way
llvm-svn: 78479
2009-08-08 17:47:41 +00:00
3b5008e23a
More ProfileInfo improvements.
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- Part of optimal static profiling patch sequence by Andreas Neustifter.
- Store edge, block, and function information separately for each functions
(instead of in one giant map).
- Return frequencies as double instead of int, and use a sentinel value for
missing information.
llvm-svn: 78477
2009-08-08 17:43:09 +00:00
72dd2eef36
ELF improvements:
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Handle large integers, x86_fp80, ConstantAggregateZero, and two more ConstantExpr:
GetElementPtr and IntToPtr
Set SHF_MERGE bit for mergeable strings
Avoid zero initialized strings to be classified as a bss symbol
Don't allow common symbols to be classified as STB_WEAK
Add a constant to be used as a global value offset in data relocations
llvm-svn: 78476
2009-08-08 17:29:04 +00:00
028f6dc4c2
Update CMake
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llvm-svn: 78475
2009-08-08 17:03:13 +00:00
dcf009ca20
Clean out per-function data after the machine code verifier is done with it.
...
Also don't dereference old pointers after they have been deleted causing
random crashes when enabling the machine code verifier.
Ahem...
I have not included a test case for the crash. It hapened when enabling the
verifier on CodeGen/X86/2009-08-06-branchfolder-crash.ll.
The crash depends on an MBB being allocated at the same address as a
previously deleted MBB. I don't think that can be reproduced reliably.
llvm-svn: 78472
2009-08-08 15:34:50 +00:00
7167f33872
Add insert_elt / extract_elt patterns for v4f32 stuff.
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Did anyone tests v4f32 ever?
llvm-svn: 78470
2009-08-08 14:06:07 +00:00
4218516f5d
Lane number should be printed w/o hash
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llvm-svn: 78469
2009-08-08 14:05:53 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
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llvm-svn: 78468
2009-08-08 13:35:48 +00:00
2d59cfff24
Update the machine code verifier to keep up with the scavenger.
...
* Cleaner handling of <undef>.
* <def> takes precedence over <def,dead>.
* Implement the OK-to-redefine-a-register-that-was-
live-in-but-has-not-been-used-before rule.
llvm-svn: 78467
2009-08-08 13:19:25 +00:00
8e96c6abf7
Remove RegisterScavenger::isSuperRegUsed(). This completely reverses the mistaken commit r77904.
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Now there is no special treatment of instructions that redefine part of a
super-register. Instead, the super-register is marked with <imp-use,kill> and
<imp-def>. For instance, from LowerSubregs on ARM:
subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5
subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def>
subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6
subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def>
llvm-svn: 78466
2009-08-08 13:19:10 +00:00
ac51533b8a
Simplify RegScavenger::forward a bit more.
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Verify that early clobber registers and their aliases are not used.
All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.
The included test case is from PR4686. It has behaviour that was dependent on the order of operands.
llvm-svn: 78465
2009-08-08 13:18:47 +00:00
e372826523
move this fp select into a pattern
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llvm-svn: 78464
2009-08-08 12:49:07 +00:00
541efcc5c4
llvm-mc/AsmMatcher: Improve match code.
...
- This doesn't actually improve the algorithm (its still linear), but the
generated (match) code is now fairly compact and table driven. Still need a
generic string matcher.
- The table still needs to be compressed, this is quite simple to do and should
shrink it to under 16k.
- This also simplifies and restructures the code to make the match classes more
explicit, in anticipation of resolving ambiguities.
llvm-svn: 78461
2009-08-08 07:50:56 +00:00
Dan Gohman