Commit Graph

356650 Commits

Author SHA1 Message Date
Simon Pilgrim b296fd2024 MustExecute.h - remove unnecessary Instruction.h include. NFC.
We already have the Instruction forward declaration.
2020-06-07 12:10:50 +01:00
Simon Pilgrim 91591ec424 ObjCARCAnalysisUtils.h - remove unused LLVMContext.h include. NFC. 2020-06-07 11:48:46 +01:00
Simon Pilgrim 1e9d2f908e OrderedInstructions.h - reduce includes to forward declarations. NFC. 2020-06-07 11:44:43 +01:00
Simon Pilgrim 52d6950c47 [X86][SSE] Extend ICMP(MOVMSK(BITCAST(X))) tests to allof patterns as well as the existing noneof/anyof patterns. 2020-06-07 11:44:43 +01:00
Simon Pilgrim 0741b75ad5 [X86][SSE] Attempt to widen MOVMSK vector input if the signbits are splatted.
As shown on PR37087, if we have a MOVMSK(BICAST(X)) from a wider vector, then by using MOVMSK from the wider type (32/64-bit elements) we can improve the chances of further combines with SimplifyDemandedBits/Elts and on some targets (skylake) can be more efficient.
2020-06-07 11:44:43 +01:00
Florian Hahn 4affc444b4 [Matrix] Implement * binary operator for MatrixType.
This patch implements the * binary operator for values of
MatrixType. It adds support for matrix * matrix, scalar * matrix and
matrix * scalar.

For the matrix, matrix case, the number of columns of the first operand
must match the number of rows of the second. For the scalar,matrix variants,
the element type of the matrix must match the scalar type.

Reviewers: rjmccall, anemet, Bigcheese, rsmith, martong

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D76794
2020-06-07 11:11:27 +01:00
Jaroslav Sevcik 1beffc1888 Support build-ids of other sizes than 16 in UUID::SetFromStringRef
SBTarget::AddModule currently handles the UUID parameter in a very
weird way: UUIDs with more than 16 bytes are trimmed to 16 bytes. On
the other hand, shorter-than-16-bytes UUIDs are completely ignored. In
this patch, we change the parsing code to handle UUIDs of arbitrary
size.

To support arbitrary size UUIDs in SBTarget::AddModule, this patch
changes UUID::SetFromStringRef to parse UUIDs of arbitrary length. We
subtly change the semantics of SetFromStringRef - SetFromStringRef now
only succeeds if the entire input is consumed to prevent some
prefix-parsing confusion. This is up for discussion, but I believe
this is more consistent - we always return false for invalid UUIDs
rather than sometimes truncating to a valid prefix. Also, all the
call-sites except the API and interpreter seem to expect to consume
the entire input.

This also adds tests for adding existing modules 4-, 16-, and 20-byte
build-ids. Finally, we took the liberty of testing the minidump
scenario we care about - removing placeholder module from minidump and
replacing it with the real module.

Reviewed By: labath, friss

Differential Revision: https://reviews.llvm.org/D80755
2020-06-07 10:03:41 +00:00
Simon Pilgrim bd67d68ca1 [X86][SSE] Add MOVMSK tests where we're using a more narrow vector elements than necessary
First step towards fixing PR37087
2020-06-07 10:48:11 +01:00
Xing GUO 288025494e [ObjectYAML][DWARF] Support emitting .debug_ranges section in ELFYAML.
This patch enables yaml2elf to emit the .debug_ranges section.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D81217
2020-06-07 15:47:47 +08:00
Fangrui Song e664d0543f [gcov] Improve tests and lower the minimum supported version to gcov 3.4
global-ctor.ll no longer checks what it intended to check
(@_GLOBAL__sub_I_global-ctor.ll needs a !dbg to work).
Rewrite it.

gcov 3.4 and gcov 4.2 use the same format, thus we can lower the version
requirement to 3.4
2020-06-06 23:11:32 -07:00
Fangrui Song 693ff89f47 [gcov] Delete unneeded code 2020-06-06 20:36:46 -07:00
James Y Knight 748d92b4d3 Simplify MachineVerifier's block-successor verification.
There's two properties we want to verify:

1. That the successors returned by analyzeBranch are in the CFG
   successor list, and
2. That there are no extraneous successors are in the CFG successor
   list.

The previous implementation mostly accomplished this, but in a very
convoluted manner.

Differential Revision: https://reviews.llvm.org/D79793
2020-06-06 22:30:51 -04:00
James Y Knight 1978309db1 MachineBasicBlock::updateTerminator now requires an explicit layout successor.
Previously, it tried to infer the correct destination block from the
successor list, but this is a rather tricky propspect, given the
existence of successors that occur mid-block, such as invoke, and
potentially in the future, callbr/INLINEASM_BR. (INLINEASM_BR, in
particular would be problematic, because its successor blocks are not
distinct from "normal" successors, as EHPads are.)

Instead, require the caller to pass in the expected fallthrough
successor explicitly. In most callers, the correct block is
immediately clear. But, in MachineBlockPlacement, we do need to record
the original ordering, before starting to reorder blocks.

Unfortunately, the goal of decoupling the behavior of end-of-block
jumps from the successor list has not been fully accomplished in this
patch, as there is currently no other way to determine whether a block
is intended to fall-through, or end as unreachable. Further work is
needed there.

Differential Revision: https://reviews.llvm.org/D79605
2020-06-06 22:30:51 -04:00
Ben Shi 4b6f0ea66c [RISCV] Fix a typo in RISCVISelLowering.cpp
The 9th parameter of "static bool CC_RISCV(...)" is isFixed, not isRet.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D81333
2020-06-06 18:41:00 -07:00
Mike Edwards 972a73a347 [LIT] NFC adding max-failures option to lit documentation.
Differential Revision: https://reviews.llvm.org/D81337
2020-06-06 18:26:45 -07:00
Craig Topper 095dceefa3 [X86] Correct some isel patterns for v1i1 KNOT/KANDN/KXNOR.
The KNOT pattern was missing. The others were
looking for a v1i1 -1 instead of a vector all ones.
2020-06-06 17:25:56 -07:00
Douglas Yung 059ba74bb6 Revert "[codeview] Put !heapallocsite on calls to operator new"
This reverts commit 672ed53860.

This commit is hitting an assertion failure across multiple bots in the test:
Profile-<arch> :: instrprof-gcov-multithread_fork.test

Failing bots include:
http://lab.llvm.org:8011/builders/llvm-avr-linux/builds/2205
http://lab.llvm.org:8011/builders/clang-cmake-aarch64-lld/builds/8967
http://lab.llvm.org:8011/builders/clang-cmake-armv7-full/builds/10789
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/27750
http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/16751
2020-06-06 23:30:46 +00:00
Jan Kratochvil 8fc1e307f9 [lldb] [nfc] Fix comment in testcase DW_TAG_variable-DW_AT_const_value.s 2020-06-06 23:31:30 +02:00
Fangrui Song 398694d7c5 [gcov] Delete `XFAIL: host-byteorder-big-endian` for test/Transforms/GCOVProfiling/{exit-block.ll,function-numbering.ll} 2020-06-06 11:59:31 -07:00
LLVM GN Syncbot b264edcce8 [gn build] Port 8422bc9efc 2020-06-06 18:22:19 +00:00
Yaxun (Sam) Liu 8422bc9efc recommit "[HIP] Add default header and include path"
recommit 11d06b9511 with
fix for lit tests.
2020-06-06 14:21:22 -04:00
Fangrui Song cdd683b516 [gcov] Support big-endian .gcno and simplify version handling in .gcda 2020-06-06 11:01:47 -07:00
Jonas Paulsson 515bfc66ea [SystemZ] Implement -fstack-clash-protection
Probing of allocated stack space is now done when this option is passed. The
purpose is to protect against the stack clash attack (see
https://www.qualys.com/2017/06/19/stack-clash/stack-clash.txt).

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D78717
2020-06-06 18:38:36 +02:00
Jacques Pienaar 92cb0ce8f8 [mlir] Change to re-enable cuda-runner tests
mlir-cuda-runner tests were failing post
https://reviews.llvm.org/D80676, small change to get those passing
again. More cleanup may be needed post.
2020-06-06 09:31:51 -07:00
Matt Arsenault 38fb446fc7 AMDGPU/GlobalISel: Fix test failure in release build
The annoying behavior where the output is different due to the
legality check struck again, plus the subtarget predicate wasn't
really correctly set for DS FP atomics.

Some of the FP min/max instructions seem to be in the gfx6/gfx7
manuals, but IIRC this might have been one of the cases where the
manual got ahead of the actual hardware support, but I've left these
as-is for now since the assembler tests seem to expect them.
2020-06-06 11:01:18 -04:00
Simon Pilgrim f14d4c9c54 EHPersonalities.h - reduce Triple.h include to forward declaration. NFC.
Move implicit include dependencies down to source files.
2020-06-06 15:48:31 +01:00
Sanjay Patel 302cc8a121 [DAGCombiner] clean-up FMA+FMUL folds; NFC
D80801 suggests some readability improvements before mocing this block.
2020-06-06 10:32:54 -04:00
Simon Pilgrim eaf1ea109c CFG.h - add missing GraphTraits.h include. NFC.
MSVC doesn't care that this isn't declared for default template args but gcc (sometimes) does.
2020-06-06 15:18:25 +01:00
Simon Pilgrim e5e33f23c7 CFG.h - reduce includes to forward declarations. NFC.
Remove unnecessary includes from CFG.cpp.

Fix implicit include dependency in X86WinEHState.cpp.
2020-06-06 15:06:42 +01:00
Matt Arsenault bc20bdb9f9 AMDGPU/GlobalISel: Start rewriting load/store legality rules
The current set is an incomprehensible mess riddled with ordering
hacks for various limitations in the legalizer at the time of writing,
many of which have been fixed. This takes a very small step in
correcting this.

The core first change is to start checking for fully legal cases
first, rather than trying to figure out all of the actions that could
need to be performed. It's recommended to check the legal cases first
for faster legality checks in the common case. This still has a table
listing some common cases, but it needs measuring whether this really
helps or not.

More significantly, stop trying to allow any arbitrary type with a
legal bitwidth as a legal memory type, and start using the bitcast
legalize action for them. Allowing loads of these weird vector types
produced new burdens we don't need for handling all of the
legalization artifacts. Unlike the SelectionDAG handling, this is
still not casting 64 or 16-bit element vectors to 32-bit
vectors. These cases should still be handled by increasing/decreasing
the number of 16-bit elements. This is primarily to fix 8-bit element
vectors.

Another change is to stop trying to handle the load-widening based on
a higher alignment. We should still do this, but the way it was
handled wasn't really correct. We really need to modify the MMO's size
at the same time, and not just increase the result type. The
LegalizerHelper does not do this, and I think this would really
require a separate WidenMemory action (or to add a memory action
payload to the LegalizeMutation). These will now fail to legalize.

The structure of the legalizer rules makes writing concise rules here
difficult. It would be easier if the same function could answer the
query the query, and report the action to perform at the same
time. Instead these two are split into distinct predicate and action
functions. This is mostly tolerable for other cases, but the
load/store rules get pretty complicated so it's difficult to keep two
versions of these functions in sync.
2020-06-06 09:59:46 -04:00
dfukalov c94d32a6b3 [AMDGPU] Increase max iterations count to analyze complete unroll
Summary: In some cases inner loops may not get boosts so try to analyze them deeper.

Reviewers: rampitec, mzolotukhin

Reviewed By: rampitec

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, zzheng, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81204
2020-06-06 16:32:45 +03:00
Simon Pilgrim 72e8f07c65 LoopPassManager.h - add missing MemorySSA.h include
Fix buildbot failure due to rG5006e551d310 - oddly I can't reproduce this locally on my msvc expensive checks build.
2020-06-06 14:23:08 +01:00
Simon Pilgrim 5006e551d3 LoopAnalysisManager.h - reduce includes to forward declarations. NFC.
Move implicit include dependencies down to header/source files.
2020-06-06 14:06:46 +01:00
Paul Walker d6d2f78fe5 [SVE ACLE] Remove redundant bool_t typedef.
Subscribers: tschuett, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D81252
2020-06-06 12:31:38 +00:00
Simon Pilgrim eda13c2420 LegacyDivergenceAnalysis.h - reduce DivergenceAnalysis.h include to forward declaration. NFC.
Move implicit include dependencies down to source file.
2020-06-06 13:30:00 +01:00
Simon Pilgrim d43603c32c LoopInfoImpl.h - remove unused SetVector.h include. NFC. 2020-06-06 12:59:22 +01:00
Roman Lebedev 1eda9bfd61
[SCEV] ScalarEvolution::createSCEV(): Instruction::Or: drop bogus no-wrap flag detection
Summary:
That's just really wrong. While sure, if LHS is AddRec, and we could
propagate it's no-wrap flags, that doesn't make, because as long as
the operands of `or` had no common bits set, then the `add`
of these operands will never overflow: http://volta.cs.utah.edu:8080/z/gmt7Sy
IOW we need no propagation/detection, we are free to just set NUW+NSW.

But as rG39e3683534c83573da5c8b70c8adfb43948f601f shows,
even when the old code failed to "deduce" flags,
we'd eventually re-deduce them somewhere, later.

So let's just set them.

Reviewers: mkazantsev, reames, sanjoy, efriedma

Reviewed By: efriedma

Subscribers: efriedma, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81246
2020-06-06 13:02:07 +03:00
Roman Lebedev c868335e24
[SCEV] ScalarEvolution::createSCEV(): clarify no-wrap flag propagation for shift by bitwidth-1
Summary:
There was this comment here previously:
```
-        // It is currently not resolved how to interpret NSW for left
-        // shift by BitWidth - 1, so we avoid applying flags in that
-        // case. Remove this check (or this comment) once the situation
-        // is resolved. See
-        // http://lists.llvm.org/pipermail/llvm-dev/2015-April/084195.html
-        // and http://reviews.llvm.org/D8890 .
```
But langref was fixed in rL286785, and the behavior is pretty obvious:
http://volta.cs.utah.edu:8080/z/MM4WZP
^ nuw can always be propagated. nsw can be propagated if
either nuw is specified, or the shift is by *less* than bitwidth-1.

This mimics similar D81189 Reassociate change, alive2 is happy about that one.

I'm not sure `NUW` isn't being printed, but that seems unrelated.

Reviewers: mkazantsev, reames, sanjoy, nlopes, craig.topper, efriedma

Reviewed By: efriedma

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81243
2020-06-06 13:02:07 +03:00
Nikita Popov ff1210edb6 [NewGVN] Remove alignment from LoadExpression (NFC)
The alignment is not actually used.
2020-06-06 11:49:20 +02:00
Nikita Popov a4953db530 [InstCombine] Remove unnecessary MaybeAlign use (NFC)
Alloca align is required now.
2020-06-06 11:44:01 +02:00
Marco Elver 97a670958c [ASan][Test] Fix globals test on 32-bit architectures
Buildbot reports failures on e.g. armv7 and thumbv7. Fix the test by
expecting either i32 or i64 for the size-argument.
2020-06-06 11:23:16 +02:00
Tres Popp 4261b026ad Revert "[mlir] Canonicalization and folding of shape.cstr_broadcastable"
This reverts commit 6aab709459.

Some users have failing builds with ShapeCanonicalization.td, so revert
for now.
2020-06-06 11:17:44 +02:00
Tres Popp 12e31f6e40 Revert "[mlir] Folding and canonicalization of shape.cstr_eq"
This reverts commit 0a554e607f.

Some users have build failures when building ShapeCanonicalization.td,
so revert changes that created and rely on it.
2020-06-06 11:08:41 +02:00
Tres Popp cf72027b35 [mlir] Move attr-dict to end of Shape dialect ops
Summary: This is to be consistent with most other assemblyFormat examles in MLIR.

Differential Revision: https://reviews.llvm.org/D81245
2020-06-06 10:05:55 +02:00
Lang Hames e429cffd4f [ORC] Always use ObjectLinkingLayer/JITLink for MachO on x86-64 and arm64.
JITLink supports all code and relocation models, so there's no reason to
conditionalize using JITLink on the code or relocation model settings.

Clients wanting to use RTDyldObjectLinkingLayer/RuntimeDyld will now
need to use a custom object linking layer creator.
2020-06-05 21:02:29 -07:00
Wen-Heng (Jack) Chung 47073ccd4e [mlir][mlir-rocm-runner] Detect HIP version and AMD ISA version.
Summary:
Prior to ROCm / HIP 3.5, HSA code object V2 is the default binary format.
Starting from ROCm 3.5, HSA code object V3 becomes default.

Also invoke `rocm_agent_enumerator` to detect proper AMD ISA version on the
system. Use `gfx900` as the fallback value.

Reviewers: jerryyin yaxunl

Subscribers: mgorny, yaxunl, mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, jurahul, msifontes

Tags: #mlir

Differential Revision: https://reviews.llvm.org/D81309
2020-06-05 22:15:23 -05:00
LLVM GN Syncbot 473220c4df [gn build] Port 2920348063 2020-06-06 01:50:36 +00:00
Nico Weber 2920348063 Revert "recommit "[HIP] Add default header and include path""
This reverts commit 1fa43e0b34.
Still breaks tests on several bots, see https://reviews.llvm.org/D81176
2020-06-05 21:50:04 -04:00
Nico Weber 101fbc0138 Revert "Migrate the rest of COFFObjectFile to Error"
This reverts commit b5289656b8.
__attribute__((optnone)) doesn't build with msvc, see
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/16326
2020-06-05 21:20:11 -04:00
LLVM GN Syncbot d81b76cfe6 [gn build] Port 1fa43e0b34 2020-06-06 00:47:43 +00:00