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385 Commits

Author SHA1 Message Date
Duncan Sands f5dda01f33 Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
Eric Christopher c63d846ad6 Invert these branches by default, it makes assembly comparisons a little 
easier to read.

llvm-svn: 118148
 2010-11-03 04:29:11 +00:00
Eric Christopher 1e43892e4b Make sure we're only storing a single bit here. 
llvm-svn: 118126
 2010-11-02 23:59:09 +00:00
Eric Christopher b2abb508ae Remove an assert - it's possible to be hit, and we just want to avoid 
handling those cases for now.

llvm-svn: 117996
 2010-11-02 01:24:49 +00:00
Eric Christopher ac746e1b38 Whitespeace 
llvm-svn: 117995
 2010-11-02 01:22:45 +00:00
Eric Christopher e8fccc82e4 No really, no thumb1 for arm fast isel. Also add an informative comment as 
to what someone would need to do to support thumb1.

llvm-svn: 117994
 2010-11-02 01:21:28 +00:00
Eric Christopher 04b0a3e651 Make sure we have a legal type (and simple) before continuing. 
llvm-svn: 117848
 2010-10-30 21:25:26 +00:00
Eric Christopher 5c308f8452 Handle comparison values we already have - this fixes the consumer-typeset 
failure for llvm-gcc on arm fast isel.

llvm-svn: 117710
 2010-10-29 21:08:19 +00:00
Jim Grosbach 338de3ee56 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Jim Grosbach 055de2c789 Trailing whitespace 
llvm-svn: 117496
 2010-10-27 21:39:08 +00:00
Jim Grosbach 5a7c715470 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach 1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Eric Christopher c9616f26bd Move rejection of NEON parameters earlier in fast isel call processing, 
note that we can actually handle some f64 arguments.

llvm-svn: 117209
 2010-10-23 09:37:17 +00:00
Evan Cheng 21abfc9450 Silence compiler warnings. 
llvm-svn: 117128
 2010-10-22 18:57:05 +00:00
Eric Christopher 93bbe6599f Add some basic ret instruction support to arm fast-isel. 
llvm-svn: 117085
 2010-10-22 01:28:00 +00:00
Eric Christopher 2f8637d393 These don't need to be virtual. 
llvm-svn: 117068
 2010-10-21 21:47:51 +00:00
Eric Christopher b353e4f579 Handle storing args to the stack for calls. 
llvm-svn: 117055
 2010-10-21 20:09:54 +00:00
Eric Christopher 73bc5b0f86 More load/store refactoring, call reg+offset simplification from within 
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.

llvm-svn: 117051
 2010-10-21 19:40:30 +00:00
Eric Christopher 4ac3ed0219 Custom lower f64 args passed in integer registers. 
llvm-svn: 116977
 2010-10-21 00:01:47 +00:00
Eric Christopher af719ef86b Fix a TODO by removing some unnecesary copies. 
llvm-svn: 116915
 2010-10-20 08:02:24 +00:00
Eric Christopher 7b92c2a9a0 Revert r116220 - thus turning arm fast isel back on by default. 
llvm-svn: 116762
 2010-10-18 22:53:53 +00:00
Eric Christopher 167a700229 Remove the check for invalid calling conventions. Testing shows that they're 
working just fine.

llvm-svn: 116698
 2010-10-18 06:49:12 +00:00
Eric Christopher c103c668ce Lift arg promotion from the X86 backend. This should be unified at some point. 
llvm-svn: 116694
 2010-10-18 02:17:53 +00:00
Eric Christopher a8a9f3c52b Now that we handle all allocas via a non-SP reg offset remove all of the 
special case handling for ARM::SP.

llvm-svn: 116688
 2010-10-17 11:08:44 +00:00
Eric Christopher 730764da62 Allow more load types to be materialized through the allocas. 
llvm-svn: 116683
 2010-10-17 06:07:26 +00:00
Eric Christopher d265b3fcfe Optimize GEP off of intermediate allocas. 
llvm-svn: 116681
 2010-10-17 01:51:42 +00:00
Eric Christopher a0b9c2e9c0 Fix comment. 
llvm-svn: 116680
 2010-10-17 01:42:53 +00:00
Eric Christopher abc3a9d34b Turn on AddOperator folding in GEP. 
llvm-svn: 116679
 2010-10-17 01:41:46 +00:00
Eric Christopher 947e422c46 Use the i12 immediate versions of the load instructions - they're handled 
more in the post-passes.

llvm-svn: 116678
 2010-10-17 01:40:27 +00:00
Eric Christopher c918d550b6 Fix some funky formatting that got through. 
llvm-svn: 116653
 2010-10-16 01:10:35 +00:00
Eric Christopher f410acbbd5 Make sure offset is 0 for load/store register to the stack call. 
llvm-svn: 116640
 2010-10-15 23:07:10 +00:00
Eric Christopher a3e64c1791 Fix else if -> if in store machinery. 
llvm-svn: 116628
 2010-10-15 22:32:37 +00:00
Eric Christopher a9b3901b47 Refactor ARM fast-isel reg + offset to be a base + offset. 
llvm-svn: 116622
 2010-10-15 21:32:12 +00:00
Eric Christopher e4b3d6b379 Expand GEP handling for constant offsets. 
llvm-svn: 116594
 2010-10-15 18:02:07 +00:00
Eric Christopher 21d0c173f4 Handle more complex GEP based loads and add a few TODOs to deal with 
GEP + alloca.

llvm-svn: 116474
 2010-10-14 09:29:41 +00:00
Jim Grosbach 340cd5174b A few 80 column fixes. 
llvm-svn: 116451
 2010-10-13 23:34:31 +00:00
Eric Christopher ef83e21b57 Update comment. 
llvm-svn: 116438
 2010-10-13 21:41:51 +00:00
Eric Christopher dd0821e7ff Start handling more global variables. 
llvm-svn: 116401
 2010-10-13 09:11:46 +00:00
Eric Christopher 22e051eef0 Fix thinko in arm fast isel alloca rewrite. 
llvm-svn: 116339
 2010-10-12 21:23:43 +00:00
Eric Christopher 7cd5cda6bb Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296
 2010-10-12 05:39:06 +00:00
Eric Christopher db3bcc9910 Handle a wider arrangement of loads. 
llvm-svn: 116284
 2010-10-12 00:43:21 +00:00
Eric Christopher d42340ecfd Use a sane mechanism for that assert. 
llvm-svn: 116249
 2010-10-11 22:01:22 +00:00
Eric Christopher 72b91c1765 We're not going to handle dynamic allocas anywhere else. 
llvm-svn: 116240
 2010-10-11 21:37:35 +00:00
Eric Christopher 71ef1af66b Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232
 2010-10-11 21:20:02 +00:00
Eric Christopher e2a0b6841a Found a bug turning this on by default. Disable again for now. 
llvm-svn: 116220
 2010-10-11 20:26:21 +00:00
Eric Christopher 46cc854e5e Fix help text. 
llvm-svn: 116218
 2010-10-11 20:15:02 +00:00
Eric Christopher 5501b7e805 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217
 2010-10-11 20:05:22 +00:00
Eric Christopher 2276e87a65 Turn on arm fast isel by default. 
llvm-svn: 116212
 2010-10-11 18:48:18 +00:00
Eric Christopher e1bcb43bb9 Copy and pasteo. 
llvm-svn: 116198
 2010-10-11 08:40:05 +00:00
Eric Christopher 7ac602bc8e Whitespace cleanup in ARM fast isel. 
llvm-svn: 116197
 2010-10-11 08:38:55 +00:00
Eric Christopher eae1b38550 Add srem libcall support to ARM fast isel. 
llvm-svn: 116196
 2010-10-11 08:37:26 +00:00
Eric Christopher e11017c19e Add i8 sdiv support for ARM fast isel. 
llvm-svn: 116195
 2010-10-11 08:31:54 +00:00
Eric Christopher 511aa31965 Implement select handling for ARM fast-isel. 
llvm-svn: 116194
 2010-10-11 08:27:59 +00:00
Eric Christopher 548587c31c Fix the store part of this as well. Fixes smg2000. 
llvm-svn: 116123
 2010-10-08 23:52:16 +00:00
Eric Christopher 15bc2438d9 Move to thumb2 loads, fixes a problem with incoming registers 
as thumb1.

Fixes lencod.

llvm-svn: 116027
 2010-10-08 01:13:17 +00:00
Eric Christopher 3e1e447ca2 Remember to promote load/store types for stack to register size. 
llvm-svn: 115984
 2010-10-07 21:40:18 +00:00
Eric Christopher a2583ea9f2 Use the correct register class for load instructions - fixes 
compilation of MultiSource/Benchmarks/Bullet.

llvm-svn: 115907
 2010-10-07 05:50:44 +00:00
Eric Christopher 76a9752d45 Use the correct register class here. 
llvm-svn: 115906
 2010-10-07 05:39:19 +00:00
Eric Christopher a98be90efe Use the thumb2 conditional move instruction. 
llvm-svn: 115905
 2010-10-07 05:31:49 +00:00
Eric Christopher 6d74673366 Remove in-progress assertion, add TODO. 
llvm-svn: 115904
 2010-10-07 05:14:08 +00:00
Eric Christopher b9f2d50d5f Comment out fastisel debugging message. 
llvm-svn: 115717
 2010-10-05 23:50:58 +00:00
Eric Christopher 8cfc459274 Random cleanup and make the intermediate register in fptosi a 
32-bit fp reg, not 64-bit.

Fixes SingleSource.

llvm-svn: 115711
 2010-10-05 23:13:24 +00:00
Eric Christopher 7787f79f21 Start on lowering global addresses. 
llvm-svn: 115390
 2010-10-02 00:32:44 +00:00
Eric Christopher 83a5ec8fe0 Stub out constant GV handling, fixes C++ eh tests. 
llvm-svn: 115375
 2010-10-01 23:24:42 +00:00
Eric Christopher 9d0136274b Direct calls only for arm fast isel for now. 
llvm-svn: 115350
 2010-10-01 21:33:12 +00:00
Eric Christopher 6080da7a79 Fix thinko on store instructions. Fixes test_indvars failure. 
llvm-svn: 115342
 2010-10-01 20:46:04 +00:00
Eric Christopher c1e209d40e Implement double return values in calls. Fixes 
SingleSource/Regression/C/casts.c.

llvm-svn: 115246
 2010-10-01 00:00:11 +00:00
Eric Christopher 56094ff402 Movement and cleanup. 
llvm-svn: 115225
 2010-09-30 22:34:19 +00:00
Eric Christopher 78f8d4eaf0 Start of generalized call support for ARM fast isel. 
llvm-svn: 115203
 2010-09-30 20:49:44 +00:00
Eric Christopher 7939806ecc Refactor arm fast isel libcall handling so that pieces can be used 
for generic call handling.

llvm-svn: 115105
 2010-09-29 23:11:09 +00:00
Eric Christopher b024be3162 Add a convenience variable so I'm not chasing all over looking for 
a context.

llvm-svn: 115094
 2010-09-29 22:24:45 +00:00
Eric Christopher 3a7e8cd6bd Rework comparison handling to set a register on true/false. This avoids 
problems with phi-nodes in blocks that have hard and not virtual registers.

Accordingly update branch handling to compensate.

llvm-svn: 115013
 2010-09-29 01:14:47 +00:00
Eric Christopher edd4b600f3 Remove unnecessary set ahead of time. 
llvm-svn: 115011
 2010-09-29 00:50:57 +00:00
Eric Christopher 2c8e7f421c Remove assert, add comment. 
llvm-svn: 115009
 2010-09-29 00:49:09 +00:00
Eric Christopher a86a6d2fed 32-bit constant ints only for now. 
llvm-svn: 115001
 2010-09-28 22:47:54 +00:00
Eric Christopher 953b1afd5f Integer materialization needed the same thinko change. 
llvm-svn: 114994
 2010-09-28 21:55:34 +00:00
Eric Christopher 7990df1ae2 Rework builtin handling and call setup. The builtin handling 
now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.

llvm-svn: 114934
 2010-09-28 01:21:42 +00:00
Eric Christopher 6f98bfd870 Fix fp constant loads to have a destination register. 
llvm-svn: 114930
 2010-09-28 00:35:09 +00:00
Eric Christopher 0720611e3a Insert missing coherency in comment. Add a quick check for hardware 
divide support also.

llvm-svn: 114813
 2010-09-27 06:08:12 +00:00
Eric Christopher 29ab6d1f82 Mass rename for Jim. 
llvm-svn: 114812
 2010-09-27 06:02:23 +00:00
Eric Christopher a6ba082cb6 Thumb opcodes for thumb calls. 
llvm-svn: 114263
 2010-09-18 02:32:38 +00:00
Eric Christopher aef6499bf1 Add addrmode5 fp load support. Swap float/thumb operand adding to handle 
thumb with floating point.

llvm-svn: 114256
 2010-09-18 01:59:37 +00:00
Eric Christopher 30f2300ed2 Floating point stores have a 3rd addressing mode type. 
llvm-svn: 114254
 2010-09-18 01:23:38 +00:00
Eric Christopher 2ccc1aa696 Rework arm fast isel branch and compare code. 
llvm-svn: 114226
 2010-09-17 22:28:18 +00:00
Eric Christopher 8b9126694d Emit libcalls for SDIV, this requires some call infrastructure 
that needs to be shared a bit more widely around.

llvm-svn: 113886
 2010-09-14 23:03:37 +00:00
Eric Christopher 72497e5d90 Start sketching out ARM fast-isel calls. 
llvm-svn: 113662
 2010-09-10 23:18:12 +00:00
Eric Christopher cc766a20d3 For consistency. 
llvm-svn: 113659
 2010-09-10 23:10:30 +00:00
Eric Christopher 712bd0a604 Fix build error. 
llvm-svn: 113566
 2010-09-10 00:35:09 +00:00
Eric Christopher 860fc9370f Update comments, reorganize some code, rename variables to be 
more clear.  No functional change.

llvm-svn: 113565
 2010-09-10 00:34:35 +00:00
Eric Christopher 22fd29a94a 64-bit fp loads can come straight out of the constant pool, not as 
bad as I'd thought.

llvm-svn: 113561
 2010-09-09 23:50:00 +00:00
Eric Christopher 4bd7047324 SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move 
some data around and implement a couple of move routines to do this.

llvm-svn: 113546
 2010-09-09 21:44:45 +00:00
Eric Christopher 2cbe0fd956 New "move to fp reg" routine. Use it. 
llvm-svn: 113537
 2010-09-09 20:49:25 +00:00
Eric Christopher 82b05d7206 "Strike that, reverse it." -- Mr. Wonka. 
Truncate when truncating, extend when extending.

llvm-svn: 113536
 2010-09-09 20:36:19 +00:00
Eric Christopher 5903c0be2a Add FPTrunc, fix some bugs where I forgot to update the value map. 
llvm-svn: 113533
 2010-09-09 20:26:31 +00:00
Eric Christopher 6e3eeba4d9 Basic FP->Int, Int->FP conversions. 
llvm-svn: 113523
 2010-09-09 18:54:59 +00:00
Eric Christopher 2ff757d422 Nuke whitespace and fix some indenting. 
llvm-svn: 113463
 2010-09-09 01:06:51 +00:00
Eric Christopher bd3d121641 Handle 64-bit floating point binops as well. 
llvm-svn: 113461
 2010-09-09 01:02:03 +00:00
Eric Christopher 24dc27f73a Basic 32-bit FP operations. 
llvm-svn: 113459
 2010-09-09 00:53:57 +00:00
Eric Christopher f14b9bf98d Handle float->double extension. 
llvm-svn: 113455
 2010-09-09 00:26:48 +00:00
Eric Christopher 3cf63f1edd Rewrite TargetMaterializeConstant splitting it out into two functions 
for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.

llvm-svn: 113453
 2010-09-09 00:19:41 +00:00
Eric Christopher c3e9c404aa Very basic compare support. 
llvm-svn: 113440
 2010-09-08 23:13:45 +00:00
Eric Christopher 5838af54bf Delete dead code. 
llvm-svn: 113436
 2010-09-08 22:58:35 +00:00
Eric Christopher 6489df7c8c Make the loads/stores match the type we really want to store. 
llvm-svn: 113417
 2010-09-08 21:49:50 +00:00
Eric Christopher f5dd1929a2 Rewrite TargetMaterializeConstant. 
llvm-svn: 113387
 2010-09-08 18:56:34 +00:00
Eric Christopher 6aaed72949 Simple branch instruction support. 
llvm-svn: 112923
 2010-09-03 00:35:47 +00:00
Eric Christopher c3e118ef3d Add basic support for materializing constants (including fp) and 
stores.

llvm-svn: 112912
 2010-09-02 23:43:26 +00:00
Eric Christopher 2020d69800 Clang's -ccc-host-triple was ignoring the arch specifier on my triple, 
I don't need to implement this quite yet - and not for ConstantInt anyhow.

llvm-svn: 112798
 2010-09-02 02:30:46 +00:00
Eric Christopher 92db201e23 This should be TargetMaterializeConstant instead. 
llvm-svn: 112795
 2010-09-02 01:48:11 +00:00
Eric Christopher 6a0333c1ed One definition of isThumb is plenty, thanks. 
llvm-svn: 112793
 2010-09-02 01:39:14 +00:00
Eric Christopher 74487fcbe7 Rework arm fast-isel load and store handling. Move offset computation 
into the "address selection" routine and handle constant materialization
for stores.

llvm-svn: 112788
 2010-09-02 00:53:56 +00:00
Eric Christopher fde5a3d494 Some basic store support. 
llvm-svn: 112752
 2010-09-01 22:16:27 +00:00
Eric Christopher 3ce9c4a65f Add some more load types in. 
llvm-svn: 112721
 2010-09-01 18:01:32 +00:00
Eric Christopher 901176a755 Rewrite slightly so we can expand for floating point types easier. 
llvm-svn: 112568
 2010-08-31 01:28:42 +00:00
Eric Christopher bbd1098989 If we have an unhandled type then assert, we shouldn't get here for 
things we can't handle.

llvm-svn: 112559
 2010-08-30 23:48:26 +00:00
Eric Christopher 7a0d8c69cb Do type checks before we bother to do everything else. 
llvm-svn: 112039
 2010-08-25 08:43:57 +00:00
Eric Christopher 761e7fb605 Reorganize load mechanisms. Handle types in a little less fixed way. 
Fix some todos.  No functional change.

llvm-svn: 112031
 2010-08-25 07:23:49 +00:00
Eric Christopher 15b182f4d4 Fix predicate and add a comment. 
llvm-svn: 111981
 2010-08-24 22:34:11 +00:00
Eric Christopher 236ec8f3b5 Rework braindead conditionals I put in yesterday. 
llvm-svn: 111974
 2010-08-24 22:07:27 +00:00
Eric Christopher 6c99ebf5b0 Fix thumb2 mode loads to have the correct operand ordering. Add a todo 
to fix this in the port.

llvm-svn: 111973
 2010-08-24 22:03:02 +00:00
Eric Christopher 46d3a56e5d Update comment. 
llvm-svn: 111887
 2010-08-24 01:10:52 +00:00
Eric Christopher c0c00ca33f Fix the opcode and the operands for the load instruction. 
llvm-svn: 111885
 2010-08-24 01:10:04 +00:00
Eric Christopher eb47692c22 Add register class hack that needs to go away, but makes it more obvious 
that it needs to go away.  Use loadRegFromStackSlot where possible.

Also, remember to update the value map.

llvm-svn: 111883
 2010-08-24 00:50:47 +00:00
Eric Christopher 9d4e471cc2 Add some more debugging code, make it more obvious that RegOffset is 
getting an address for an object and select some default values.

llvm-svn: 111871
 2010-08-24 00:07:24 +00:00
Eric Christopher e3107d6283 Don't need the extra register here. 
llvm-svn: 111864
 2010-08-23 23:28:04 +00:00
Eric Christopher 414501c511 Add some more "get address into register" code and a more TODOs/FIXMEs. 
llvm-svn: 111860
 2010-08-23 23:14:31 +00:00
Eric Christopher 8d03b8a8ce Add an ARMFunctionInfo member and use it. 
llvm-svn: 111854
 2010-08-23 22:32:45 +00:00
Eric Christopher 00202ee329 Start getting ARM loads/address computation going. 
llvm-svn: 111850
 2010-08-23 21:44:12 +00:00
Eric Christopher 985d9e4ea8 Fix loop conditionals (MO.isDef() asserts that it's a reg) and 
move some constraints around.

llvm-svn: 111594
 2010-08-20 00:36:24 +00:00
Eric Christopher d8e8a2945e Add a couple of random comments. 
llvm-svn: 111592
 2010-08-20 00:20:31 +00:00
Eric Christopher a5d60c62b1 Silence warning. 
llvm-svn: 111518
 2010-08-19 15:35:27 +00:00
Eric Christopher 0d274a0258 Add an AddOptionalDefs method and use it. 
llvm-svn: 111489
 2010-08-19 00:37:05 +00:00
Eric Christopher 09f757d4bc Copy over some overridden MI wrappers for ARM fast-isel. This is where 
we're adding predicates and optional defs to the MachineInstrs.

llvm-svn: 111222
 2010-08-17 01:25:29 +00:00
Eric Christopher 663f49900d Make arm fast-isel possible to enable via command line. 
llvm-svn: 111219
 2010-08-17 00:46:57 +00:00
Evan Cheng 23b05d1cf5 ARM fastisel isn't ready. 
llvm-svn: 109421
 2010-07-26 18:32:55 +00:00
Eric Christopher 84bdfd80df Baby steps towards ARM fast-isel. 
llvm-svn: 109047
 2010-07-21 22:26:11 +00:00