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Author SHA1 Message Date
Elena Demikhovsky 714f23bcdb AVX-512: Added support for FP instructions with embedded rounding mode. 
By Asaf Badouh <asaf.badouh@intel.com>

llvm-svn: 229645
 2015-02-18 07:59:20 +00:00
Craig Topper d1e1d106ca [X86] Change comparision immediate type to i8 in test cases for AVX512 floating point comparisons. The type was already changed in the definitions and was being auto upgraded to the new type. 
llvm-svn: 227064
 2015-01-25 23:26:12 +00:00
Craig Topper 29f2e95185 [X86] Use i8 immediate for comparison type on AVX512 packed integer instructions. This matches floating point equivalents. Includes autoupgrade support to convert old code. 
llvm-svn: 227063
 2015-01-25 23:26:02 +00:00
Adam Nemet 3e8b22bc1b [AVX512] Add intrinsics for masked aligned FP loads and stores 
Similar to the unaligned cases.

Test was generated with update_llc_test_checks.py.

Part of <rdar://problem/17688758>

llvm-svn: 226296
 2015-01-16 18:50:09 +00:00
Adam Nemet 9b8cfa212c [AVX512] Remove trailing whitespaces in this test 
llvm-svn: 226295
 2015-01-16 18:50:07 +00:00
Elena Demikhovsky 949b0d46bf AVX-512: Added all forms of BLENDM instructions, 
intrinsics, encoding tests for AVX-512F and skx instructions.

llvm-svn: 224707
 2014-12-22 13:52:48 +00:00
Cameron McInally 5fb084e798 [AVX512] Add support for 512b variable bit shift intrinsics. 
llvm-svn: 224028
 2014-12-11 17:13:05 +00:00
Cameron McInally 9b7c15a364 [AVX512] Add 512b integer shift by variable intrinsics and patterns. 
llvm-svn: 222786
 2014-11-25 20:41:51 +00:00
Cameron McInally 04400449c5 [AVX512] Add 512b masked integer shift by immediate patterns. 
llvm-svn: 222002
 2014-11-14 15:43:00 +00:00
Cameron McInally 73a6bca32b [AVX512] Add integer shift by immediate intrinsics. 
llvm-svn: 221811
 2014-11-12 19:58:54 +00:00
Elena Demikhovsky be8808dc3f AVX-512: Intrinsics for ERI 
3 instructions: vrcp28, vrsqrt28, vexp2, only vector forms.
Intrinsics include SAE (Suppres All Exceptions) parameter.

http://reviews.llvm.org/D6214

llvm-svn: 221774
 2014-11-12 07:31:03 +00:00
Adam Nemet 47b2d5f1e0 [AVX512] Intrinsics for vextract*x4 
This adds the Pat<>'s for the intrinsics.  These are necessary because we
don't lower these intrinsics to SDNodes but match them directly.  See the
rational in the previous commit.

llvm-svn: 219362
 2014-10-08 23:25:37 +00:00
Robert Khasanov b51bb22611 [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VPCMP/VPCMPU{BWDQ} 
Added CMP_MASK_CC intrinsic type.
Added tests for intrinsics.

Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>

llvm-svn: 219316
 2014-10-08 15:49:26 +00:00
Robert Khasanov 28a7df0b5f [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VCMPGT{BWDQ}. 
Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>

llvm-svn: 218670
 2014-09-30 12:15:52 +00:00
Robert Khasanov a27c8e0fd9 [AVX512] Enabled intrinsics for VPCMPEQD and VPCMPEQQ. 
Added CMP_MASK intrinsic type

llvm-svn: 218667
 2014-09-30 11:19:50 +00:00
Elena Demikhovsky ff620edd3c AVX-512: Added intrinsic for VMOVSS store form with mask. 
llvm-svn: 216530
 2014-08-27 07:38:43 +00:00
Adam Nemet cee9d0a460 [AVX512] Handle valign masking intrinsic via C++ lowering 
I think that this will scale better in most cases than adding a Pat<> for each
mapping from the intrinsic DAG to the intruction (i.e. rri, rrik, rrikz).  We
can just lower to the SDNode and have the resulting DAG be matches by the DAG
patterns.

Alternatively (long term), we could keep the Pat<>s but generate them via the
new AVX512_masking multiclass.  The difficulty is that in order to formulate
that we would have to concatenate DAGs.  Currently this is only supported if
the operators of the input DAGs are identical.

llvm-svn: 215473
 2014-08-12 21:13:12 +00:00
Adam Nemet 5ec912881f [X86] Fixes commit r214890 to match the posted patch 
This was another fallout from my local rebase where something went wrong :(

llvm-svn: 214951
 2014-08-06 07:13:12 +00:00
Adam Nemet fd2161b710 [AVX512] Add masking variant and intrinsics for valignd/q 
This is similar to what I did with the two-source permutation recently.  (It's
almost too similar so that we should consider generating the masking variants
with some tablegen help.)

Both encoding and intrinsic tests are added as well.  For the latter, this is
what the IR that the intrinsic test on the clang side generates.

Part of <rdar://problem/17688758>

llvm-svn: 214890
 2014-08-05 17:23:04 +00:00
Elena Demikhovsky f164859efc AVX-512: Fixed intrinsic of VSQRTPS/PD instructions. 
I set number and types of parameters according to GCC intrinsics.

llvm-svn: 213640
 2014-07-22 11:07:31 +00:00
Adam Nemet 11dd5cf9f1 [X86] AVX512: Allow writemask argument in vpermt* intrinsics 
llvm-svn: 212223
 2014-07-02 21:26:01 +00:00
Cameron McInally 0d0489cea6 Hook up vector int_ctlz for AVX512. 
llvm-svn: 211024
 2014-06-16 14:12:28 +00:00
Cameron McInally ed5f645bf3 Fix bad copy-and-paste from r210652. AVX512 masked leading zero intrinsics. 
llvm-svn: 210901
 2014-06-13 13:20:01 +00:00
Cameron McInally 5d1b7b94e4 Add AVX512 masked leadz instrinsic support. 
llvm-svn: 210652
 2014-06-11 12:54:45 +00:00
Adam Nemet 7f62b23e92 [X86] AVX512: Add vmovntdqa 
Along with the corresponding intrinsic and tests.

llvm-svn: 210543
 2014-06-10 16:39:53 +00:00
Elena Demikhovsky e73333a50f AVX-512: minor change in rndscale intrinsic 
llvm-svn: 207937
 2014-05-04 13:35:37 +00:00
Elena Demikhovsky 299cf511c4 AVX-512: optimized a shuffle pattern to VINSERTI64x4. 
Added intrinsics for VPERMT2PS/PD/D/Q instructions.

llvm-svn: 207513
 2014-04-29 09:09:15 +00:00
Elena Demikhovsky fd05667276 AVX-512: masked load/store + intrinsics for them. 
llvm-svn: 203790
 2014-03-13 12:05:52 +00:00
Elena Demikhovsky 3ebfe11532 AVX-512: Fixed encoding of VPTESTMQ 
llvm-svn: 201980
 2014-02-23 14:28:35 +00:00
Elena Demikhovsky a30e437659 AVX-512: Added intrinsic for cvtph2ps. 
Added VPTESTNM instruction.
Added a pattern to vselect (lit tests will follow).

llvm-svn: 200823
 2014-02-05 07:05:03 +00:00
Elena Demikhovsky b19c9dc1a1 AVX-512: Embedded Rounding Control - encoding and printing 
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.

llvm-svn: 199102
 2014-01-13 12:55:03 +00:00
Elena Demikhovsky 172a27c750 AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq. 
llvm-svn: 198745
 2014-01-08 10:54:22 +00:00
Elena Demikhovsky 3629b4aa0e AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without) 
llvm-svn: 198593
 2014-01-06 08:45:54 +00:00
Elena Demikhovsky 52e4a0e109 AVX-512: Added more intrinsics for convert and min/max. 
Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.

llvm-svn: 198557
 2014-01-05 10:46:09 +00:00
Elena Demikhovsky de3f751baf AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
 2014-01-01 15:12:34 +00:00
Elena Demikhovsky cf08809813 AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC. 
I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll
I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions).

llvm-svn: 197041
 2013-12-11 14:31:04 +00:00
Elena Demikhovsky e382c3fdcd AVX-512: changed intrinsics for mask operations 
llvm-svn: 196918
 2013-12-10 13:53:10 +00:00
Elena Demikhovsky 6270b388c8 AVX-512: Changed intrinsics of VPCONFLICT to match GCC builtin form 
llvm-svn: 196914
 2013-12-10 11:58:35 +00:00
Cameron McInally e3cc4aacb9 Update AVX512 vector blend intrinsic names. 
llvm-svn: 196581
 2013-12-06 13:35:35 +00:00
Cameron McInally cbb51dacfb Fix assembly syntax for AVX512 vector blend instructions. 
llvm-svn: 196393
 2013-12-04 18:05:36 +00:00
Cameron McInally d80f7d34de Add support for AVX512 masked vector blend intrinsics. 
llvm-svn: 194006
 2013-11-04 19:14:56 +00:00
Elena Demikhovsky dacddb0bab AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen

llvm-svn: 193959
 2013-11-03 13:46:31 +00:00
Cameron McInally 394d557f41 Add AVX512 unmasked integer broadcast intrinsics and support. 
llvm-svn: 193748
 2013-10-31 13:56:31 +00:00
Elena Demikhovsky 199c823555 AVX-512: PMIN/PMAX intrinsics and patterns 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193497
 2013-10-27 08:18:37 +00:00
Quentin Colombet 8761a8f5c0 [X86][AVX512] Add patterns that match the AVX512 floating point register vbroadcast intrinsics. 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193422
 2013-10-25 18:04:12 +00:00
Quentin Colombet 4bf1c282c2 [X86][AVX512] Add patterns that match the AVX512 floating point vbroadcast intrinsics. 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193421
 2013-10-25 17:47:18 +00:00
Elena Demikhovsky dd0794e51b AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsics 
llvm-svn: 193312
 2013-10-24 07:16:35 +00:00
Elena Demikhovsky a3a714082b AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. 
llvm-svn: 192283
 2013-10-09 08:16:14 +00:00
Elena Demikhovsky 2e408aefe0 AVX-512: added scalar convert instructions and intrinsics. 
Fixed load folding in VPERM2I instruction.

llvm-svn: 192063
 2013-10-06 13:11:09 +00:00
Elena Demikhovsky 9a5ed9c3bd AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS 
llvm-svn: 189472
 2013-08-28 11:21:58 +00:00