Commit Graph

29 Commits

Author SHA1 Message Date
Brian Cain 9107594f37 [libunwind] add hexagon support 2020-04-10 04:24:10 -05:00
Sam Elliott ce3d1c6d61 [libunwind][RISCV] Add 64-bit RISC-V support
Summary:
Add unwinding support for 64-bit RISC-V.

This is from the FreeBSD implementation with the following minor
changes:

- Renamed and renumbered DWARF registers to match the RISC-V ABI [1]
- Use the ABI mneumonics in getRegisterName() instead of the exact
   register names
- Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit
   ABI in the future.

[1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

Patch by Mitchell Horne (mhorne)

Reviewers: lenary, luismarques, compnerd, phosek

Reviewed By: lenary, luismarques

Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski, simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl, benna, lenary, s.egerton, luismarques, emaste, cfe-commits

Differential Revision: https://reviews.llvm.org/D68362
2019-12-16 16:36:56 +00:00
Chandler Carruth 57b08b0944 Update more file headers across all of the LLVM projects in the monorepo
to reflect the new license. These used slightly different spellings that
defeated my regular expressions.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351648
2019-01-19 10:56:40 +00:00
Daniel Cederman 17121adfa6 [Sparc] Add Sparc V8 support
Summary:
Adds the register class implementation for Sparc.
Adds support for DW_CFA_GNU_window_save.
Adds save and restore context functionality.

Adds getArch() function to each Registers_ class to be able to separate
between DW_CFA_AARCH64_negate_ra_state and DW_CFA_GNU_window_save which
are both represented by the same constant.

On Sparc the return address is the address of the call instruction, so
an offset needs to be added when returning to skip the call instruction
and its delay slot. If the function returns a struct it is also necessary
to skip one extra instruction on Sparc V8.

Reviewers: jyknight, mclow.lists, mstorsjo, compnerd

Reviewed By: jyknight, compnerd

Subscribers: jgorbe, mgorny, christof, llvm-commits, fedor.sergeev, JDevlieghere, ldionne, libcxx-commits

Differential Revision: https://reviews.llvm.org/D55763

llvm-svn: 351044
2019-01-14 10:15:20 +00:00
Jorge Gorbe Moya 8d530b777d Revert "[Sparc] Add Sparc V8 support"
This reverts commit r350705.

llvm-svn: 350787
2019-01-10 01:08:31 +00:00
Daniel Cederman b2be18f42d [Sparc] Add Sparc V8 support
Summary:
Adds the register class implementation for Sparc.
Adds support for DW_CFA_GNU_window_save.
Adds save and restore context functionality.

On Sparc the return address is the address of the call instruction,
so an offset needs to be added when returning to skip the call instruction
and its delay slot. If the function returns a struct it is also necessary
to skip one extra instruction.

Reviewers: jyknight, mclow.lists, mstorsjo, compnerd

Reviewed By: compnerd

Subscribers: fedor.sergeev, JDevlieghere, ldionne, libcxx-commits

Differential Revision: https://reviews.llvm.org/D55763

llvm-svn: 350705
2019-01-09 12:06:05 +00:00
Martin Storsjo 09cf6374c1 [SEH] Add initial support for AArch64
This doesn't yet implement inspecting the .pdata/.xdata to find the
LSDA pointer (in UnwindCursor::getInfoFromSEH), but normal C++
exception handling seems to run just fine without it. (The only
place I can see where it's even referenced is in
unwind_phase2_forced, and I can't find a codepath where libcxxabi
would end up calling that.)

Differential Revision: https://reviews.llvm.org/D55674

llvm-svn: 349532
2018-12-18 20:05:59 +00:00
Martin Storsjo a2646444d2 Fix existing code for SEH on ARM to compile correctly
Even though SEH for ARM is incomplete, make what code already exists
at least compile correctly.

The _LIBUNWIND_CURSOR_SIZE wasn't correct.

ARM (and AArch64) have a DISPATCHER_CONTEXT field named TargetPc
instead of TargetIp.

For the libunwind.h UNW_* constants, there is no UNW_ARM_PC, only
UNW_ARM_IP.

Don't use 'r' as loop variable when 'r' already is a Registers_arm
member.

Differential Revision: https://reviews.llvm.org/D51530

llvm-svn: 341217
2018-08-31 14:56:55 +00:00
Charles Davis a7e3a6d802 Add support for SEH unwinding on Windows.
Summary:
I've tested this implementation on x86-64 to ensure that it works. All
`libc++abi` tests pass, as do all `libc++` exception-related tests. ARM
still remains to be implemented (@compnerd?).

Special thanks to KJK::Hyperion for his excellent series of articles on
how EH works on x86-64 Windows. (Seriously, check it out. It's awesome.)

I'm actually not sure if this should go in as is. I particularly don't
like that I duplicated the UnwindCursor class for this special case.

Reviewers: mstorsjo, rnk, compnerd, smeenai, javed.absar

Subscribers: mgorny, kristof.beyls, christof, chrib, cfe-commits, compnerd, llvm-commits

Differential Revision: https://reviews.llvm.org/D50564

llvm-svn: 341125
2018-08-30 21:29:00 +00:00
whitequark 4f9c59f863 [OR1K] Add the EPCR special-purpose register to register state.
This makes it possible to unwind hardware exception stack frames,
which necessarily save every register and so need an extra column
for storing the return address. CFI for the exception handler could
then look as follows:

.globl exception_vector
exception_vector:
    .cfi_startproc
    .cfi_signal_frame
    .cfi_return_column 32
    l.addi  r1, r1, -0x100
    .cfi_def_cfa_offset 0x100
    l.sw    0x00(r1), r2
    .cfi_offset 2, 0x00-0x100
    l.sw    0x04(r1), r3
    .cfi_offset 3, 0x04-0x100
    l.sw    0x08(r1), r4
    .cfi_offset 4, 0x08-0x100
    l.mfspr r3, r0, SPR_EPCR_BASE
    l.sw    0x78(r1), r3
    .cfi_offset 32, 0x78-0x100
    l.jal   exception_handler
     l.nop
    l.lwz   r2, 0x00(r1)
    l.lwz   r3, 0x04(r1)
    l.lwz   r4, 0x08(r1)
    l.jr    r9
     l.nop
    .cfi_endproc

This register could, of course, also be accessed by the trace
callback or personality function, if so desired.

llvm-svn: 332513
2018-05-16 19:09:48 +00:00
John Baldwin c3f240f7dc [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
Summary:
For MIPS ABIs with 64-bit floating point registers including newabi
and O32 with 64-bit floating point registers, just save and restore the
32 floating-point registers as doubles.

For O32 MIPS with 32-bit floating-point registers, save and restore the
individual floating-point registers as "plain" registers.  These registers
are encoded as floats rather than doubles, but the DWARF unwinder
assumes that floating-point registers are stored as doubles when reading
them from memory (via AddressSpace::getDouble()).  Treating the
registers as "normal" registers instead causes the DWARF unwinder to
fetch them from memory as a 32-bit register.  This does mean that for
O32 with 32-bit floating-point registers unw_get_fpreg() and
unw_set_fpreg() do not work.  One would have to use unw_get_reg()
and unw_set_reg() instead.  However, DWARF unwinding works
correctly as the DWARF CFI emits records for individual 32-bit
floating-point registers even when they are treated as doubles stored
in paired registers.  If the lack of unw_get/set_fpreg() becomes a pressing
need in the future for O32 MIPS we could add in special handling to
make it work.

Reviewers: sdardis, compnerd

Reviewed By: sdardis

Differential Revision: https://reviews.llvm.org/D41968

llvm-svn: 332414
2018-05-15 22:44:56 +00:00
John Baldwin 0594aee52f [libunwind][MIPS]: Add support for unwinding in N32 processes.
Summary:
N32 uses the same register context as N64.  However, N32 requires one
change to properly fetch addresses from registers stored in memory.
Since N32 is an ILP32 platform, getP() only fetches the first 32-bits
of a stored register.  For a big-endian platform this fetches the
upper 32-bits which will be zero.  To fix this, add a new
getRegister() method to AddressSpace which is responsible for
extracting the address stored in a register in memory.  This matches
getP() for all current ABIs except for N32 where it reads the 64-bit
register and returns the low 32-bits as an address.  The
DwarfInstructions::getSavedRegister() method uses
AddressSpace::getRegister() instead of AddressSpace::getP().

Reviewers: sdardis, compnerd

Reviewed By: sdardis

Differential Revision: https://reviews.llvm.org/D39074

llvm-svn: 326250
2018-02-27 21:24:02 +00:00
Martin Storsjo 89e636c87c [PPC64] Added vector registers.
The Registers_ppc64 class needed a couple of changes, both to accommodate the
new registers as well as to handle the overlaps of VS register set
without wasting space.

The save/restore code of V and VS registers was added.
As VS registers depend on the VMX extension, they are processed only if
VMX support is detected (_ARCH_PWR8 for now).

Patch by Leandro Lupori!

Differential Revision: https://reviews.llvm.org/D41906

llvm-svn: 322596
2018-01-16 20:54:10 +00:00
John Baldwin 40bab37551 [libunwind][MIPS]: Rename Registers_mips_n64 to Registers_mips_newabi.
This is in preparation for adding support for N32 unwinding which reuses
the newabi register class.

Reviewed By: compnerd

Differential Revision: https://reviews.llvm.org/D41842

llvm-svn: 322093
2018-01-09 17:07:18 +00:00
Martin Storsjo 7c907061aa Reland [PPC64] Port to ppc64le - initial version
Initial working version of libunwind for PowerPC 64. Tested on
little-endian ppc64 host only.
Based on the existing PowerPC 32 code.

It supports:

- context save/restore (unw_getcontext, unw_init_local, unw_resume)
- read/write from/to saved registers
- backtrace (unw_step)

Patch by Leandro Lupori!

Differential Revision: https://reviews.llvm.org/D41386

Now builds with LIBUNWIND_ENABLE_CROSS_UNWINDING=ON should
work.

llvm-svn: 321680
2018-01-02 22:11:30 +00:00
Tim Shen f5d150037a Revert `rL321667: [PPC64] Port to ppc64le - initial version`
Differential Revision: https://reviews.llvm.org/D41386

llvm-svn: 321678
2018-01-02 22:04:03 +00:00
Martin Storsjo 0aa55fdbba [PPC64] Port to ppc64le - initial version
Initial working version of libunwind for PowerPC 64. Tested on
little-endian ppc64 host only.
Based on the existing PowerPC 32 code.

It supports:

- context save/restore (unw_getcontext, unw_init_local, unw_resume)
- read/write from/to saved registers
- backtrace (unw_step)

Patch by Leandro Lupori!

Differential Revision: https://reviews.llvm.org/D41386

llvm-svn: 321667
2018-01-02 20:10:54 +00:00
John Baldwin dfbbbdf8cd [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
This supports the soft-float ABI only and has been tested with both clang
and gcc on FreeBSD.

Reviewed By: sdardis, compnerd

Differential Revision: https://reviews.llvm.org/D38110

llvm-svn: 320528
2017-12-12 21:43:36 +00:00
Martin Storsjo 6a3ed9bfd0 Fix building for ARM with dwarf exception handling
The previous definition of _LIBUNWIND_HIGHEST_DWARF_REGISTER seems
to be a copy of the ARM64 value (introduced in SVN r276128); since
the code actually hasn't compiled properly for arm in dwarf mode
before, this hasn't actually been used. Set it to the correct value
based on the UNW_ARM_* enum values.

The iwmmx control variables have to be made mutable, since they are
touched from within getRegister (which previously wasn't const), and
getRegister is used on a const Registers object in DwarfInstructions.hpp.

Differential Revision: https://reviews.llvm.org/D39251

llvm-svn: 317192
2017-11-02 08:16:16 +00:00
Martin Storsjo c18d5c05cb Change unw_word_t to always have the same size as the pointer size
This matches the original libunwind API. This also unifies the
type between ARM EHABI and the other configurations, and allows
getting rid of a number of casts in log messages.

The cursor size updates for ppc and or1k are untested, but
unw_proc_info_t shrinks by 4 uint64_t units on i386 at least.

Differential Revision: https://reviews.llvm.org/D39365

llvm-svn: 316942
2017-10-30 19:06:34 +00:00
Martin Storsjo d9e8909261 Restore arch specific lastDwarfRegNum in builds without _LIBUNWIND_IS_NATIVE_ONLY
This restores the previous behaviour of the Registers_* classes
after SVN r316745.

Differential Revision: https://reviews.llvm.org/D39382

llvm-svn: 316843
2017-10-28 20:19:49 +00:00
Martin Storsjo 66bb841f64 Add support for dwarf unwinding on windows on x86_64
Clang doesn't currently support building for windows/x86_64 with
dwarf by setting command line parameters, but if manually modified
to use dwarf, we can make libunwind work in this configuration
as well.

Also include i386 in the docs when adding this as a supported
configuration; libunwind already works for i386 windows, but
can fail due to an issue unrelated to windows itself.

Differential Revision: https://reviews.llvm.org/D38819

llvm-svn: 316747
2017-10-27 08:11:36 +00:00
Martin Storsjo 62dd9d20d5 Express Registers_*::lastDwarfReg using _LIBUNWIND_HIGHEST_DWARF_REGISTER
This avoids having to keep the same information duplicated in multiple
places.

Adjust _LIBUNWIND_HIGHEST_DWARF_REGISTER to actually have the value
of the highest used register and only use the value
_LIBUNWIND_HIGHEST_DWARF_REGISTER + 1 (kMaxRegisterNumber + 1) for
allocating the savedRegisters array.

Differential Revision: https://reviews.llvm.org/D39281

llvm-svn: 316745
2017-10-27 07:59:01 +00:00
Martin Storsjo dd45ea16f3 Fix the context/cursor size for ARM with WMMX enabled
This was missed in SVN r274744 when the WMMX part was made optional;
when made optional, some struct fields were reordered, which caused
the total struct size to grow due to padding/alignment.

llvm-svn: 316559
2017-10-25 08:07:19 +00:00
Ranjeet Singh 5808011bd9 [libunwind] Clean up macro usage.
Convention in libunwind is to use !defined(FOOT) not !FOO.

Differential Revision: https://reviews.llvm.org/D31078

llvm-svn: 299225
2017-03-31 15:28:06 +00:00
Ed Maste 41020b94a3 libunwind: limit stack usage in unwind cursor
Obtained from FreeBSD SVN r302475

Differential Revision:	https://reviews.llvm.org/D22570

llvm-svn: 276128
2016-07-20 15:19:09 +00:00
Asiri Rathnayake f33c3423ec [libunwind][ARM] Improve unwinder stack usage - Make WMMX support optional
These registers are only available on a limited set of ARM targets (those
based on XScale). Other targets should not have to pay the cost of these.

This patch shaves off about ~300 bytes of stack usage and ~1KB of code-size.

Differential revision: http://reviews.llvm.org/D21991
Reviewers: bcraig, compnerd

Change-Id: I2d7a1911a193bd70b123e78747e1a7d1482463c7
llvm-svn: 274744
2016-07-07 10:55:39 +00:00
Asiri Rathnayake 54387eef07 Introduce a native-only unwinder build.
Currently libunwind is built to support cross-unwinding [1] by default, which
requires the buffers unw_context_t and unw_cursor_t to be large enough to hold
the vritual register set (VRS) of any supported architecture. This is not
desirable for some platforms where the stack usage of the unwinder needs
to be kept to a minimum (e.g. bare-metal targets). The current patch introduces
a native-only (-DLIBUNWIND_ENABLE_CROSS_UNWINDING=OFF) unwinder variant that
adopts strict sizes for the buffers unw_context_t and unw_cursor_t depending
on the target architecture.

[1] http://www.nongnu.org/libunwind/man/libunwind(3).html#section_4

Change-Id: I380fff9a56c16a0fc520e3b1d8454a34b4a48373
llvm-svn: 270692
2016-05-25 12:36:34 +00:00
Logan Chien 5191fe9509 libunwind: Introduce __libunwind_config.h.
Introduce __libunwind_config.h to avoid cross repository circular
dependency with libcxxabi.

llvm-svn: 242642
2015-07-19 15:23:10 +00:00