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16 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen e782fa649f Fix test that depends on register allocation. 
The test is really checking the prolog/epilog load/store multiple
formation.

llvm-svn: 158328
 2012-06-11 21:14:28 +00:00
Jakob Stoklund Olesen 8ec1a92afd Linear scan is going away. 
llvm-svn: 144472
 2011-11-12 22:39:34 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
 2011-08-11 18:07:11 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
 2011-08-11 17:35:48 +00:00
Jakob Stoklund Olesen 0888bcf542 Fix ARM tests to be register allocator independent. 
llvm-svn: 128680
 2011-03-31 22:14:03 +00:00
Anton Korobeynikov 879be84aa5 Update the test 
llvm-svn: 122666
 2011-01-01 20:57:26 +00:00
Jim Grosbach 5fccad84a3 ARM stm/ldm instructions require more than one register in the register list. 
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460

llvm-svn: 121391
 2010-12-09 18:31:13 +00:00
Eric Christopher b006fc9c07 Rewrite stack callee saved spills and restores to use push/pop instructions. 
Remove movePastCSLoadStoreOps and associated code for simple pointer
increments. Update routines that depended upon other opcodes for save/restore.

Adjust all testcases accordingly.

llvm-svn: 119725
 2010-11-18 19:40:05 +00:00
Jim Grosbach 3fe94f1e9f FileCheck'ize 
llvm-svn: 117401
 2010-10-26 21:26:47 +00:00
Johnny Chen 8f3004cff2 Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm 
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]

llvm-svn: 98745
 2010-03-17 17:52:21 +00:00
Bob Wilson 1b4e8cc69c --- Reverse-merging r98637 into '.': 
U    test/CodeGen/ARM/tls2.ll
U    test/CodeGen/ARM/arm-negative-stride.ll
U    test/CodeGen/ARM/2009-10-30.ll
U    test/CodeGen/ARM/globals.ll
U    test/CodeGen/ARM/str_pre-2.ll
U    test/CodeGen/ARM/ldrd.ll
U    test/CodeGen/ARM/2009-10-27-double-align.ll
U    test/CodeGen/Thumb2/thumb2-strb.ll
U    test/CodeGen/Thumb2/ldr-str-imm12.ll
U    test/CodeGen/Thumb2/thumb2-strh.ll
U    test/CodeGen/Thumb2/thumb2-ldr.ll
U    test/CodeGen/Thumb2/thumb2-str_pre.ll
U    test/CodeGen/Thumb2/thumb2-str.ll
U    test/CodeGen/Thumb2/thumb2-ldrh.ll
U    utils/TableGen/TableGen.cpp
U    utils/TableGen/DisassemblerEmitter.cpp
D    utils/TableGen/RISCDisassemblerEmitter.h
D    utils/TableGen/RISCDisassemblerEmitter.cpp
U    Makefile.rules
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/Makefile
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D    lib/Target/ARM/Disassembler
U    lib/Target/ARM/ARMInstrFormats.td
U    lib/Target/ARM/ARMAddressingModes.h
U    lib/Target/ARM/Thumb2ITBlockPass.cpp

llvm-svn: 98640
 2010-03-16 16:59:47 +00:00
Johnny Chen 3d9327bd06 Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend 
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]

llvm-svn: 98637
 2010-03-16 16:36:54 +00:00
Dan Gohman c8054d90fb Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81293
 2009-09-09 00:09:15 +00:00
Evan Cheng 7f5976e11b Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface. 
llvm-svn: 72826
 2009-06-04 01:15:28 +00:00
Evan Cheng ab0c710fae Temporarily revert 72756 for now. 
llvm-svn: 72757
 2009-06-03 07:40:47 +00:00
Evan Cheng dfe6e689fd Fold preceding / trailing base inc / dec into the single load / store as well. 
llvm-svn: 72756
 2009-06-03 06:14:58 +00:00