Commit Graph

8 Commits

Author SHA1 Message Date
Tim Northover c7ea8048e7 ARM: don't expand atomicrmw inline on Cortex-M0
There's a barrier instruction so that should still be used, but most actual
atomic operations are going to need a platform decision on the correct
behaviour (either nop if single-threaded or OS-support otherwise).

rdar://problem/15287210

llvm-svn: 193399
2013-10-25 09:30:24 +00:00
Tim Northover a564d329c2 LegalizeDAG: allow libcalls for max/min atomic operations
ARM processors without ldrex/strex need to be able to make libcalls for all
atomic operations, including the newer min/max versions.

The alternative would probably be expanding these operations in terms of
cmpxchg (as x86 does always), but in the configurations where this matters
code-size tends to be paramount so the libcall is more desirable.

llvm-svn: 193398
2013-10-25 09:30:20 +00:00
Jakob Stoklund Olesen d3bda3c5b9 Fix a couple of typos in EmitAtomic.
Thumb2 instructions are mostly constrained to rGPR, not tGPR which is
for Thumb1.

rdar://problem/12203728

llvm-svn: 162968
2012-08-31 02:08:34 +00:00
Chad Rosier 7248bda595 Fix a couple of copy-n-paste bugs. Noticed by George Russell!
llvm-svn: 147064
2011-12-21 18:56:22 +00:00
Evan Cheng dc8a1aaea6 Fix a couple of copy-n-paste bugs. Noticed by George Russell.
llvm-svn: 147032
2011-12-21 03:04:10 +00:00
Eli Friedman c064f2c33e Convert more tests over to the new atomic instructions.
llvm-svn: 140559
2011-09-26 20:27:49 +00:00
Jakob Stoklund Olesen 50ef7611aa Atomic pseudos don't use (as in read) CPSR. They clobber it.
llvm-svn: 139148
2011-09-06 17:40:35 +00:00
Cameron Zwarich 1d553a2cc4 Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
and add some basic tests for them.

llvm-svn: 132235
2011-05-27 23:54:00 +00:00