llvm-project

Commit Graph

Author	SHA1	Message	Date
Jia Liu	b22310fda6	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878	2012-02-18 12:03:15 +00:00
Kalle Raiskila	a5538cdbf9	Fix a thinko in 123226 that caused test failures on "other" platforms. llvm-svn: 123229	2011-01-11 11:27:56 +00:00
Kalle Raiskila	be9ad1e631	Add a "nop filler" pass to SPU. Filling no-ops is done just before emitting of assembly, when the instruction stream is final. No-ops are inserted to align the instructions so the dual-issue of the pipeline is utilized. This speeds up generated code with a minimum of 1% on a select set of algorithms. This pass may be redundant if the instruction scheduler and all subsequent passes that modify the instruction stream (prolog+epilog inserter, register scavenger, are there others?) are made aware of the instruction alignments. llvm-svn: 123226	2011-01-11 09:07:54 +00:00

Author

SHA1

Message

Date

Jia Liu

b22310fda6

Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

llvm-svn: 150878

2012-02-18 12:03:15 +00:00

Kalle Raiskila

a5538cdbf9

Fix a thinko in 123226 that caused test failures on "other" platforms.

llvm-svn: 123229

2011-01-11 11:27:56 +00:00

Kalle Raiskila

be9ad1e631

Add a "nop filler" pass to SPU.

Filling no-ops is done just before emitting of assembly,
when the instruction stream is final. No-ops are inserted
to align the instructions so the dual-issue of the pipeline
is utilized. This speeds up generated code with a minimum of 
1% on a select set of algorithms.

This pass may be redundant if the instruction scheduler and 
all subsequent passes that modify the instruction stream 
(prolog+epilog inserter, register scavenger, are there others?)
are made aware of the instruction alignments.

llvm-svn: 123226

2011-01-11 09:07:54 +00:00

3 Commits