Threading was disabled in r317263 because it broke a test in combination
with `-DLLVM_ENABLE_THREADS=OFF`. This was because a ThreadPool warning
was piped to llvm-dwarfdump which was expecting to read an object from
stdin.
This patch re-enables threading and fixes the offending test.
Unfortunately this required more than just moving the ThreadPool out of
the for loop because of the TempFile refactoring that took place in the
meantime.
Differential revision: https://reviews.llvm.org/D41180
llvm-svn: 320601
Having a SectionBase method check Repl is inconsistent with how we
handle other section information.
For example, if a section is replaced, Sec->Live is false and it is
natural for Sec->getOutputSection() to be null.
It is the symbol that is moved to the replacement section.
llvm-svn: 320599
Summary:
See D40657 & D40679 for previous versions of this patch & description.
A couple of things were fixed here to have it not break some bots.
Weak symbols can't be used with `SANITIZER_GO` so the previous version was
breakin TsanGo. I set up some additional local tests and those pass now.
I changed the workaround for the glibc vDSO issue: `__progname` is initialized
after the vDSO and is actually public and of known type, unlike
`__vdso_clock_gettime`. This works better, and with all compilers.
The rest is the same.
Reviewers: alekseyshl
Reviewed By: alekseyshl
Subscribers: srhines, kubamracek, krytarowski, llvm-commits, #sanitizers
Differential Revision: https://reviews.llvm.org/D41121
llvm-svn: 320594
There are two /proc/cpuinfo layots in use for AArch64: old and new.
The old one has all 'processor : n' lines in one section, hence
checking for duplications does not make sense.
Differential Revision: https://reviews.llvm.org/D41000
llvm-svn: 320593
Summary:
getScudoChunk function is implicitly inlined for optimized builds on
clang, but not on gcc. It's a small enough function that it seems
sensible enough to just inline it by default.
Reviewers: cryptoad, alekseyshl
Reviewed By: cryptoad
Differential Revision: https://reviews.llvm.org/D41138
llvm-svn: 320592
The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).
Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.
Differential Revision: https://reviews.llvm.org/D30431
llvm-svn: 320584
Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.
llvm-svn: 320575
Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK
We'd probably get more hits if SimplifyDemandedBits was better at handling vectors...
Differential Revision: https://reviews.llvm.org/D41119
llvm-svn: 320570
Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.
This patch builds upon D40902.
Differential Revision: https://reviews.llvm.org/D41071
Patch by Mario Werner.
llvm-svn: 320569
Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`.
Only debug syntax is affected.
llvm-svn: 320565
Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of
`<cp#0-8>`.
Only debug syntax is affected.
Differential Revision: https://reviews.llvm.org/D41116
llvm-svn: 320564
Previously, v2i16 -> f32 bitcast could not be matched.
Add patterns to support matching this and similar types of bitcasts.
Differential revision: https://reviews.llvm.org/D40959
llvm-svn: 320562
Summary:
This makes it possible to run an arbitrary matcher on the value
contained within the Expected<T> object.
To do this, I've needed to fully spell out the matcher, instead of using
the shorthand MATCHER_P macro.
The slight gotcha here is that standard template deduction will fail if
one tries to match HasValue(47) against an Expected<int &> -- the
workaround is to use HasValue(testing::Eq(47)).
The explanations produced by this matcher have changed a bit, since now
we delegate to the nested matcher to print the value. Since these don't
put quotes around the value, I've changed our PrintTo methods to match.
Reviewers: zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41065
llvm-svn: 320561
When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.
This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.
Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.
llvm-svn: 320560
NFC.
Adding MC regressions tests to cover the BMI1 and BMI2 ISA sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, craig.topper, m_zuckerman, RKSimon
Differential Revision: https://reviews.llvm.org/D41106
Change-Id: I033ce137b5b82d36e1e601cd5e0534637b43a4a9
llvm-svn: 320557
r320413 triggered cmake configure failures when building with
-DLLVM_OPTIMIZED_TABLEGEN=True and with LLVM_EXPERIMENTAL_TARGETS_TO_BUILD set
(e.g. to RISCV). This is because that patch moved to passing through
LLVM_TARGETS_TO_BUILD, and at that point LLVM_EXPERIMENTAL_TARGETS_TO_BUILD
has been merged in to it. LLVM_EXPERIMENTAL_TARGETS_TO_BUILD must be also be
passed through to avoid errors like below:
-- Constructing LLVMBuild project information
CMake Error at CMakeLists.txt:682 (message):
The target `RISCV' does not exist.
It should be one of
AArch64;AMDGPU;ARM;BPF;Hexagon;Lanai;Mips;MSP430;NVPTX;PowerPC;Sparc;SystemZ;X86;XCore
-- Configuring incomplete, errors occurred!
See the thread
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20171211/509225.html
for discussion of this fix.
llvm-svn: 320556
Summary:
- when the diagnostic has an explicit range, we prefer that
- if the diagnostic has a fixit, its RemoveRange is our next choice
- otherwise we try to expand the diagnostic location into a whole token.
(inspired by VSCode, which does this client-side when given an empty range)
- if all else fails, we return the zero-width range as now.
(clients react in different ways to this, highlighting a token or a char)
- this includes the off-by-one fix from D40860, and borrows heavily from it
Reviewers: rwols, hokein
Subscribers: klimek, ilya-biryukov, cfe-commits
Differential Revision: https://reviews.llvm.org/D41118
llvm-svn: 320555
Simon Pilgrim