d9a00a9c38
[Hexagon] Adding doubleword multiplies with and without accumulation.
...
llvm-svn: 224293
2014-12-16 00:07:24 +00:00
18c927620a
[Hexagon] Adding halfword to doubleword multiplies.
...
llvm-svn: 224289
2014-12-15 23:29:37 +00:00
64ffd52943
[Hexagon] Adding logical-logical accumulation instructions and tests.
...
llvm-svn: 224288
2014-12-15 23:19:07 +00:00
71e11a1d0d
[Hexagon] Adding a number of additional multiply forms with tests.
...
llvm-svn: 224282
2014-12-15 22:10:37 +00:00
4a46429305
[Hexagon] Adding misc multiply encodings and tests.
...
llvm-svn: 224273
2014-12-15 21:17:03 +00:00
26f884aedf
[Hexagon] Adding doubleworld accumulating multiplies of halfwords.
...
llvm-svn: 224267
2014-12-15 20:17:46 +00:00
572c53e258
[Hexagon] Adding accumulating half word multiplies.
...
llvm-svn: 224266
2014-12-15 20:10:28 +00:00
d1704cdc07
[Hexagon] Adding multiply with rnd/sat/rndsat
...
llvm-svn: 224265
2014-12-15 20:01:59 +00:00
fe4012a969
[Hexagon] Adding encoding bits for halfword multiplies.
...
llvm-svn: 224261
2014-12-15 19:22:07 +00:00
150b6b3a73
[Hexagon] Renaming classes in preparation for replacement.
...
llvm-svn: 224036
2014-12-11 19:01:28 +00:00
adab80720d
[Hexagon] Ading i64 <- i32, i32 sextw pattern.
...
llvm-svn: 224027
2014-12-11 17:08:21 +00:00
eb52f69f59
[Hexagon] Adding encoding information for sign extend word instruction.
...
llvm-svn: 224026
2014-12-11 16:43:06 +00:00
db0b13cef0
[Hexagon] Adding encodings for JR class instructions. Updating complier usages.
...
llvm-svn: 223967
2014-12-10 21:24:10 +00:00
8872d20788
[Hexagon] Adding JR class predicated call reg instructions.
...
llvm-svn: 223933
2014-12-10 18:24:16 +00:00
b32bf14c2a
[Hexagon] [NFC] Cleaning up unused classes.
...
llvm-svn: 223845
2014-12-09 22:33:26 +00:00
b030c254c0
[Hexagon] Fixing broken tests.
...
llvm-svn: 223823
2014-12-09 20:36:53 +00:00
4af437fee5
[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.
...
llvm-svn: 223821
2014-12-09 20:23:30 +00:00
b580d7d8c8
[Hexagon] Adding word combine dot-new form and replacing old combine opcode.
...
llvm-svn: 223815
2014-12-09 19:23:45 +00:00
30dcb232b0
[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.
...
llvm-svn: 223800
2014-12-09 18:16:49 +00:00
5cf5632696
[Hexagon] Removing old def versions and replacing usages with versions that have encodings.
...
llvm-svn: 223720
2014-12-08 23:55:43 +00:00
f5b4d655d2
[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns.
...
llvm-svn: 223710
2014-12-08 23:07:59 +00:00
b6c4dd96f9
[Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns.
...
llvm-svn: 223702
2014-12-08 22:19:14 +00:00
9bfe5473da
[Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass.
...
llvm-svn: 223701
2014-12-08 21:56:47 +00:00
025f860638
[Hexagon] Adding xtype parity, min, minu, max, maxu instructions.
...
llvm-svn: 223693
2014-12-08 21:19:18 +00:00
8d1376c60e
[Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions.
...
llvm-svn: 223692
2014-12-08 20:33:01 +00:00
cc46cd8eec
[Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift patterns.
...
llvm-svn: 223680
2014-12-08 18:33:49 +00:00
b56e6cd9b9
[Hexagon] Adding combine reg, reg with predicated forms.
...
llvm-svn: 223667
2014-12-08 17:33:06 +00:00
a55070dbdd
[Hexagon] Adding packhl instruction.
...
llvm-svn: 223664
2014-12-08 17:01:18 +00:00
d8b766072b
[Hexagon] Relocating logical instructions and templates later in the td file.
...
llvm-svn: 223523
2014-12-05 21:51:12 +00:00
2c77a35e6e
[Hexagon] Adding sub/and/or reg, imm forms
...
llvm-svn: 223522
2014-12-05 21:38:29 +00:00
9665f98c10
[Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
...
llvm-svn: 223515
2014-12-05 21:09:27 +00:00
19985e9a8d
[Hexagon] Adding tfrih/l instructions.
...
llvm-svn: 223506
2014-12-05 20:07:19 +00:00
a4ab58101a
[Hexagon] Adding add reg, imm form with encoding bits and test.
...
llvm-svn: 223504
2014-12-05 19:51:23 +00:00
383c36e3a8
[Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding combine imm-imm form.
...
llvm-svn: 223494
2014-12-05 18:24:06 +00:00
63035ebee1
[Hexagon] [NFC] Rearranging patterns and mux instruction.
...
llvm-svn: 223488
2014-12-05 17:58:06 +00:00
7358593e34
[Hexagon] [NFC] Rearranging def order.
...
llvm-svn: 223487
2014-12-05 17:55:51 +00:00
7f0a430c7d
[Hexagon] Adding combine reg-reg forms.
...
llvm-svn: 223485
2014-12-05 17:38:36 +00:00
01785bb063
[Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassembly tests for many instructions.
...
llvm-svn: 223482
2014-12-05 17:27:39 +00:00
5d6f03bd5a
[Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests.
...
llvm-svn: 223334
2014-12-04 03:41:21 +00:00
6e0f9f8d61
[Hexagon] Adding cmp* immediate form instructions.
...
llvm-svn: 222849
2014-11-26 19:43:12 +00:00
31abe33726
[Hexagon] Adding and64, or64, and xor64 instructions.
...
llvm-svn: 222846
2014-11-26 18:55:59 +00:00
c50d64b07b
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
...
llvm-svn: 222801
2014-11-26 00:46:26 +00:00
b3d08bb44b
[Hexagon] Adding add64 and sub64 instructions.
...
llvm-svn: 222795
2014-11-25 22:15:44 +00:00
6f6c4ff1fc
Reverting 222792
...
llvm-svn: 222793
2014-11-25 21:39:57 +00:00
aaf33928ee
[Hexagon] Adding compare with immediate instructions.
...
llvm-svn: 222792
2014-11-25 21:30:28 +00:00
6f352b03a4
[Hexagon] Adding NOP encoding bits.
...
llvm-svn: 222791
2014-11-25 21:23:07 +00:00
e83bc7476f
[Hexagon] Adding C2_mux instruction.
...
llvm-svn: 222784
2014-11-25 20:20:09 +00:00
902157c249
[Hexagon] Replacing cmp* instructions with ones that contain encoding bits.
...
llvm-svn: 222771
2014-11-25 18:20:52 +00:00
397a25e7cd
[Hexagon] Adding asrh instruction, removing unused multiclasses.
...
llvm-svn: 222670
2014-11-24 18:04:42 +00:00
3b3197ef95
[Hexagon] Adding aslh instruction.
...
llvm-svn: 222668
2014-11-24 17:44:19 +00:00
098256c5e6
[Hexagon] Adding zxth instruction.
...
llvm-svn: 222662
2014-11-24 17:11:34 +00:00
bb7d6f5514
[Hexagon] Adding zxtb instruction.
...
llvm-svn: 222660
2014-11-24 16:48:43 +00:00
310991c66f
[Hexagon] Adding sxth instruction.
...
llvm-svn: 222577
2014-11-21 21:54:59 +00:00
91ffec908f
[Hexagon] Adding sxtb instruction. Renaming some identically named classes that will be removed after converting referencing defs.
...
llvm-svn: 222575
2014-11-21 21:35:52 +00:00
e88447d8de
[Hexagon] Removing SUB_rr and replacing with A2_sub.
...
llvm-svn: 222571
2014-11-21 21:19:18 +00:00
ac00643603
[Hexagon] Adding A2_xor instruction with IR selection pattern and test.
...
llvm-svn: 222399
2014-11-19 23:22:23 +00:00
21866546ae
[Hexagon] Adding A2_or instruction with IR selection pattern and test.
...
llvm-svn: 222396
2014-11-19 22:58:04 +00:00
44fd1c8bdf
[Hexagon] Adding A2_and instruction.
...
llvm-svn: 222274
2014-11-18 22:45:47 +00:00
38765e6d89
[Hexagon] Adding A2_sub instruction
...
Renaming test files.
llvm-svn: 222263
2014-11-18 21:51:51 +00:00
efa74e0280
[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
...
Adding test to show correct instruction selection and encoding.
llvm-svn: 222249
2014-11-18 20:28:11 +00:00
5241881bbc
[Hexagon] Reverting 220584 to address ASAN errors.
...
llvm-svn: 221210
2014-11-04 00:14:36 +00:00
838307b31f
[Hexagon] Resubmission of 220427
...
Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst.
Adding encoding bits for add opcode.
Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220584
2014-10-24 19:00:32 +00:00
504bbf91cd
Revert r220427, "[Hexagon] Adding encoding bits for add opcode."
...
It brought cyclic dependecy between HexagonAsmPrinter and HexagonDesc.
llvm-svn: 220478
2014-10-23 11:31:22 +00:00
73a51a1a68
[Hexagon] Adding encoding bits for add opcode.
...
Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220427
2014-10-22 20:58:35 +00:00
88ebb9e2da
[Hexagon] Adding basic disassembler.
...
Marking all instructions as CodeGenOnly since encoding bits are not set yet.
http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc
llvm-svn: 220393
2014-10-22 16:49:14 +00:00
f98a1eca6e
[Hexagon] Add New TSFlags to be used in the upcoming patches.
...
llvm-svn: 208239
2014-05-07 19:07:34 +00:00
803e506fec
Hexagon: Pass to replace tranfer/copy instructions into combine instruction
...
where possible.
llvm-svn: 181817
2013-05-14 18:54:06 +00:00
a03eb9b5d5
Hexagon: Set accessSize and addrMode on all load/store instructions.
...
llvm-svn: 181324
2013-05-07 15:06:29 +00:00
7dda912cd7
Hexagon - Add peephole optimizations for zero extends.
...
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
sequence of a pair of i32->i64 extensions followed by a "bitwise or"
into COMBINE_rr.
* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
* test/CodeGen/Hexagon/union-1.ll: New test.
* test/CodeGen/Hexagon/combine_ir.ll: Fix test.
llvm-svn: 180946
2013-05-02 20:22:51 +00:00
5ed5181178
Hexagon: Use multiclass for Jump instructions.
...
llvm-svn: 180885
2013-05-01 21:37:34 +00:00
af2359b98c
Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.
...
llvm-svn: 180145
2013-04-23 21:17:40 +00:00
89c84821ea
Hexagon: Remove assembler mapped instruction definitions.
...
llvm-svn: 180133
2013-04-23 19:15:55 +00:00
ce1be1130f
Hexagon: Set isPredicatedNew flag on predicate new instructions.
...
llvm-svn: 179388
2013-04-12 18:01:06 +00:00
bea8327fcb
Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication.
...
llvm-svn: 179387
2013-04-12 17:46:52 +00:00
a46059b74d
Hexagon: Replace switch-case in isDotNewInst with TSFlags.
...
llvm-svn: 178281
2013-03-28 19:44:04 +00:00
93e740485f
Hexagon: Use multiclass for gp-relative instructions.
...
Remove noV4T gp-relative instructions.
llvm-svn: 178246
2013-03-28 16:25:57 +00:00
15957b129f
Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
...
llvm-svn: 178032
2013-03-26 15:43:57 +00:00
7825e064b9
Hexagon: Add patterns for zero extended loads from i1->i64.
...
llvm-svn: 176689
2013-03-08 14:15:15 +00:00
2ba0c0b927
Hexagon: Add support to lower block address.
...
llvm-svn: 176637
2013-03-07 19:10:28 +00:00
457801f7ab
reverting patch 176508.
...
llvm-svn: 176513
2013-03-05 20:29:23 +00:00
7179e712dd
Hexagon: Add support for lowering block address.
...
llvm-svn: 176508
2013-03-05 19:37:46 +00:00
f4e324f4fb
Hexagon: Add encoding bits to the TFR64 instructions.
...
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.
llvm-svn: 176499
2013-03-05 18:42:28 +00:00
de722193e5
Hexagon: Change insn class to support instruction encoding.
...
This patch doesn't introduce any functionality changes.
It adds some new fields to the Hexagon instruction classes and
changes their layout to support instruction encoding.
llvm-svn: 175205
2013-02-14 19:57:17 +00:00
0af477c3b1
Move MRI liveouts to Hexagon return instructions.
...
llvm-svn: 174407
2013-02-05 18:08:43 +00:00
7ab68fbd1d
Hexagon: Add V4 combine instructions and some more Def Pats for V2.
...
llvm-svn: 174331
2013-02-04 15:52:56 +00:00
b16a9cb132
Use multiclass for post-increment store instructions.
...
llvm-svn: 173816
2013-01-29 18:42:41 +00:00
a609b1c89d
Add constant extender support for MInst type instructions.
...
llvm-svn: 173813
2013-01-29 18:18:50 +00:00
ae65212a4b
Remove more unnecessary # operators with nothing to paste proceeding them.
...
llvm-svn: 171702
2013-01-07 06:14:20 +00:00
a8c5ec09c7
Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side.
...
llvm-svn: 171697
2013-01-07 05:45:56 +00:00
56605448f2
Add constant extender support to GP-relative load/store instructions.
...
llvm-svn: 170672
2012-12-20 06:52:46 +00:00
dfd779e108
Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros)
...
instructions.
llvm-svn: 169287
2012-12-04 18:05:01 +00:00
22d61dd4ce
Add constant extender support to ALU32 instructions for V2.
...
llvm-svn: 169284
2012-12-04 17:12:00 +00:00
5929cfc534
Move all operand definitions into HexagonOperands.td
...
llvm-svn: 169213
2012-12-04 05:00:31 +00:00
efe4f559b1
Move generic Hexagon subtarget information into Hexagon.td
...
llvm-svn: 169212
2012-12-04 04:29:16 +00:00
6f3bd03e50
Define store instructions with base+immediate offset addressing mode
...
using multiclass.
llvm-svn: 169168
2012-12-03 22:26:28 +00:00
4d8686cc42
Define load instructions with base+immediate offset addressing mode
...
using multiclass.
llvm-svn: 169153
2012-12-03 21:13:13 +00:00
a77c054e85
Use multiclass for the load instructions with MEMri operand.
...
llvm-svn: 169018
2012-11-30 17:31:52 +00:00
b950ea61fc
Use multiclass for the store instructions with MEMri operand.
...
llvm-svn: 168983
2012-11-30 06:10:22 +00:00
e95559fc16
Use multiclass for 'transfer' instructions.
...
llvm-svn: 168929
2012-11-29 19:35:44 +00:00
6c0a3550c8
Renamed HexagonImmediates.td -> HexagonOperands.td.
...
llvm-svn: 168434
2012-11-21 16:28:18 +00:00
6649360860
Added multiclass for post-increment load instructions.
...
llvm-svn: 167974
2012-11-14 20:38:48 +00:00
ccfd77ef90
Test commit.
...
Add a blank line.
llvm-svn: 167819
2012-11-13 06:31:55 +00:00
34b601804e
Use the relationship models infrastructure to add two relations - getPredOpcode
...
and getPredNewOpcode. The first relates non predicated instructions with their
predicated forms and the second relates predicated instructions with their
predicate-new forms.
Patch by Jyotsna Verma!
llvm-svn: 167243
2012-11-01 19:13:23 +00:00
0bb7f23cfc
[Hexagon] Don't mark callee saved registers as clobbered by a tail call
...
This was causing unnecessary spills/restores of callee saved registers.
Fixes PR13572.
Patch by Pranav Bhandarkar!
llvm-svn: 161778
2012-08-13 19:54:01 +00:00
ed6c0408fa
Remove variable_ops from call instructions in most targets.
...
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.
llvm-svn: 160189
2012-07-13 20:44:29 +00:00
bde9176663
Fix typos found by http://github.com/lyda/misspell-check
...
llvm-svn: 157885
2012-06-02 10:20:22 +00:00
f6b687e5d1
Revert 156634 upon request until code improvement changes are made.
...
llvm-svn: 156775
2012-05-14 19:35:42 +00:00
31f8723ef3
Hexagon constant extender support.
...
Patch by Jyotsna Verma.
llvm-svn: 156634
2012-05-11 19:56:59 +00:00
69295b8963
Hexagon V5 FP Support.
...
llvm-svn: 156568
2012-05-10 20:20:25 +00:00
c92c31674e
Extensions of Hexagon V4 instructions.
...
This adds new instructions for Hexagon V4 architecture.
llvm-svn: 156071
2012-05-03 16:18:50 +00:00
3c3bb55a85
Revert r155365, r155366, and r155367. All three of these have regression
...
test suite failures. The failures occur at each stage, and only get
worse, so I'm reverting all of them.
Please resubmit these patches, one at a time, after verifying that the
regression test suite passes. Never submit a patch without running the
regression test suite.
llvm-svn: 155372
2012-04-23 18:25:57 +00:00
a3f8ba2439
Hexagon V5 (floating point) support.
...
llvm-svn: 155367
2012-04-23 17:49:40 +00:00
2c7bf00fba
Support for Hexagon architectural feature, new value jump.
...
llvm-svn: 155366
2012-04-23 17:49:28 +00:00
6cd2251598
Support for Hexagon VLIW Packetizer.
...
llvm-svn: 155365
2012-04-23 17:49:20 +00:00
b415bf98f0
This reverts a long string of commits to the Hexagon backend. These
...
commits have had several major issues pointed out in review, and those
issues are not being addressed in a timely fashion. Furthermore, this
was all committed leading up to the v3.1 branch, and we don't need piles
of code with outstanding issues in the branch.
It is possible that not all of these commits were necessary to revert to
get us back to a green state, but I'm going to let the Hexagon
maintainer sort that out. They can recommit, in order, after addressing
the feedback.
Reverted commits, with some notes:
Primary commit r154616: HexagonPacketizer
- There are lots of review comments here. This is the primary reason
for reverting. In particular, it introduced large amount of warnings
due to a bad construct in tablegen.
- Follow-up commits that should be folded back into this when
reposting:
- r154622: CMake fixes
- r154660: Fix numerous build warnings in release builds.
- Please don't resubmit this until the three commits above are
included, and the issues in review addressed.
Primary commit r154695: Pass to replace transfer/copy ...
- Reverted to minimize merge conflicts. I'm not aware of specific
issues with this patch.
Primary commit r154703: New Value Jump.
- Primarily reverted due to merge conflicts.
- Follow-up commits that should be folded back into this when
reposting:
- r154703: Remove iostream usage
- r154758: Fix CMake builds
- r154759: Fix build warnings in release builds
- Please incorporate these fixes and and review feedback before
resubmitting.
Primary commit r154829: Hexagon V5 (floating point) support.
- Primarily reverted due to merge conflicts.
- Follow-up commits that should be folded back into this when
reposting:
- r154841: Remove unused variable (fixing build warnings)
There are also accompanying Clang commits that will be reverted for
consistency.
llvm-svn: 155047
2012-04-18 21:31:19 +00:00
96e8ee17e0
Hexagon V5 (Floating Point) Support.
...
llvm-svn: 154829
2012-04-16 17:05:06 +00:00
0e6e36d1d0
Add support for Hexagon Architectural feature, New Value Jump.
...
llvm-svn: 154696
2012-04-13 20:22:31 +00:00
a8071a0f88
Pass to replace tranfer/copy instructions into combine instruction where possible.
...
llvm-svn: 154695
2012-04-13 20:22:19 +00:00
b486144c12
HexagonPacketizer patch.
...
llvm-svn: 154616
2012-04-12 21:06:38 +00:00
5cee621c88
Hexagon: enable assembler output through the MC layer.
...
llvm-svn: 154597
2012-04-12 17:55:53 +00:00
2a783d5b94
Efficient pattern for store truncate. Patch by Evandro Menezes.
...
llvm-svn: 151166
2012-02-22 16:45:10 +00:00
30804c24ca
Optimize redundant sign extends and negation of predicates.
...
llvm-svn: 150606
2012-02-15 18:52:27 +00:00
d9811eb7be
Revert "Optimize redundant sign extends and negation of predicates"
...
as it's breaking the build.
This reverts commit 11241abca5e2a313412fed594bb9d9fa2a2057fb.
llvm-svn: 150604
2012-02-15 18:32:25 +00:00
4736aee81e
Optimize redundant sign extends and negation of predicates
...
llvm-svn: 150601
2012-02-15 18:22:18 +00:00
6f35837048
Use TSFlag bit to describe instruction properties.
...
Creating the isPredicated TSFlag enables the code
to use the property defined in the instruction format
instead of using a large switch statement.
llvm-svn: 150078
2012-02-08 18:25:47 +00:00
1213a7a57f
Hexagon backend support
...
llvm-svn: 146412
2011-12-12 21:14:40 +00:00
Colin LeMahieu