Commit Graph

47899 Commits

Author SHA1 Message Date
Andrew Trick efe2b1963d indvars -disable-iv-rewrite: just because SCEV ignores casts doesn't
mean they can be removed.

llvm-svn: 134054
2011-06-29 03:13:40 +00:00
Jakob Stoklund Olesen 8628435c06 Revert r134047 while investigating a llvm-gcc-i386-linux-selfhost
miscompile.

llvm-svn: 134053
2011-06-29 02:03:36 +00:00
Evan Cheng 8264e272a9 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
llvm-svn: 134049
2011-06-29 01:14:12 +00:00
Jakob Stoklund Olesen ffbc05b715 Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art.
This function has to deal with a lot of special cases, and the old
version got it wrong sometimes. In particular, it would sometimes leave
multiple uses in the stack interval in a single block. That causes bad
code with multiple reloads in the same basic block.

The new version handles block entry and exit in a single pass. It first
eliminates all the easy cases, and then goes on to create a local
interval for the blocks with difficult interference. Previously, we
would only create the local interval for completely isolated blocks.

It can happen that the stack interval becomes completely empty because
we could allocate a register in all edge bundles, and the new local
intervals deal with the interference. The empty stack interval is
harmless, but we need to remove a SplitKit assertion that checks for
empty intervals.

llvm-svn: 134047
2011-06-29 00:24:24 +00:00
Evan Cheng 194c3dc01f Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
llvm-svn: 134030
2011-06-28 21:14:33 +00:00
Evan Cheng 0beca53a29 Hide more details in tablegen generated MCRegisterInfo ctor function.
llvm-svn: 134027
2011-06-28 20:44:22 +00:00
Evan Cheng df8974ef2f Add MCInstrInfo registeration machinery.
llvm-svn: 134026
2011-06-28 20:29:03 +00:00
Evan Cheng 1e210d08d8 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
llvm-svn: 134024
2011-06-28 20:07:07 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Jakob Stoklund Olesen 7297e7e223 Clean up the handling of the x87 fp stack to make it more robust.
Drop the FpMov instructions, use plain COPY instead.

Drop the FpSET/GET instruction for accessing fixed stack positions.
Instead use normal COPY to/from ST registers around inline assembly, and
provide a single new FpPOP_RETVAL instruction that can access the return
value(s) from a call. This is still necessary since you cannot tell from
the CALL instruction alone if it returns anything on the FP stack. Teach
fast isel to use this.

This provides a much more robust way of handling fixed stack registers -
we can tolerate arbitrary FP stack instructions inserted around calls
and inline assembly. Live range splitting could sometimes break x87 code
by inserting spill code in unfortunate places.

As a bonus we handle floating point inline assembly correctly now.

llvm-svn: 134018
2011-06-28 18:32:28 +00:00
Chad Rosier 6b610b387d Remove warning: 'c0' may be used uninitialized in this function.
llvm-svn: 134014
2011-06-28 17:26:57 +00:00
Jakob Stoklund Olesen a1dceb0e3c Print registers by name instead of by number.
llvm-svn: 134013
2011-06-28 17:24:32 +00:00
Andrew Trick 4426f5b388 cleanup: misleading comment.
llvm-svn: 134010
2011-06-28 16:45:04 +00:00
Roman Divacky 4394e68c24 Implement ISD::VAARG lowering on PPC32.
llvm-svn: 134005
2011-06-28 15:30:42 +00:00
Jay Foad 2a31eb49c7 PR10210: New method ConstantArray::getAsCString(). Use it in LTO to
avoid getting embedded trailing null bytes in std::strings.

llvm-svn: 133999
2011-06-28 08:24:19 +00:00
Andrew Trick 154d78a661 Cleanup. Fix a stupid variable name.
llvm-svn: 133995
2011-06-28 05:41:52 +00:00
Andrew Trick 411daa5e81 SCEVExpander: give new insts a name that identifies the reponsible pass.
llvm-svn: 133992
2011-06-28 05:07:32 +00:00
Andrew Trick 60ab3efb3e whitespace
llvm-svn: 133991
2011-06-28 05:04:16 +00:00
Nick Lewycky fa44dc6509 Fix typo in comment.
llvm-svn: 133990
2011-06-28 03:57:31 +00:00
Rafael Espindola 09932bd5b6 Fix cmake build.
llvm-svn: 133989
2011-06-28 03:17:03 +00:00
Andrew Trick 56b315a9cf indvars --disable-iv-rewrite: sever ties with IVUsers.
llvm-svn: 133988
2011-06-28 03:01:46 +00:00
Andrew Trick 8a3c39c737 indvars --disable-iv-rewrite: Defer evaluating s/zext until SCEV
evaluates all other IV exprs.

llvm-svn: 133982
2011-06-28 02:49:20 +00:00
Chandler Carruth 137c7ead2e Fix CMake build by removing this now dead file.
llvm-svn: 133981
2011-06-28 02:03:12 +00:00
Jakob Stoklund Olesen 040d659206 Fix a bad iterator dereference that Evan uncovered.
llvm-svn: 133978
2011-06-28 01:18:58 +00:00
Jim Grosbach 16896325a6 ARM Thumb2 asm syntax optional destination operand for binary operators.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff

rdar://9672867

llvm-svn: 133973
2011-06-28 00:19:13 +00:00
Evan Cheng 21afabe73d Remove RegClass2VRegMap from MachineRegisterInfo.
llvm-svn: 133967
2011-06-27 23:54:40 +00:00
Jim Grosbach a6f7a1efcc ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.

llvm-svn: 133966
2011-06-27 23:54:06 +00:00
Evan Cheng b7d00313dc Remove the experimental (and unused) pre-ra splitting pass. Greedy regalloc can split live ranges.
llvm-svn: 133962
2011-06-27 23:40:45 +00:00
Andrew Trick 163b4a70fb indvars -disable-iv-rewrite: run RLEV after SimplifyIVUsers for
a bit more control over the order SCEVs are evaluated.

llvm-svn: 133959
2011-06-27 23:17:44 +00:00
Devang Patel 4dc034df1d During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
llvm-svn: 133953
2011-06-27 22:32:04 +00:00
Jakub Staszak 423651e46a Calculate GetBestDestForJumpOnUndef correctly.
llvm-svn: 133946
2011-06-27 21:51:12 +00:00
Jim Grosbach 1a13cd77f1 ARM Asm parsing of Thumb2 move immediate.
Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet)
encode the instruction properly, but this gets the parsing part.

llvm-svn: 133945
2011-06-27 21:38:03 +00:00
Evan Cheng 8d71a75777 More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
llvm-svn: 133944
2011-06-27 21:26:13 +00:00
Jim Grosbach 0ceb5473a3 Add exception necessitated by 133938.
llvm-svn: 133939
2011-06-27 20:59:10 +00:00
Jim Grosbach 07d9027088 ARM assembly carry set/clear condition code aliases for 'hi/lo'
llvm-svn: 133938
2011-06-27 20:40:29 +00:00
Jim Grosbach 89bbfc434a ARM assembler support for ldmfd/stmfd mnemonics.
llvm-svn: 133936
2011-06-27 20:32:18 +00:00
Jim Grosbach 29882a75eb ARM assembler support for vpush/vpop.
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231

llvm-svn: 133932
2011-06-27 20:00:07 +00:00
Jim Grosbach b5ee311602 ARM Assembly syntax support for arithmetic implied dest operand.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
  sub r2, r2, #6
  sub r2, #6

rdar://9682597

llvm-svn: 133925
2011-06-27 19:09:15 +00:00
Owen Anderson b0a5a1ee29 The index stored in the RegDefIter is one after the current index. When getting the index, decrement it so that it points to the current element. Fixes an off-by-one bug encountered when trying to make use of MVT::untyped.
llvm-svn: 133923
2011-06-27 18:34:12 +00:00
Evan Cheng d9997acd14 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.

llvm-svn: 133922
2011-06-27 18:32:37 +00:00
Andrew Trick 31f25bc66f pre-RA-sched: Cleanup register pressure tracking.
Removed the check that peeks past EXTRA_SUBREG, which I don't think
makes sense any more. Intead treat it as a normal register def. No
significant affect on x86 or ARM benchmarks.

llvm-svn: 133917
2011-06-27 18:01:20 +00:00
Jakob Stoklund Olesen 79f1b714a2 Track live-out physical registers in MachineDCE.
Patch by Sanjoy Das!

llvm-svn: 133910
2011-06-27 15:00:36 +00:00
Nick Lewycky a61df3f843 Teach one piece of scalarrepl to handle lifetime markers. When transforming an
alloca that only holds a copy of a global and we're going to replace the users
of the alloca with that global, just nuke the lifetime intrinsics. Part of
PR10121.

llvm-svn: 133905
2011-06-27 05:40:02 +00:00
Nick Lewycky 3e334a42d7 Move onlyUsedByLifetimeMarkers to ValueTracking so that it can be used by other
passes as well.

llvm-svn: 133904
2011-06-27 04:20:45 +00:00
Jakob Stoklund Olesen ff653a2eed Grow the X86FloatingPoint register map to hold 16 registers.
This allows for more live scratch registers which is needed to handle
live ST registers before return and inline asm instructions.

llvm-svn: 133903
2011-06-27 04:08:36 +00:00
Jakob Stoklund Olesen 537a302d1a Distinguish early clobber output operands from clobbered registers.
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.

This will pop a register off the stack:

  asm("fstp %st" : : "t"(x) : "st");

While this will pop the input and push an output:

  asm("fst %st" : "=&t"(r) : "t"(x));

We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.

llvm-svn: 133902
2011-06-27 04:08:33 +00:00
Jakob Stoklund Olesen 6b356b18b4 Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:

  INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>

llvm-svn: 133901
2011-06-27 04:08:29 +00:00
Rafael Espindola 2cf9489cf6 Remove unused methods.
llvm-svn: 133900
2011-06-26 22:44:34 +00:00
Rafael Espindola 676c405acb There is only one register coalescer. Merge it into the base class and
remove the analysis group.

llvm-svn: 133899
2011-06-26 22:34:10 +00:00
Rafael Espindola ea1a9c342d Merge SimpleRegisterCoalescing.cpp into RegisterCoalescer.cpp.
llvm-svn: 133897
2011-06-26 22:06:36 +00:00