Commit Graph

541 Commits

Author SHA1 Message Date
Matheus Almeida 595fcab2d0 [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier).
Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4019

llvm-svn: 210654
2014-06-11 15:05:56 +00:00
Zoran Jovanovic 2855142ac5 [mips][mips64r6] Add LDPC instruction
Differential Revision: http://reviews.llvm.org/D3822

llvm-svn: 210460
2014-06-09 09:49:51 +00:00
Daniel Sanders 8966caab05 [mips][mips64r6] t(eq|ge|lt|ne)i and t(ge|lt)iu are not available in MIPS32r6/MIPS64r6
Summary: Depends on D3872

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3891

llvm-svn: 209513
2014-05-23 13:24:08 +00:00
Daniel Sanders ac27263512 [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6
Summary:
Instead the system is required to provide some means of handling unaligned
load/store without special instructions. Options include full hardware
support, full trap-and-emulate, and hybrids such as hardware support within
a cache line and trap-and-emulate for multi-line accesses.

MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to
assume that unaligned accesses are 'fast' on the basis that I expect few
hardware implementations will opt for pure-software handling of unaligned
accesses. The ones that do handle it purely in software can override this.

mips64-load-store-left-right.ll has been merged into load-store-left-right.ll

The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has
been fixed and the variables renamed to clarify the units they hold.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3872

llvm-svn: 209512
2014-05-23 13:18:02 +00:00
Daniel Sanders 36ff7c2adc [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6
Summary: Depends on D3787. Tablegen will raise an assertion without it.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3842

llvm-svn: 209419
2014-05-22 11:42:31 +00:00
Tim Northover fe6591ed77 Mips: don't print subu alias for addiu
Certainly not without having a custom PrintMethod to invert the immediate
beforehand. But probably not at all.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208964
2014-05-16 09:41:30 +00:00
Daniel Sanders 01124a0132 [mips][mips64r6] Add align and dalign
Summary: Depends on D3689

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3728

llvm-svn: 208872
2014-05-15 12:06:36 +00:00
Daniel Sanders b59e1a41f4 [mips][mips64r6] Add addiupc, aluipc, and auipc
Summary:
No support for symbols in place of the immediate yet since it requires new
relocations.

Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3689

llvm-svn: 208858
2014-05-15 10:45:58 +00:00
Daniel Sanders 387fc15d2c [mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-3 that was available in MIPS32R2.

To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3696

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3697

llvm-svn: 208690
2014-05-13 11:45:36 +00:00
Daniel Sanders 579168629e [mips] Free up two values in SubtargetFeatureFlag by folding the redundant IsGP32/IsGP64 into IsGP32bit/IsGP64bit
Summary:
We are currently very close to the 32-bit limit of the current assembler
implementation. This is because there is no way to represent an instruction
that is available in, for example, Mips3 or Mips32. We have to define a
feature bit that represents this.

This patch cleans up a pair of redundant feature bits and slightly postpones the
point we will reach the limit.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3703

llvm-svn: 208685
2014-05-13 11:17:46 +00:00
Tim Northover ee20caaf82 TableGen: use PrintMethods to print more aliases
llvm-svn: 208607
2014-05-12 18:04:06 +00:00
Daniel Sanders 0ac5ec58b8 [mips][mips64r6] Added mul/mulu/muh/muhu
Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3668

llvm-svn: 208576
2014-05-12 15:12:45 +00:00
Daniel Sanders aadc357e5f [mips] Marked up instructions added in MIPS32 and tested that IAS for -mcpu=mips2 does not accept them
Summary:
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are explicitly tested.

Depends on D3695

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3696

llvm-svn: 208549
2014-05-12 13:04:32 +00:00
Daniel Sanders 07cdea2baa [mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-V that was available in MIPS32R2

Most of these instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now. It happens
because many of the MIPS V instructions have not been implemented.

Depends on D3694

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3695

llvm-svn: 208546
2014-05-12 12:52:44 +00:00
Daniel Sanders 070fd1c42a [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64
Summary:
DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no
effect on the CodeGen tests since expansion of i64 prevented their use
anyway.

The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as
well. This is not a functional change since DCLZ is still prohibited by
being a MIPS64 instruction (MIPS16 is only compatible with MIPS32).

No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3694

llvm-svn: 208544
2014-05-12 12:41:59 +00:00
Daniel Sanders fcea8102e8 [mips] Fold FeatureSEInReg into FeatureMips32r2
Summary: No functional change

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3693

llvm-svn: 208543
2014-05-12 12:28:15 +00:00
Daniel Sanders 39d0051847 [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2
Summary:
dsbh and dshd are not available on Mips32r2. No codegen test changes
required since expansion of i64 prevented the use of these instructions
anyway.

Depends on D3690

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3692

llvm-svn: 208542
2014-05-12 12:15:41 +00:00
Daniel Sanders 94eda2e1ab [mips] Replace FeatureFPIdx with FeatureMips4_32r2
Summary:
No functional change.

The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions)

Depends on D3677

Reviewers: rkotler, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3690

llvm-svn: 208541
2014-05-12 11:56:16 +00:00
Daniel Sanders e57d866ed0 [mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-IV that was available in MIPS32

A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.

Depends on D3676

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3677

llvm-svn: 208414
2014-05-09 14:06:17 +00:00
Daniel Sanders 395b8181ec [mips] Remove unused CondMov feature bit
Summary:
No functional change

Depends on D3675

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3676

llvm-svn: 208410
2014-05-09 13:15:07 +00:00
Daniel Sanders f2056bef32 [mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-III that was available in MIPS32

A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.

There's some obvious InstAlias's that ought to be marked MIPS-III but arent.
This is because they are not currently tested. I intend to catch these with
a final pass through the tablegen records to find tablegen records without
ISA annotations.

Depends on D3674

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3675

llvm-svn: 208408
2014-05-09 13:02:27 +00:00
Daniel Sanders b7f1c6ff3e [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6
Summary:
Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these
processors.

I've also included comments to describe removed and re-encoded instructions,
along with placeholder def's for the new instructions but there are no
functional changes to codegen at this point.

Reviewers: jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3622

llvm-svn: 208399
2014-05-09 09:46:21 +00:00
Daniel Sanders 52bdd651e5 [mips] Added missing dsra -> dsrav and sra -> srav aliases.
Summary: dsll, dsrl, sll, and srl already exist.

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3673

llvm-svn: 208397
2014-05-09 09:24:49 +00:00
Daniel Sanders 7d290b0974 [mips] Add PredicateControl to InstAlias's
Summary:
No functional change

Depends on D3649

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3672

llvm-svn: 208334
2014-05-08 16:12:31 +00:00
Daniel Sanders d39320c6b6 [mips] Marked up instructions added in MIPS-II and tested that IAS for -mcpu=mips1 does not accept them
Summary:
A small number of instructions are rejected with the wrong error message.
These have been placed in a separate test for now. There seems to be some
parsing quirk that triggers when these instructions are disabled.

Depends on D3571

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3647

llvm-svn: 208305
2014-05-08 12:40:48 +00:00
Daniel Sanders 8dcb116a3e [mips] Implement tlbp, tlbr, tlbwi, and tlbwr
Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3571

llvm-svn: 208301
2014-05-08 11:51:18 +00:00
Daniel Sanders 5b864d0cbb [mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates
Summary:
No functional change (confirmed by diffing tablegen-erated files).

Depends on D3642

Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3645

llvm-svn: 208213
2014-05-07 14:25:43 +00:00
Daniel Sanders 3872b47231 [mips] Add INSN_<name> adverbs and start using them instead of AdditionalPredicates overrides
Summary:
No functional change

Depends on D3641

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3642

llvm-svn: 208212
2014-05-07 14:11:46 +00:00
Daniel Sanders 9c1b1bec03 [mips] Add ISA_<name> adverbs and start using them instead of AdditionalPredicates overrides
Summary:
One small functional change. The recently added PAUSE instruction now has
the HasStdEnc predicate which was accidentally removed by a Requires<>.

Depends on D3640

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3641

llvm-svn: 208209
2014-05-07 13:57:22 +00:00
Daniel Sanders 3dc2c016a6 [mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
The overall idea is to chop the Predicates list into subsets that are
usually overridden independently. This allows subclasses to partially
override the predicates of their superclasses without having to re-add all
the existing predicates.

This patch starts the process by moving HasStdEnc into a new
EncodingPredicates list and almost everything else into
AdditionalPredicates.

It has revealed a couple likely bugs where 'let Predicates' has removed
the HasStdEnc predicate.

No functional change (confirmed by diffing tablegen-erated files).

Depends on D3549, D3506

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3550

llvm-svn: 208184
2014-05-07 10:27:09 +00:00
Daniel Sanders 0e2364149c [mips] Move HasStdEnc to the front of the predicates lists.
Summary:
This will make it easier to prove that a more complicated change in the
following commit is non-functional.

No functional change.

Depends on D3506

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3549

llvm-svn: 208179
2014-05-07 09:58:05 +00:00
Daniel Sanders 88fbbcaa30 [mips] Removed two-operand alias for sllv, sr[al]v, rotrv, dsllv, dsr[al]v, and drotrv
GAS doesn't actually accept these particular cases.

The mnemonic without the trailing 'v' still supports two-operand aliases.

llvm-svn: 207740
2014-05-01 10:08:36 +00:00
Matheus Almeida e844872830 [mips] Add instruction alias (negu).
Summary: negu $reg is equivalent to negu $reg, $reg.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3510

llvm-svn: 207673
2014-04-30 16:53:49 +00:00
Matheus Almeida b7be52343d [mips] Add instruction alias (sltu).
Summary:
The pattern sltu $r1, $r2, $imm is found in handwritten assembly which
is just a shorthand version of sltui $r1, $r2, $imm.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3508

llvm-svn: 207671
2014-04-30 16:29:56 +00:00
Matheus Almeida 312ac02491 [mips] Add instruction alias (sll and srl).
Summary:
The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of sllv/srlv $rd, $rt, $rs.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3483

llvm-svn: 207657
2014-04-30 15:23:04 +00:00
Sasa Stankovic 7b061a42b1 [mips] Fix MipsLongBranch pass to work when the offset from the branch to the
target cannot be determined accurately. This is the case for NaCl where the
sandboxing instructions are added in MC layer, after the MipsLongBranch pass.
It is also the case when the code has inline assembly. Instead of calculating
offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2)
expressions that are resolved during the fixup.

This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll
and implements microMIPS CHECKs in a much simpler way in a file
test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64.

llvm-svn: 207656
2014-04-30 15:06:25 +00:00
Daniel Sanders f562582d15 [mips] Remove redundant 'let Predicates = [HasStdEnc]' statements
Summary:
The MipsPat class already initializes Predicates to [HasStdEnc].

No functional change (confirmed by diffing tablegen-erated files before and
after)

Differential Revision: http://reviews.llvm.org/D3546

llvm-svn: 207548
2014-04-29 16:24:10 +00:00
Matheus Almeida 483d7e9349 [mips] Use TwoOperandAliasConstraint for shift instructions.
This enables TableGen to generate an additional two operand
matcher for our shift_rotate_imm and shift_rotate_reg class of instructions.

The tests were also updated so that they include now encoding information
for all affected instructions.

llvm-svn: 206398
2014-04-16 16:28:59 +00:00
Vladimir Medic 16d671a413 Current definition of subtract with immediate instruction aliases uses CodeGenOnly defined instructions and post matcher expansion methods to emit real instructions add with immediate. However, they can directly alias add with immediate instruction and remove unnecessary definitions and code in MipsAsmParser.cpp. This patch makes no change in functionality, just removes unnecessary definitions and code.
llvm-svn: 206272
2014-04-15 10:14:49 +00:00
Daniel Sanders 3d84935d28 [mips] Fix more incorrect uses of HasMips64 and isMips64()
Summary:
- Conditional moves acting on 64-bit GPR's should require MIPS-IV rather than MIPS64
- ISD::MUL, and ISD::MULH[US] should be lowered on all 64-bit ISA's

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

I've added additional testcases to cover as much of the codegen changes
affecting MIPS-IV as I can. Where I've been unable to find an existing
MIPS64 testcase that can be re-used for MIPS-IV (mainly tests covering
ISD::GlobalAddress and similar), I at least agree that MIPS-IV should
behave like MIPS64. Further testcases that are fixed by this patch will follow
in my next commit. The testcases from that commit that fail for MIPS-IV without
this patch are:
    LLVM :: CodeGen/Mips/2010-07-20-Switch.ll
    LLVM :: CodeGen/Mips/cmov.ll
    LLVM :: CodeGen/Mips/eh-dwarf-cfa.ll
    LLVM :: CodeGen/Mips/largeimmprinting.ll
    LLVM :: CodeGen/Mips/longbranch.ll
    LLVM :: CodeGen/Mips/mips64-f128.ll
    LLVM :: CodeGen/Mips/mips64directive.ll
    LLVM :: CodeGen/Mips/mips64ext.ll
    LLVM :: CodeGen/Mips/mips64fpldst.ll
    LLVM :: CodeGen/Mips/mips64intldst.ll
    LLVM :: CodeGen/Mips/mips64load-store-left-right.ll
    LLVM :: CodeGen/Mips/sint-fp-store_pattern.ll

Reviewers: dsanders

Reviewed By: dsanders

CC: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3343

llvm-svn: 206183
2014-04-14 15:44:42 +00:00
Daniel Sanders 77277ea501 [mips] NotMips64 predicate is really a test for 32-bit GPR's.
Summary:
Similarly, the HasMips64 on the 64-bit move InstAlias is a test for 64-bit
GPR's.

No functional change.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3263

llvm-svn: 205968
2014-04-10 15:00:28 +00:00
Daniel Sanders b282f1fec5 Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math
Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies).

nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008.

Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3274

llvm-svn: 205844
2014-04-09 09:56:43 +00:00
Reed Kotler 735da8e015 Reverting commit r205628 due to mips64 issues.
llvm-svn: 205741
2014-04-07 22:11:40 +00:00
Daniel Sanders d4341a0ad7 [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math
Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the
processor which are used to select between the 1985 and 2008 versions of IEEE
754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid
operation exceptions when given NaN), in 2008 mode they are non-arithmetic
(i.e. they are copies).

nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because
the ISA spec does not explicitly state that they obey Has2008 and ABS2008.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3274

llvm-svn: 205628
2014-04-04 14:52:54 +00:00
Daniel Sanders 442f1a12f1 [mips] Implement ehb, ssnop, and pause in assembler
Summary: Add negative tests for pause

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3246

llvm-svn: 205537
2014-04-03 13:21:51 +00:00
Zoran Jovanovic cabf0f41e0 Implementation of 16-bit microMIPS instructions MFHI and MFLO.
Differential Revision: http://llvm-reviews.chandlerc.com/D3141

llvm-svn: 205532
2014-04-03 12:47:34 +00:00
Daniel Sanders b50ccf8e26 [mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

llvm-svn: 205292
2014-04-01 10:35:28 +00:00
Daniel Sanders e34a120285 Revert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot errors in lld tests.
It's currently unable to parse 'sym + imm' without surrounding parenthesis.

llvm-svn: 205237
2014-03-31 18:51:43 +00:00
Daniel Sanders 0c648ba5be [mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

llvm-svn: 205229
2014-03-31 17:43:46 +00:00
Zoran Jovanovic 9b05a31f76 Fixed issue with microMIPS JAL instruction.
Differential Revision: http://llvm-reviews.chandlerc.com/D3200

llvm-svn: 205185
2014-03-31 14:00:10 +00:00
Matheus Almeida ea06727f03 [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.
This enables TableGen to generate an additional two operand matcher
for our ArithLogicR class of instructions (constituted by 3 register operands).
E.g.: and $1, $2 <=> and $1, $1, $2

llvm-svn: 204826
2014-03-26 16:09:43 +00:00
Kai Nacke 93fe5e810d [MIPS] Add cpu octeon and some instructions
The Octeon cpu from Cavium Networks is mips64r2 based and has an extended
instruction set. In order to utilize this with LLVM, a new cpu feature "octeon"
and a subtarget feature "cnmips" is added. A small set of new instructions
(baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and
dpop instructions with option -mcpu=octeon or -mattr=+cnmips.

llvm-svn: 204337
2014-03-20 11:51:58 +00:00
Zoran Jovanovic a0f5328984 Provide an operand for microMIPS wait instruction.
llvm-svn: 204329
2014-03-20 10:41:37 +00:00
Zoran Jovanovic 87d13e5ec1 Implementation of microMIPS 16-bit instructions MOVE and JALR.
Differential Revision: http://llvm-reviews.chandlerc.com/D3112

llvm-svn: 204325
2014-03-20 10:18:24 +00:00
Daniel Sanders fa961d76f0 [mips] Prevent %lo relocation being used on MSA loads and stores.
Summary:
Parts of the compiler still believed MSA load/stores have a 16-bit offset when
it is actually 10-bit. Corrected this, and fixed a closely related issue this
uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS
respectively) could not load/store using offsets from the stack/frame pointer.
They accepted frameindex+offset, but not frameindex by itself.

Reviewers: jacksprat, matheusalmeida

Reviewed By: jacksprat

Differential Revision: http://llvm-reviews.chandlerc.com/D2888

llvm-svn: 202717
2014-03-03 14:31:21 +00:00
Vladimir Medic f9f8f4859a Fixing a build failure reported by certain buildbots. This will disable jalx instruction for micromips target.
llvm-svn: 202715
2014-03-03 14:05:14 +00:00
Vladimir Medic 43e978234a This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
llvm-svn: 202706
2014-03-03 13:12:59 +00:00
Daniel Sanders 4d4f3d98de [mips] Remove unused NotN64 predicate
llvm-svn: 201682
2014-02-19 15:16:47 +00:00
Petar Jovanovic 9725016af3 [mips] Add NaCl target and forbid indexed loads and stores for it
This patch adds NaCl target for Mips. It also forbids indexed loads and
stores if the target is NaCl.

Patch by Sasa Stankovic.

Differential Revision: http://llvm-reviews.chandlerc.com/D2690

llvm-svn: 200855
2014-02-05 17:19:30 +00:00
Daniel Sanders 37463f7259 [mips][sched] Split IIStore into II_S[BHWD], II_S[WD][LR], and II_SAVE
No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199876
2014-01-23 10:31:31 +00:00
Daniel Sanders 0b385ac138 [mips][sched] Split IILoad into II_L[BHWD], II_L[BHW]U, II_L[WD][LR], and II_RESTORE
No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199749
2014-01-21 15:21:14 +00:00
Daniel Sanders 298ad0f277 [mips][sched] Split IIslt into II_SLT_SLTU, II_SLTI_SLTIU
No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199719
2014-01-21 10:42:13 +00:00
Daniel Sanders c7a9f8d298 [mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU
No functional change since the InstrItinData's were duplicated

llvm-svn: 199497
2014-01-17 14:48:06 +00:00
Daniel Sanders e95a137b96 [mips][sched] Split IIImul and IIImult into subclasses.
IIImul -> II_MUL
IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU

No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199495
2014-01-17 14:32:41 +00:00
Daniel Sanders 9342557ea7 [mips][sched] Split IIHiLo into II_MFHI_MFLO and II_MTHI_MTLO
No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199493
2014-01-17 14:17:34 +00:00
Daniel Sanders 4d20f0c00f [mips][sched] Split IIseb into II_SEB and II_SEH
No functional change since there are no InstrItinData's.

llvm-svn: 199396
2014-01-16 16:19:38 +00:00
Daniel Sanders 306ef07b8d [mips][sched] Split IILogic into II_AND, II_OR, II_XOR, II_ANDI, II_ORI, II_XORI
This is necessary because the classes are shared between all implementations.

No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199394
2014-01-16 15:57:05 +00:00
Daniel Sanders 980589a803 [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
  II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
  II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
  II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
  II_SR[AL]V, II_SUBU, II_XOR

No functional change since the InstrItinData's have been duplicated.

This is necessary because the classes are shared between all schedulers.

Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.

llvm-svn: 199391
2014-01-16 14:27:20 +00:00
Zoran Jovanovic bd28c373c4 Support for microMIPS load effective address.
llvm-svn: 198010
2013-12-25 10:14:07 +00:00
Zoran Jovanovic ce02486d16 Support for microMIPS FPU instructions 1.
llvm-svn: 197815
2013-12-20 15:44:08 +00:00
Zoran Jovanovic 8e918c3c4d Support for microMIPS control instructions.
llvm-svn: 197696
2013-12-19 16:25:00 +00:00
Zoran Jovanovic ff9d5f3284 Support for microMIPS LL and SC instructions.
llvm-svn: 197692
2013-12-19 16:12:56 +00:00
Matheus Almeida 6b59c449d9 [mips][msa] Fix issue with immediate fields of LD/ST instructions
not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.

llvm-svn: 196494
2013-12-05 11:06:22 +00:00
Akira Hatanaka f6109e4ad7 [mips] Redefine TAILCALL as a pseudo instruction.
No functionality change.

llvm-svn: 195896
2013-11-27 23:58:32 +00:00
Zoran Jovanovic f4d4d789f7 Use instr mapping for microMIPS in llvm-mc.
llvm-svn: 194792
2013-11-15 08:07:34 +00:00
Zoran Jovanovic ccb70caa13 Support for microMIPS trap instruction with immediate operands.
llvm-svn: 194569
2013-11-13 13:15:03 +00:00
Zoran Jovanovic c18b6d1083 Support for microMIPS trap instructions 1.
llvm-svn: 194205
2013-11-07 14:35:24 +00:00
Zoran Jovanovic 8a80aa76c8 Support for microMIPS branch instructions.
llvm-svn: 193992
2013-11-04 14:53:22 +00:00
Zoran Jovanovic 507e084a18 Support for microMIPS jump instructions
llvm-svn: 193623
2013-10-29 16:38:59 +00:00
Reed Kotler 91ae9829a9 Make first substantial checkin of my port of ARM constant islands code to Mips.
Before I just ported the shell of the pass. I've tried to keep everything
nearly identical to the ARM version. I think it will be very easy to eventually
merge these two and create a new more general pass that other targets can
use. I have some improvements I would like to make to allow pools to 
be shared across functions and some other things. When I'm all done we
can think about making a more general pass. More to be ported but the
basic mechanism works now almost as good as gcc mips16.

llvm-svn: 193509
2013-10-27 21:57:36 +00:00
Akira Hatanaka 06aff571a3 [mips] Define a pseudo instruction which writes to both the lower and higher
parts of the accumulators and gets expanded post-RA.

llvm-svn: 192667
2013-10-15 01:48:30 +00:00
Akira Hatanaka ec67c90216 [mips] Use predicates to guard instructions using accumulator registers instead
of relying on AddedComplexity.

llvm-svn: 192665
2013-10-15 01:21:37 +00:00
Akira Hatanaka d98c99fd01 [mips] Rename isel nodes.
llvm-svn: 192663
2013-10-15 01:12:50 +00:00
Benjamin Kramer 8a37f63714 Mips: Disassemble sign-extended 64 bit immediates properly.
This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483
2013-10-11 19:05:08 +00:00
Akira Hatanaka 16048332f1 [mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.

llvm-svn: 192119
2013-10-07 18:49:46 +00:00
Vladimir Medic 2b953d0b39 This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
llvm-svn: 191734
2013-10-01 09:48:56 +00:00
Robert Wilhelm 2788d3ec99 Even more spelling fixes for "instruction".
llvm-svn: 191611
2013-09-28 13:42:22 +00:00
Akira Hatanaka ff1fbda4cd [mips] MUL should clobber HI0 and LO0.
I cannot think of a test case that reliably triggers this bug.

llvm-svn: 191109
2013-09-20 21:22:28 +00:00
Zoran Jovanovic fc26cfcde7 Fixed bug when generating Load Upper Immediate microMIPS instruction.
llvm-svn: 190746
2013-09-14 07:35:41 +00:00
Zoran Jovanovic 3671a5441a Support for microMIPS DIV instructions.
llvm-svn: 190745
2013-09-14 07:15:21 +00:00
Zoran Jovanovic ab85278137 Support for misc microMIPS instructions.
llvm-svn: 190744
2013-09-14 06:49:25 +00:00
Akira Hatanaka 3121353c99 [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
into a 5-bit or 6-bit field.

llvm-svn: 190226
2013-09-07 00:02:02 +00:00
Akira Hatanaka 79e38cde37 [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".
llvm-svn: 190224
2013-09-06 23:52:46 +00:00
Akira Hatanaka 50eebac68b [mips] Delete unused classes and defs.
llvm-svn: 190221
2013-09-06 23:42:58 +00:00
Akira Hatanaka 2c544d8ed5 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220
2013-09-06 23:40:15 +00:00
Akira Hatanaka dffc542123 [mips] Set instruction itineraries of loads, stores and conditional moves.
llvm-svn: 190219
2013-09-06 23:28:24 +00:00
Vladimir Medic b936da159e This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
llvm-svn: 190154
2013-09-06 13:08:00 +00:00
Vladimir Medic 457ba56b05 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
llvm-svn: 190152
2013-09-06 12:53:21 +00:00
Daniel Sanders e6ed5b72f1 [mips][msa] Added load/store intrinsics.
llvm-svn: 189476
2013-08-28 12:04:29 +00:00
Akira Hatanaka 9bfa2e2e7f [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates.

llvm-svn: 189432
2013-08-28 00:55:15 +00:00
Akira Hatanaka 37e9b0dbb2 [mips] Clean up definitions of move word from/to coprocessor instructions.
No functionality change.

llvm-svn: 189431
2013-08-28 00:42:50 +00:00
Daniel Sanders 70835f6025 [mips][msa] Added bitconverts for vector types for big and little-endian
llvm-svn: 189330
2013-08-27 09:40:30 +00:00
Vladimir Medic 8277c1874a This patch implements trap instructions for mips. The test cases are added.
llvm-svn: 189213
2013-08-26 10:02:40 +00:00
Akira Hatanaka 6781fc1648 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.

llvm-svn: 188830
2013-08-20 21:08:22 +00:00
Akira Hatanaka a43b56d9af [mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.

llvm-svn: 188824
2013-08-20 20:46:51 +00:00
Vladimir Medic 2df9ee6ec8 This patch implements wait instruction for mips. Examples are added in test files.
llvm-svn: 188537
2013-08-16 10:17:03 +00:00
Jack Carter babdcc8c2c [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders

llvm-svn: 188457
2013-08-15 12:24:57 +00:00
Akira Hatanaka 8002a3f6d8 [mips] Rename HIRegs and LORegs.
llvm-svn: 188341
2013-08-14 00:47:08 +00:00
Jack Carter 3a2c2d42b8 [Mips][msa] Added initial MSA support.
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders

llvm-svn: 188313
2013-08-13 20:54:07 +00:00
Jack Carter 9770097727 [Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic

llvm-svn: 188312
2013-08-13 20:19:16 +00:00
Vladimir Medic 939877ee14 This patch implements ei and di instructions for mips. Test cases are added.
llvm-svn: 188176
2013-08-12 13:07:23 +00:00
Akira Hatanaka 00fcf2e169 [mips] Rename accumulator register classes and FP register operands.
llvm-svn: 188020
2013-08-08 21:54:26 +00:00
Akira Hatanaka 13e6ccf341 [mips] Rename register classes CPURegs and CPU64Regs.
llvm-svn: 187832
2013-08-06 23:08:38 +00:00
Akira Hatanaka e2a39e7532 [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.

llvm-svn: 187824
2013-08-06 22:35:29 +00:00
Akira Hatanaka 34a32c0b87 [mips] Replace usages of register classes with register operands. Also, remove
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.

llvm-svn: 187821
2013-08-06 22:20:40 +00:00
Akira Hatanaka 21f334372e [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,
remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.

llvm-svn: 187632
2013-08-01 23:14:16 +00:00
Akira Hatanaka f8fff213d5 [mips] Define instruction itineraries IIArith and IILogic.
No functionality change.

llvm-svn: 187468
2013-07-31 00:55:34 +00:00
Akira Hatanaka 5973e8371a [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
turns "bal" into "bgezal".

llvm-svn: 187440
2013-07-30 20:24:24 +00:00
Akira Hatanaka a3d9ab90dc [mips] Implement llvm.trap intrinsic.
Patch by Sasa Stankovic.

llvm-svn: 187244
2013-07-26 20:58:55 +00:00
Akira Hatanaka 44ff81d4e3 [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855
2013-07-22 18:52:22 +00:00
Vladimir Medic 29410f9c91 Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
llvm-svn: 186507
2013-07-17 14:05:19 +00:00
Akira Hatanaka 1baf2ea2d1 [mips] Add instruction itinerary classes for mult, seb and slt instructions.
llvm-svn: 186222
2013-07-12 22:43:20 +00:00
Vladimir Medic bcf1ca08e0 Add support for Mips break and syscall insructions. The corresponding test cases are added.
llvm-svn: 186151
2013-07-12 09:25:35 +00:00
Vladimir Medic 524ad0e46e Reverting commit r185999 due to buildboot failure.
llvm-svn: 186000
2013-07-10 12:26:26 +00:00
Vladimir Medic e84de1e101 Add support for Mips break and syscall insructions. The corresponding test cases are added.
llvm-svn: 185999
2013-07-10 10:18:10 +00:00
Akira Hatanaka b34ad7860f [mips] Add new InstrItinClasses for move from/to coprocessor instructions and
floating point loads and stores.

No changes in functionality.

llvm-svn: 185399
2013-07-02 00:00:02 +00:00
Akira Hatanaka 1af66c9b8a [mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.

No intended functionality changes.

llvm-svn: 185376
2013-07-01 20:39:53 +00:00
Akira Hatanaka da4496c860 [mips] brcond + setgt/setugt instruction selection patterns.
llvm-svn: 183334
2013-06-05 19:49:55 +00:00
Akira Hatanaka 6871031be9 [mips] Add instruction selection patterns for blez and bgez.
llvm-svn: 182396
2013-05-21 17:13:47 +00:00
Akira Hatanaka 5de4416962 [mips] Add (setne $lhs, 0) instruction selection pattern.
llvm-svn: 182307
2013-05-20 18:18:07 +00:00
Akira Hatanaka 1cb024207f [mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

llvm-svn: 182306
2013-05-20 18:07:43 +00:00
Jack Carter 03f0fd37a9 Mips assembler: Add TwoOperandConstraint definitions
This patch removes alias definition for addiu $rs,$imm 
and instead uses the TwoOperandAliasConstraint field in 
the ArithLogicI instruction class. 

This way all instructions that inherit ArithLogicI class 
have the same macro defined. 

The usage examples are added to test files.

Patch by Vladimir Medic

llvm-svn: 182048
2013-05-16 20:24:27 +00:00
Jack Carter 59817110ff Mips td file formatting: white space and long lines
llvm-svn: 182047
2013-05-16 20:08:49 +00:00
Jack Carter 51785c4715 Mips assembler: Add branch macro definitions
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm

The corresponding test cases are added.

Patch by Vladimir Medic

llvm-svn: 182040
2013-05-16 19:40:19 +00:00
Jack Carter f5f48d8ff7 Mips assembler: Assembler macro ADDIU $rs,imm
This patch adds alias for addiu instruction which enables following syntax:

    addiu $rs,imm

The macro is translated as:

    addiu $rs,$rs,imm


Contributer: Vladimir Medic
llvm-svn: 181729
2013-05-13 20:26:46 +00:00
Akira Hatanaka b4526ea132 [mips] Add instruction selection pattern for (seteq $LHS, 0).
llvm-svn: 181459
2013-05-08 19:38:04 +00:00
Akira Hatanaka 4254319ef9 [mips] Fix handling of instructions which copy to/from accumulator registers.
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.

llvm-svn: 180827
2013-04-30 23:22:09 +00:00
Akira Hatanaka f0aa6c9101 [mips] Add definitions of micromips load and store instructions.
Patch by Zoran Jovanovic.

llvm-svn: 180241
2013-04-25 01:21:25 +00:00
Akira Hatanaka cd9b74a599 [mips] Add definitions of micromips shift instructions.
Patch by Zoran Jovanovic.

llvm-svn: 180238
2013-04-25 01:11:15 +00:00
Akira Hatanaka be6a818fd4 [mips] First patch which adds support for micromips.
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.

llvm-svn: 179873
2013-04-19 19:03:11 +00:00
Akira Hatanaka c68fd9f4f1 [mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change
operand type to uimm16.

Patch by Vladimir Medic.

llvm-svn: 179872
2013-04-19 18:47:40 +00:00
Akira Hatanaka 2f08822f9d [mips] Reapply r179420 and r179421.
llvm-svn: 179434
2013-04-13 00:55:41 +00:00
Akira Hatanaka 8ed2892c1c Revert r179420 and r179421.
llvm-svn: 179422
2013-04-12 22:40:07 +00:00
Akira Hatanaka 931ad87f6a [mips] Instruction selection patterns for carry-setting and using add
instructions.

llvm-svn: 179421
2013-04-12 22:24:52 +00:00
Akira Hatanaka b3c1847b30 [mips] Add patterns for DSP indexed load instructions.
llvm-svn: 178408
2013-03-30 02:14:45 +00:00
Akira Hatanaka b1457304cc [mips] Define reg+imm load/store pattern templates.
llvm-svn: 178407
2013-03-30 02:01:48 +00:00
Akira Hatanaka be8612f6f4 [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.

llvm-svn: 178403
2013-03-30 01:36:35 +00:00
Akira Hatanaka c8d85025a0 [mips] Define pseudo instructions for spilling and copying accumulator
registers.

llvm-svn: 178390
2013-03-30 00:54:52 +00:00
Jack Carter 311246c6d5 [Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction 
to have an immediate parameter. This patch adds an instruction 
alias that converts this macro into a Mips ORI instruction. 

Contributer: Vladimir Medic
llvm-svn: 178316
2013-03-28 23:45:13 +00:00
Jack Carter e1d85d55e6 [Mips Assembler] Add alias definitions for jal
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs

This patch provides alias definitions in td files and test cases to show the usage.

Contributer: Vladimir Medic
llvm-svn: 178304
2013-03-28 23:02:21 +00:00
Jack Carter 9e65aa35a0 This patch that enables the Mips assembler to use symbols for offset for instructions
This patch uses the generated instruction info tables to 
identify memory/load store instructions.
After successful matching and based on the operand type 
and size, it generates additional instructions to the output.

Contributor: Vladimir Medic
llvm-svn: 177685
2013-03-22 00:05:30 +00:00
Akira Hatanaka c7828356aa [mips] Print move instructions.
"move $4, $5" is printed instead of "or $4, $5, $zero".

llvm-svn: 176455
2013-03-04 22:25:01 +00:00
Akira Hatanaka ece459bb66 [mips] Fix inefficient code generation.
This patch eliminates the need to emit a constant move instruction when this
pattern is matched:

(select (setgt a, Constant), T, F)

The pattern above effectively turns into this:

(conditional-move (setlt a, Constant + 1), F, T)

llvm-svn: 176384
2013-03-01 21:52:08 +00:00
Akira Hatanaka a35bc832a0 [mips] Remove SDNPWantParent from the list of SDNodeProperties.
No functionality change intended.

llvm-svn: 175325
2013-02-16 00:14:37 +00:00
Akira Hatanaka 69fb3d11ec [mips] Split SelectAddr, which was used to match address patterns, into two
functions. Set AddedComplexity to determine the order in which patterns are
matched.

This simplifies selection of floating point loads/stores.

No functionality change intended.

llvm-svn: 175300
2013-02-15 21:20:45 +00:00
Reed Kotler b9bf8dca47 Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the
same so we put in the comment field an indicator when we think we are
emitting the 16 bit version. For the direct object emitter, the difference is 
important as well as for other passes which need an accurate count of 
program size. There will be other similar putbacks to this for various
instructions.

llvm-svn: 174747
2013-02-08 21:42:56 +00:00
Akira Hatanaka 061d1ea5da [mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.

llvm-svn: 174657
2013-02-07 19:48:00 +00:00
Akira Hatanaka 556135d813 [mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".
llvm-svn: 174546
2013-02-06 21:50:15 +00:00
Jakob Stoklund Olesen a206050ccb Move MRI liveouts to Mips return instructions.
llvm-svn: 174410
2013-02-05 18:12:03 +00:00
Jack Carter 9c1a027fe8 This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 
llvm-svn: 174358
2013-02-05 08:32:10 +00:00
Reed Kotler f8933f83f0 Start static relocation implementation for mips16.
This checkin makes hello world work. 

llvm-svn: 174264
2013-02-02 04:07:35 +00:00
Akira Hatanaka c0b020690b [mips] Lower EH_RETURN.
Patch by Sasa Stankovic.

llvm-svn: 173862
2013-01-30 00:26:49 +00:00
Jack Carter 7ab15fafe3 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Formatting fixes. Mostly long lines and 
blank spaces at end of lines.

Contributer: Jack Carter
 
llvm-svn: 172882
2013-01-19 02:00:40 +00:00
Jack Carter 86c2c564ff This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

Removal of redundant code and formatting fixes.

Contributers: Jack Carter/Vladimir Medic
 
llvm-svn: 172842
2013-01-18 20:15:06 +00:00
Jack Carter 873c724b4a This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic
llvm-svn: 172284
2013-01-12 01:03:14 +00:00
Craig Topper a8c5ec09c7 Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side.
llvm-svn: 171697
2013-01-07 05:45:56 +00:00
Akira Hatanaka f412e7501a [mips] Reorder template parameters. Remove class shift_rotate_imm32 and
shift_rotate_imm64.

llvm-svn: 171513
2013-01-04 19:25:46 +00:00
Akira Hatanaka e36e2f6876 [mips] Refactor instructions which move data from or to coprocessors.
llvm-svn: 171510
2013-01-04 19:13:49 +00:00
Akira Hatanaka 6ac2fc4976 [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware
instructions.

llvm-svn: 170956
2012-12-21 23:21:32 +00:00
Akira Hatanaka beea8a34c3 [mips] Refactor SYNC and multiply/divide instructions.
llvm-svn: 170955
2012-12-21 23:17:36 +00:00
Akira Hatanaka 31ddec5887 [mips] Refactor BAL instructions.
llvm-svn: 170954
2012-12-21 23:15:59 +00:00
Akira Hatanaka d6b694f036 [mips] Fix encoding of BAL instruction. Also, fix assembler test case which
was not catching the error.

llvm-svn: 170953
2012-12-21 23:13:59 +00:00
Akira Hatanaka a158042a56 [mips] Refactor jump, jump register, jump-and-link and nop instructions.
llvm-svn: 170952
2012-12-21 23:03:50 +00:00
Akira Hatanaka e1826d7464 [mips] Refactor load/store left/right and load-link and store-conditional
instructions.

llvm-svn: 170950
2012-12-21 23:01:24 +00:00
Akira Hatanaka d9bf8424e5 [mips] Refactor load/store instructions.
llvm-svn: 170948
2012-12-21 22:58:55 +00:00
Akira Hatanaka b59b047fbe [mips] Remove unnecessary isPseudo parameter.
llvm-svn: 170947
2012-12-21 22:57:26 +00:00
Akira Hatanaka e738efc95b [mips] Refactor LUI instruction.
llvm-svn: 170944
2012-12-21 22:46:07 +00:00
Akira Hatanaka 895e1cb2aa [mips] Refactor count leading zero or one instructions.
llvm-svn: 170942
2012-12-21 22:43:58 +00:00
Akira Hatanaka 4f4c4aa05e [mips] Refactor sign-extension-in-register instructions.
llvm-svn: 170940
2012-12-21 22:41:52 +00:00
Akira Hatanaka b14c6e4e5f [mips] Refactor instructions which copy from and to HI/LO registers.
llvm-svn: 170939
2012-12-21 22:39:17 +00:00
Akira Hatanaka 9e89195dce [mips] Refactor logical NOR instructions.
llvm-svn: 170937
2012-12-21 22:35:47 +00:00
Akira Hatanaka ac10697207 [mips] Move instruction definitions in MipsInstrInfo.td.
llvm-svn: 170936
2012-12-21 22:33:43 +00:00
Reed Kotler 8965d24a2a There is one more patch to finish large frames. Make sure we assert
on code that has large frames which will not yet compile correctly.

llvm-svn: 170673
2012-12-20 06:57:00 +00:00
Akira Hatanaka e7f1acc7c0 [mips] Refactor SLT (set on less than) instructions. Separate encoding
information from the rest. 

llvm-svn: 170664
2012-12-20 04:27:52 +00:00
Akira Hatanaka bbd197e9c4 [mips] Refactor unconditional branch instruction. Separate encoding information
from the rest. 

llvm-svn: 170663
2012-12-20 04:22:39 +00:00
Akira Hatanaka b1527b7505 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.

llvm-svn: 170661
2012-12-20 04:20:09 +00:00
Akira Hatanaka 14f9ce0f83 [mips] Delete definition of CPRESTORE instruction.
llvm-svn: 170660
2012-12-20 04:15:30 +00:00
Akira Hatanaka c0ea0bb99b [mips] Refactor conditional branch instructions with one register operand.
Separate encoding information from the rest.

llvm-svn: 170659
2012-12-20 04:13:23 +00:00
Akira Hatanaka f71ffd29d9 [mips] Refactor conditional branch instructions with two register operands.
Separate encoding information from the rest.

llvm-svn: 170657
2012-12-20 04:10:13 +00:00
Akira Hatanaka 7d75f9e3d3 [mips] Change the order of template parameters. Move the default parameters to
the end. 

llvm-svn: 170651
2012-12-20 03:52:08 +00:00
Akira Hatanaka 244f9e874c [mips] Refactor shift instructions with register operands. Separate encoding
information from the rest.

llvm-svn: 170650
2012-12-20 03:48:24 +00:00
Akira Hatanaka 7f96ad325f [mips] Refactor shift immediate instructions. Separate encoding information
from the rest.

llvm-svn: 170649
2012-12-20 03:44:41 +00:00
Akira Hatanaka ab1b715bf2 [mips] Refactor arithmetic and logic instructions with immediate operands.
Separate encoding information from the rest.

llvm-svn: 170648
2012-12-20 03:40:03 +00:00
Akira Hatanaka 1b37c4af01 [mips] Refactor arithmetic and logic instructions. Separate encoding
information from the rest.

llvm-svn: 170647
2012-12-20 03:34:05 +00:00
Akira Hatanaka 73495897b1 [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and
ArithLogicI as the instruction base classes.

llvm-svn: 170642
2012-12-20 03:00:16 +00:00
Akira Hatanaka 02ec5516f8 [mips] Move class IsCommutable into MipsInstrInfo.td.
llvm-svn: 170054
2012-12-13 00:32:01 +00:00
Akira Hatanaka efdce0fb09 [mips] Delete nodes and instructions for dynamic alloca that are no longer in
use.

llvm-svn: 169580
2012-12-07 03:10:18 +00:00
Akira Hatanaka 97e179f9e4 [mips] Shorten predicate name.
llvm-svn: 169579
2012-12-07 03:06:09 +00:00
Akira Hatanaka 02a346d11f [mips] Remove unnecessary predicates.
llvm-svn: 169577
2012-12-07 03:01:24 +00:00
Akira Hatanaka bb6e74a2f1 [mips] Generate big GOT code.
llvm-svn: 168460
2012-11-21 20:40:38 +00:00