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1967 Commits

Author SHA1 Message Date
Kevin Enderby e1a12cf3ee Fixed a crash in llvm-mc for Mach-O when a symbol difference expression uses a 
symbol from an assignment.  In this case the symbol did not have a fragment so
MCObjectWriter::IsSymbolRefDifferenceFullyResolved() should not have been
calling IsSymbolRefDifferenceFullyResolvedImpl() with a NULL fragment and should
just have returned false in that case.

llvm-svn: 149442
 2012-01-31 23:02:57 +00:00
Devang Patel 7cdb2ff6b5 Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax. 
llvm-svn: 149291
 2012-01-30 22:47:12 +00:00
Devang Patel 9a9bb5c5db Intel syntax. Support .intel_syntax directive. 
llvm-svn: 149270
 2012-01-30 20:02:42 +00:00
James Molloy b47489d4ef Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends. 
Fixes PR11877

llvm-svn: 149180
 2012-01-28 15:58:32 +00:00
Rafael Espindola 004725876e Small improvement to the recursion detection logic from the previous commit. 
llvm-svn: 149175
 2012-01-28 06:22:14 +00:00
Rafael Espindola 72f5f170c6 Handle recursive variable definitions directly. This gives us better error 
messages and allows us to fix PR11865.

llvm-svn: 149174
 2012-01-28 05:57:00 +00:00
Devang Patel 63fe5697f4 Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] 
llvm-svn: 149142
 2012-01-27 19:48:28 +00:00
James Molloy 6685c08e5f Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. 
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057
 2012-01-26 09:25:43 +00:00
Jim Grosbach 82f76d1275 ARM assemly parsing and validation of IT instruction. 
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969
 2012-01-25 19:52:01 +00:00
Jim Grosbach 086cbfac7d NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach b78403ce48 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Jim Grosbach 35bc8f9159 ARM Darwin symbol ref differences w/o subsection-via-symbols. 
When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.

llvm-svn: 148865
 2012-01-24 21:45:25 +00:00
Devang Patel a410ed3ced Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. 
llvm-svn: 148864
 2012-01-24 21:43:36 +00:00
Jim Grosbach 8e2722cdb0 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Jim Grosbach 14952a0e32 NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jim Grosbach 3cfef8d467 NEON Two-operand assembly aliases for VSRA. 
llvm-svn: 148821
 2012-01-24 17:55:36 +00:00
Jim Grosbach 9ca3a067c8 Remove redundant test file. 
llvm-svn: 148820
 2012-01-24 17:55:32 +00:00
Jim Grosbach 7ae12cc546 NEON Two-operand assembly aliases for VSLI. 
llvm-svn: 148819
 2012-01-24 17:49:15 +00:00
Jim Grosbach 7b6f0f67aa NEON Two-operand assembly aliases for VSRI. 
llvm-svn: 148818
 2012-01-24 17:46:58 +00:00
Jim Grosbach 1395b67e3b Tidy up. 
llvm-svn: 148817
 2012-01-24 17:46:54 +00:00
Jim Grosbach da70eac268 NEON VST4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148764
 2012-01-24 00:58:13 +00:00
Jim Grosbach ed561fc850 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach d3d36d9315 NEON VST3(single element from one lane) assembly parsing. 
llvm-svn: 148755
 2012-01-24 00:07:41 +00:00
Jim Grosbach 1a74724fc9 NEON VST3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148748
 2012-01-23 23:45:44 +00:00
Jim Grosbach ac2af3ffab NEON VLD3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148745
 2012-01-23 23:20:46 +00:00
Devang Patel cf893a437e Intel syntax: Robustify parsing of memory operand's displacement experssion. 
llvm-svn: 148737
 2012-01-23 22:35:25 +00:00
Jim Grosbach a8b444b08b NEON VLD3 lane-indexed assembly parsing and encoding. 
llvm-svn: 148734
 2012-01-23 21:53:26 +00:00
Rafael Espindola 3c47e37387 Add support for .cfi_signal_frame. Fixes pr11762. 
llvm-svn: 148733
 2012-01-23 21:51:52 +00:00
Devang Patel e660fdd953 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] 
llvm-svn: 148721
 2012-01-23 20:20:06 +00:00
Jim Grosbach d28ef9ac46 Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
 2012-01-23 19:39:08 +00:00
Devang Patel 880bc1644b Intel syntax: Parse segment registers. 
llvm-svn: 148712
 2012-01-23 18:31:58 +00:00
Devang Patel ce6a2ca8c8 Intel syntax: Robustify register parsing. 
llvm-svn: 148591
 2012-01-20 22:32:05 +00:00
Devang Patel d0930fff85 Intel syntax: Parse ... PTR [-8] 
llvm-svn: 148570
 2012-01-20 21:21:01 +00:00
Devang Patel f36613cb45 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. 
llvm-svn: 148569
 2012-01-20 21:14:06 +00:00
Jim Grosbach a9d36fbca7 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
 2012-01-20 18:09:51 +00:00
Devang Patel f83dcfd052 Post process 'and', 'sub' instructions and select better encoding, if available. 
llvm-svn: 148489
 2012-01-19 18:40:55 +00:00
Devang Patel 2529dd9e00 Intel syntax: There is no need to create unary expr for simple negative displacement. 
llvm-svn: 148486
 2012-01-19 18:15:51 +00:00
Devang Patel 4a62ff9bcb Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
llvm-svn: 148485
 2012-01-19 17:53:25 +00:00
Jim Grosbach 29ecaa944d Add testcase. 
llvm-svn: 148454
 2012-01-19 01:36:59 +00:00
Jim Grosbach 94298a906a Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
 2012-01-18 22:46:46 +00:00
Devang Patel de47cced25 Process instructions after match to select alternative encoding which may be more desirable. 
llvm-svn: 148431
 2012-01-18 22:42:29 +00:00
Jim Grosbach cb80eb2e75 Thumb2 relaxation for LDR(literal). 
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.

rdar://10711829

llvm-svn: 148424
 2012-01-18 21:54:16 +00:00
Jim Grosbach 4045507fea MC tweak symbol difference resolution for non-local symbols. 
When the non-local symbol in the expression is in the same fragment
as the second symbol, the assembler can still evaluate the expression
without needing a relocation.

For example, on ARM:
_foo:
	ldr lr, (_foo - 4)

rdar://10348687

llvm-svn: 148341
 2012-01-17 22:14:39 +00:00
Jim Grosbach 354f48f201 Tidy up. 
llvm-svn: 148339
 2012-01-17 22:03:42 +00:00
Devang Patel c9ed518792 Intel syntax: Fix parser match class to check memory operand size. 
llvm-svn: 148338
 2012-01-17 21:48:03 +00:00
Devang Patel a7143b6a2b Intel syntax: Parse "BYTE PTR [RDX + RCX]" 
llvm-svn: 148334
 2012-01-17 21:25:10 +00:00
Devang Patel 8b39be79ad Intel syntax: Do not unncessarily create plus expression for memory operand displacement. 
llvm-svn: 148321
 2012-01-17 19:08:07 +00:00
Devang Patel a77c03be54 Intel syntax: Ignore mnemonic aliases. 
llvm-svn: 148316
 2012-01-17 18:30:45 +00:00
Devang Patel 41b9ddeb7a Intel syntax: Robustify memory operand parsing. 
llvm-svn: 148312
 2012-01-17 18:00:18 +00:00
Devang Patel 5d85276e30 Add new test. 
llvm-svn: 148128
 2012-01-13 18:45:31 +00:00