Commit Graph

3 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes cc6659b2ae The Mips specific function for instruction cache invalidation cannot be
compiled on mips32r1 processors because it uses synci and rdhwr instructions
which are supported only on mips32r2, so I replaced this function with the
call to function cacheflush which works for both mips32r1 and mips32r2.
Patch by Sasa Stankovic

llvm-svn: 141564
2011-10-10 18:41:02 +00:00
Bruno Cardoso Lopes 483c269a33 One more patch towards JIT support for Mips.
- Add TSFlags for the instruction formats. The idea here is to use
  as much encoding as possible from getBinaryCodeForInstr, and having
  TSFLags formats for that would make it easier to encode most part
  of the instructions (since Mips encodings are pretty straightforward)
- Improve the mips mechanism for compilation callback
- Add Mips specific code for invalidating the instruction cache
- Next patch will address wrong tablegen encoding

Commit msg added by my own but the patch is from Sasa Stankovic.

llvm-svn: 139688
2011-09-14 03:00:41 +00:00
Michael J. Spencer 447762da85 Merge System into Support.
llvm-svn: 120298
2010-11-29 18:16:10 +00:00