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81 Commits

Author SHA1 Message Date
Richard Osborne 038d24f90c [XCore] Add missing l2rus instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173634
 2013-01-27 22:28:30 +00:00
Richard Osborne f2ecd40929 [XCore] Add missing l2r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173629
 2013-01-27 21:26:02 +00:00
Richard Osborne 7fe8f63544 [XCore] Add missing 1r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173624
 2013-01-27 20:46:21 +00:00
Richard Osborne 8f56317287 [XCore] Add missing 0r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173623
 2013-01-27 20:42:57 +00:00
Richard Osborne 6b86eec819 Add instruction encodings / disassembly support for l4r instructions. 
llvm-svn: 173501
 2013-01-25 21:55:32 +00:00
Richard Osborne a520a7dcf3 Use the correct format in the STW / SETPSC instruction names. 
llvm-svn: 173494
 2013-01-25 21:25:12 +00:00
Richard Osborne 9a228a13c6 Fix order of operands for crc8_l4r 
The order in which operands appear in the encoded instruction is different
to order in which they appear in assembly. This changes the XCore backend to
use the instruction encoding order.

llvm-svn: 173493
 2013-01-25 21:20:28 +00:00
Richard Osborne a19fa86a70 Add instruction encodings / disassembly support for l5r instructions. 
llvm-svn: 173479
 2013-01-25 20:20:07 +00:00
Richard Osborne 8ae02d3cef Fix order of operands for l5r instructions. 
With this change the operands order matches the order in which the operands
are encoded in the instruction.

llvm-svn: 173477
 2013-01-25 20:16:00 +00:00
Richard Osborne ea023fcde1 Use correct mnemonic / instruction name for ldivu. 
llvm-svn: 173476
 2013-01-25 20:11:26 +00:00
Richard Osborne 54e311821f Add instruction encodings / disassembly support for l6r instructions. 
llvm-svn: 173288
 2013-01-23 20:08:11 +00:00
Richard Osborne 1a06479f46 Add instruction encodings / disassembly support for u10 / lu10 instructions. 
llvm-svn: 173204
 2013-01-22 22:55:04 +00:00
Richard Osborne 5d477751df Fix some incorrectly named u10 / lu10 instructions. 
llvm-svn: 173090
 2013-01-21 21:12:30 +00:00
Richard Osborne 38cff3ea7f Remove unused multiclass. 
llvm-svn: 173087
 2013-01-21 20:50:54 +00:00
Richard Osborne 9d3ec06ef8 Add instruction encodings / disassembly support for u6 / lu6 instructions. 
llvm-svn: 173086
 2013-01-21 20:44:17 +00:00
Richard Osborne 6e58c6d86d Add instruction encoding / disassembly support for ru6 / lru6 instructions. 
llvm-svn: 173085
 2013-01-21 20:42:16 +00:00
Richard Osborne 0d68e21ca7 Use correct format for the LDAWCP instruction (u6). 
llvm-svn: 173083
 2013-01-21 20:32:54 +00:00
Richard Osborne 4e69724869 Add instruction encodings / disassembly support for l2rus instructions. 
llvm-svn: 172987
 2013-01-20 18:51:15 +00:00
Richard Osborne 9fbf57b26c Add instruction encodings / disassembly support for l3r instructions. 
llvm-svn: 172986
 2013-01-20 18:37:49 +00:00
Richard Osborne f063fcee7a Add instruction encodings / disassembler support for 2rus instructions. 
llvm-svn: 172985
 2013-01-20 17:22:43 +00:00
Richard Osborne 3fb7395233 Add instruction encodings / disassembly support 3r instructions. 
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

llvm-svn: 172984
 2013-01-20 17:18:47 +00:00
Richard Osborne 459e35c261 Add instruction encodings / disassembly support for l2r instructions. 
llvm-svn: 170345
 2012-12-17 16:28:02 +00:00
Richard Osborne 51bf1b269a Add instruction encodings for PEEK and ENDIN. 
Previously these were marked with the wrong format.

llvm-svn: 170334
 2012-12-17 14:23:54 +00:00
Richard Osborne 041071c558 Add instruction encodings / disassembly support for rus instructions. 
llvm-svn: 170330
 2012-12-17 13:50:04 +00:00
Richard Osborne e405e58639 Add instruction encodings for ZEXT and SEXT. 
Previously these were marked with the wrong format.

llvm-svn: 170327
 2012-12-17 13:20:37 +00:00
Richard Osborne 3a0d5cc314 Add instruction encodings / disassembly support for 2r instructions. 
llvm-svn: 170323
 2012-12-17 12:29:31 +00:00
Richard Osborne 016967e4ff Add instruction encodings / disassembly support for 0r instructions. 
llvm-svn: 170322
 2012-12-17 12:26:29 +00:00
Richard Osborne 1b5562ad8e Add instruction encodings and disassembly for 1r instructions. 
llvm-svn: 170293
 2012-12-16 17:37:34 +00:00
Richard Osborne b1de9f7e07 Replace ${:comment} with the comment symbol. 
llvm-svn: 170286
 2012-12-16 15:59:02 +00:00
Jakob Stoklund Olesen 3ac45d9a1f Fix load/store SDNode flags. 
llvm-svn: 162558
 2012-08-24 14:43:30 +00:00
Bill Wendling ea6397f67b Remove tabs. 
llvm-svn: 160477
 2012-07-19 00:11:40 +00:00
Jakob Stoklund Olesen ed6c0408fa Remove variable_ops from call instructions in most targets. 
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.

llvm-svn: 160189
 2012-07-13 20:44:29 +00:00
Richard Osborne ab7d788eb5 Fix pattern for MKMSK instruction. 
llvm-svn: 158409
 2012-06-13 17:59:12 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Richard Osborne ae191ef63b Fix 80 column violations. 
Original patch by Liu.

llvm-svn: 140385
 2011-09-23 16:28:10 +00:00
Richard Osborne dcde6e30b9 Mark LDWCP as having no side effects. 
llvm-svn: 139494
 2011-09-12 14:41:31 +00:00
Richard Osborne 6e3c83eb1c Add Uses=[SP] to call instructions. This fixes a miscompilation with a 
variable sized alloca.

llvm-svn: 138433
 2011-08-24 13:32:43 +00:00
Richard Osborne 56f3b70225 Add intrinsics for SETEV, GETED, GETET. 
llvm-svn: 137938
 2011-08-18 13:00:48 +00:00
Richard Osborne f1b800998a Add intrinsics for the zext / sext instructions. 
llvm-svn: 135476
 2011-07-19 13:28:50 +00:00
Richard Osborne 252c43ee88 Add intrinsics for the testct, testwct instructions. 
llvm-svn: 135475
 2011-07-19 13:00:40 +00:00
Richard Osborne 707f0beae1 Add intrinsics for the peek and endin instructions. 
llvm-svn: 135474
 2011-07-19 12:50:25 +00:00
Richard Osborne 4dae7379ef Fix 80 column violations. 
llvm-svn: 132341
 2011-05-31 16:30:33 +00:00
Richard Osborne 2f14b0bb1d Add XCore intrinsic for crc8. 
llvm-svn: 132340
 2011-05-31 16:24:49 +00:00
Richard Osborne 542f9a2bcf Add XCore intrinsic for crc32. 
llvm-svn: 132336
 2011-05-31 14:47:36 +00:00
Richard Osborne 9a827b30ab Add XCore intrinsics for initializing / starting / synchronizing threads. 
llvm-svn: 128633
 2011-03-31 15:13:13 +00:00
Richard Osborne 6120962d7d Add XCore intrinsic for setpsc. 
llvm-svn: 127821
 2011-03-17 18:42:05 +00:00
Richard Osborne c871eff3f5 Add XCore intrinsics for setclk, setrdy. 
llvm-svn: 127761
 2011-03-16 21:56:00 +00:00
Richard Osborne d4346f2388 Add checkevent intrinsic to check if any resources owned by the current thread 
can event.

llvm-svn: 127741
 2011-03-16 18:34:00 +00:00
Richard Osborne 3a68eb150b Add XCore intrinsics for getps, setps, setsr and clrsr. 
llvm-svn: 127678
 2011-03-15 13:45:47 +00:00
Richard Osborne 42f52e737e Add XCore intrinsic for eeu instruction. 
llvm-svn: 126384
 2011-02-24 13:39:18 +00:00