Commit Graph

5901 Commits

Author SHA1 Message Date
Konstantin Belochapka 741099bc0f [X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when x86-asm-syntax=intel (PR34617).
Fix for incorrect code generation when x86-asm-syntax=intel.
Differential Revision: https://reviews.llvm.org/D37945

llvm-svn: 314140
2017-09-25 19:26:48 +00:00
Konstantin Belochapka 3477711ec7 [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038).
Fixed suboptimal encoding of instruction memory operand when assembler is used to select 32 bit fixup rather than 8 bit immediate for encoding memory offset value.
Differential Revision: https://reviews.llvm.org/D38117

llvm-svn: 314044
2017-09-22 23:37:48 +00:00
Andre Vieira 640527f7f1 [ARM] Fix assembly and disassembly for VMRS/VMSR
Reviewed by: t.p.northover
Differential Revision: https://reviews.llvm.org/D36306

llvm-svn: 313979
2017-09-22 12:17:42 +00:00
Yonghong Song d2e0d1fa11 bpf: initial 32-bit ALU encoding support in assembler
This patch adds instruction patterns for operations in BPF_ALU. After this,
assembler could recognize some 32-bit ALU statement. For example, those listed
int the unit test file.

Separate MOV patterns are unnecessary as MOV is ALU operation that could reuse
ALU encoding infrastructure, this patch removed those redundant patterns.

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 313961
2017-09-22 04:36:36 +00:00
Jonas Devlieghere 26f9a0c529 [dwarfdump] Add verbose output for .debug-line section
This patch adds dumping of line table instructions as well as the final
state at each specified pc value in verbose mode. This is essentially
the same as the default in Darwin's dwarfdump. Dumping the actual line
table opcodes can be particularly useful for something like debugging a
bad `.debug_line` section.

Differential revision: https://reviews.llvm.org/D37971

llvm-svn: 313910
2017-09-21 20:15:30 +00:00
Simon Atanasyan ede43b71f8 [mips] Implement generation of relocations "chains" used by N32 ABI
In case of using a "nested" relocation expressions like this
`%hi(%neg(%gp_rel()))`, N32 ABI requires generation of three consecutive
relocations. That differs from the N64 ABI case where all relocations
are packed into the single relocation record.

llvm-svn: 313879
2017-09-21 14:04:53 +00:00
Simon Atanasyan 11766558d7 [mips] Fix relocation record format and ELF header for N32 ABI
The N32 ABI uses RELA relocation format, do not use 3-in-1 relocation's
encoding, and uses ELFCLASS32. This change passes the `IsN32` flag
to the `MCAsmBackend` to distinguish usage of N32 ABI.

We still do not handle some cases like providing the `-target-abi=o32`
command line option with the `mips64` target triple. That's why
elf_header.s contains some "FIXME" strings. This case will be fixed in
a separate patch.

Differential revision: https://reviews.llvm.org/D37960

llvm-svn: 313873
2017-09-21 10:44:26 +00:00
Sam Clegg 79cd5d0080 [WebAssembly] Weak symbols should be defined in SF_Global
Summary:
This manifested itself in lld since it meant that weak
symbols were not appearing in archive symbol tables.

Subscribers: jfb, dschuff, jgravelle-google, aheejin

Differential Revision: https://reviews.llvm.org/D38111

llvm-svn: 313838
2017-09-20 23:39:44 +00:00
Sam Clegg 31a2c80935 [WebAssembly] Add support for local symbol bindings
Differential Revision: https://reviews.llvm.org/D38096

llvm-svn: 313817
2017-09-20 21:17:04 +00:00
Simon Atanasyan 72982e6913 [mips] Fix calculation of a branch instruction offset to escape left shift of negative value
llvm-svn: 313815
2017-09-20 21:01:30 +00:00
Matt Arsenault 644883ff07 AMDGPU: Fix encoding of op_sel for mad_mix* opcodes
llvm-svn: 313797
2017-09-20 19:09:28 +00:00
Sam Clegg d95ed959d8 Reland "[WebAssembly] Add support for naming wasm data segments"
Add adds support for naming data segments.  This is useful
useful linkers so that they can merge similar sections.

Differential Revision: https://reviews.llvm.org/D37886

llvm-svn: 313795
2017-09-20 19:03:35 +00:00
Simon Atanasyan 8bdbb29524 [mips] Add a valid test case to check the reason of the recent build-bot failure. NFC
llvm-svn: 313761
2017-09-20 15:57:25 +00:00
Andrew V. Tischenko 92980ce6aa 'into' instruction should not be decoded as a valid instr in 64-bit mode
llvm-svn: 313735
2017-09-20 08:17:17 +00:00
Mike Edwards b487bf45f0 Reverting due to Green Dragon bot failure.
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/42594/

llvm-svn: 313706
2017-09-20 01:21:02 +00:00
Sam Clegg b292c25966 [WebAssembly] Add support for naming wasm data segments
Add adds support for naming data segments.  This is useful
useful linkers so that they can merge similar sections.

Differential Revision: https://reviews.llvm.org/D37886

llvm-svn: 313692
2017-09-19 23:00:57 +00:00
Jonathan Roelofs 85908aa84b [ARM] Relax 'cpsie'/'cpsid' flag parsing.
The ARM docs suggest in examples that the flags can have either case, and there
are applications in the wild that (libopencm3, for example) that expect to be
able to use the uppercase spelling.

https://reviews.llvm.org/D37953

llvm-svn: 313680
2017-09-19 21:23:19 +00:00
Reid Kleckner 26fa1bf4da Re-land "Fix Bug 30978 by emitting cv file checksums."
This reverts r313431 and brings back r313374 with a fix to write
checksums as binary data and not ASCII hex strings.

llvm-svn: 313657
2017-09-19 18:14:45 +00:00
Tony Jiang 425071eff3 [Power9] Add missing Power9 instructions.
The following 8 instructions are implemented in this patch.
addpcis(subpcis, lnia), darn, maddhd, maddhdu, maddld, setb

llvm-svn: 313636
2017-09-19 15:22:36 +00:00
Sam Parker 3fa0ccffc6 [AArch64] Add V8_2aOps feature to Cortex-A55 and 75
Add the missing hardware features the ProcA55 and ProcA75 feature.
These are already enabled via the target parser, but I had missed
them in the backend.

Differential Revision: https://reviews.llvm.org/D37974

llvm-svn: 313535
2017-09-18 14:46:14 +00:00
Sjoerd Meijer 4e6df15962 [ARM] Fix for indexed dot product instruction descriptions
The indexed dot product instructions only accept the lower 16 D-registers as
the indexed register, but we were e.g. incorrectly accepting:

vudot.u8 d16,d16,d18[0]

Differential Revision: https://reviews.llvm.org/D37968

llvm-svn: 313531
2017-09-18 14:17:57 +00:00
Jonas Devlieghere c0a758d8ab [dwarfdump] Make .eh_frame an alias for .debug_frame
This patch makes the `.eh_frame` extension an alias for `.debug_frame`.
Up till now it was only possible to dump the section using objdump, but
not with dwarfdump. Since the two are essentially interchangeable, we
dump whichever of the two is present.

As a workaround, this patch also adds parsing for 3 currently
unimplemented CFA instructions: `DW_CFA_def_cfa_expression`,
`DW_CFA_expression`, and `DW_CFA_val_expression`. Because I lack the
required knowledge, I just parse the fields without actually creating
the instructions.

Finally, this also fixes the typo in the `.debug_frame` section name
which incorrectly contained a trailing `s`.

Differential revision: https://reviews.llvm.org/D37852

llvm-svn: 313530
2017-09-18 14:15:57 +00:00
Alex Bradbury 8ab4a9696a [RISCV] Add support for disassembly
This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s
has been updated appropriately.

Differential Revision: https://reviews.llvm.org/D23567

llvm-svn: 313486
2017-09-17 14:36:28 +00:00
Alex Bradbury 6758ecb98c [RISCV] Add support for all RV32I instructions
This patch supports all RV32I instructions as described in the RISC-V manual.
A future patch will add support for pseudoinstructions and other instruction
expansions (e.g. 0-arg fence -> fence iorw, iorw).

Differential Revision: https://reviews.llvm.org/D23566

llvm-svn: 313485
2017-09-17 14:27:35 +00:00
Eric Beckmann 913213c8ae Revert "Fix Bug 30978 by emitting cv file checksums."
This reverts commit 6389e7aa724ea7671d096f4770f016c3d86b0d54.

There is a bug in this implementation where the string value of the
checksum is outputted, instead of the actual hex bytes.  Therefore the
checksum is incorrect, and this prevent pdbs from being loaded by visual
studio.  Revert this until the checksum is emitted correctly.

llvm-svn: 313431
2017-09-16 01:14:36 +00:00
Sam Clegg 759631c77b [WebAssembly] MC: Create wasm data segments based on MCSections
This means that we can honor -fdata-sections rather than
always creating a segment for each symbol.

It also allows for a followup change to add .init_array and friends.

Differential Revision: https://reviews.llvm.org/D37876

llvm-svn: 313395
2017-09-15 20:54:59 +00:00
Sam Clegg aff1c4df25 [WebAssembly] MC: Fix crash in getProvitionalValue on weak references
- Create helper function for resolving weak references.
- Add test that preproduces the crash.

Differential Revision: https://reviews.llvm.org/D37916

llvm-svn: 313381
2017-09-15 19:22:01 +00:00
Eric Beckmann 349746f044 Fix Bug 30978 by emitting cv file checksums.
Summary:
The checksums had already been placed in the IR, this patch allows
MCCodeView to actually write it out to an MCStreamer.

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D37157

llvm-svn: 313374
2017-09-15 18:20:28 +00:00
Sam Clegg 7c39594357 [WebAssembly] Use a separate wasm data segment for each global symbol
This is stepping stone towards honoring -fdata-sections
and letting the assembler decide how many wasm data
segments to create.

Differential Revision: https://reviews.llvm.org/D37834

llvm-svn: 313313
2017-09-14 23:07:53 +00:00
Simon Dardis 6819a7a1cb [bpf] Fix test to always use little endian.
r313055 broke the big endian buildbots as the CHECK lines contained little
endian data but -triple bpf uses the host endian.

llvm-svn: 313281
2017-09-14 17:55:50 +00:00
Simon Dardis 55e446737f [mips] Implement the 'dext' aliases and it's disassembly alias.
The other members of the dext family of instructions (dextm, dextu) are
traditionally handled by the assembler selecting the right variant of
'dext' depending on the values of the position and size operands.

When these instructions are disassembled, rather than reporting the
actual instruction, an equivalent aliased form of 'dext' is generated
and is reported. This is to mimic the behaviour of binutils.

Reviewers: slthakur, nitesh.jain, atanasyan

Differential Revision: https://reviews.llvm.org/D34887

llvm-svn: 313276
2017-09-14 17:27:53 +00:00
Simon Dardis 6f83ae38a3 [mips] Implement the 'dins' aliases.
Traditionally GAS has provided automatic selection between dins, dinsm and
dinsu. Binutils also disassembles all instructions in that family as 'dins'
rather than the actual instruction.

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D34877

llvm-svn: 313267
2017-09-14 15:17:50 +00:00
Adrian Prantl 3ae35eb56b llvm-dwarfdump: automatically dump both regular and .dwo variant of sections
Since users typically don't really care about the .dwo / non.dwo
distinction, this patch makes it so dwarfdump --debug-<info,...> dumps
.debug_info and (if available) also .debug_info.dwo. This simplifies
the command line interface (I've removed all dwo-specific dump
options) and makes the tool friendlier to use.

Differential Revision: https://reviews.llvm.org/D37771

llvm-svn: 313207
2017-09-13 22:09:01 +00:00
Petar Jovanovic 50e068158b [mips] correct operand range for DINSM instruction
This patch corrects the definition of the DINSM instruction.
Specification for DINSM instruction for Mips64 says that size operand should
be 2 <= size <= 64, but it is defined as uimm5_inssize_plus1 which gives
range of 1 .. 32.

Patch by Aleksandar Beserminji.

Differential Revision: https://reviews.llvm.org/D37683

llvm-svn: 313149
2017-09-13 14:09:13 +00:00
Stefan Pintilie dff606ec3e [Power9] Add missing instructions: extswsli, popcntb
Added the following P9 instructions: extswsli, extswsli., popcntb

Differential Revision: https://reviews.llvm.org/D37342

llvm-svn: 313147
2017-09-13 14:05:27 +00:00
Yonghong Song 06ff655e59 bpf: Add BPF AsmParser support in LLVM
Reviewed-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
llvm-svn: 313055
2017-09-12 17:55:23 +00:00
Adrian Prantl 16aa4cf7ef llvm-dwarfdump: Make -brief the default and add a -verbose option instead.
Differential Revision: https://reviews.llvm.org/D37717

llvm-svn: 312972
2017-09-11 23:05:20 +00:00
Adrian Prantl 7bc1b28291 llvm-dwarfdump: Replace -debug-dump=sect option with individual options.
As discussed on llvm-dev in
http://lists.llvm.org/pipermail/llvm-dev/2017-September/117301.html
this changes the command line interface of llvm-dwarfdump to match the
one used by the dwarfdump utility shipping on macOS. In addition to
being shorter to type this format also has the advantage of allowing
more than one section to be specified at the same time.

In a nutshell, with this change

  $ llvm-dwarfdump --debug-dump=info
  $ llvm-dwarfdump --debug-dump=apple-objc

becomes

  $ dwarfdump --debug-info --apple-objc

Differential Revision: https://reviews.llvm.org/D37714

llvm-svn: 312970
2017-09-11 22:59:45 +00:00
Petar Jovanovic d4f3723c56 [mips][microMIPS] add lapc instruction
Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6.

Patch by Milos Stojanovic.

Differential Revision: https://reviews.llvm.org/D35984

llvm-svn: 312934
2017-09-11 18:34:04 +00:00
Andre Vieira c429aabb91 [ARM] Enable the use of SVC anywhere in an IT block
Differential Revision: https://reviews.llvm.org/D37374

llvm-svn: 312908
2017-09-11 11:11:17 +00:00
Sam Clegg e7a60708ff [WebAssembly] Only treat imports/exports as symbols when reading relocatable object files
This change only treats imported and exports functions and globals
as symbol table entries the object has a "linking" section (i.e. it is
relocatable object file).

In this case all globals must be of type I32 and initialized with
i32.const.  This was previously being assumed but not checked for and
was causing a failure on big endian machines due to using the wrong
value of then union.

See: https://bugs.llvm.org/show_bug.cgi?id=34487

Differential Revision: https://reviews.llvm.org/D37497

llvm-svn: 312674
2017-09-06 22:05:41 +00:00
Matt Arsenault efa1d655d4 AMDGPU: Add ds_{read|write}_addtid_b32 definitions
llvm-svn: 312349
2017-09-01 18:38:02 +00:00
Matt Arsenault ed6e8f0a90 AMDGPU: Add most d16 load/store instruction definitions
Doesn't include the tied operand necessary for the loads,
but is enough for the assembler to work.

llvm-svn: 312347
2017-09-01 18:36:06 +00:00
Sam Clegg 13a2e89926 [WebAssembly] Update relocation names to match spec
Summary: See https://github.com/WebAssembly/tool-conventions/blob/master/Linking.md

Differential Revision: https://reviews.llvm.org/D37385

llvm-svn: 312342
2017-09-01 17:32:01 +00:00
Oliver Stannard d771f6cb16 [ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUB
This adds 2-operand assembly aliases for these instructions:
  add r0, r1    =>   add r0, r0, r1
  sub r0, r1    =>   sub r0, r0, r1

Previously this syntax was only accepted for Thumb2 targets, where the
wide versions of the instructions were used.

This patch allows the 2-operand syntax to be used for Thumb1 targets,
and selects the narrow encoding when it is used for Thumb2 targets.

Differential revision: https://reviews.llvm.org/D37377

llvm-svn: 312321
2017-09-01 10:47:25 +00:00
Sam Parker 5f9346471c [AArch64] v8.3-a complex number support
New instructions are added to AArch32 and AArch64 to aid
floating-point multiplication and addition of complex numbers,
where the complex numbers are packed in a vector register as a
pair of elements. The Imaginary part of the number is placed in the
more significant element, and the Real part of the number is placed
in the less significant element.

Differential Revision: https://reviews.llvm.org/D36792

llvm-svn: 312228
2017-08-31 09:27:04 +00:00
Sam Parker a42d8a9164 [AArch64] IDSAR6 register assembler support
The IDSAR6 system register has been introduced to identify the
v8.3-a Javascript data type conversion and v8.2-a dot product
support.

Differential Revision: https://reviews.llvm.org/D37068

llvm-svn: 312225
2017-08-31 08:36:45 +00:00
Matt Arsenault c8f8cda0cd AMDGPU: Correct operand types for v_mad_mix*
These aren't really packed instructions, so the default
op_sel_hi should be 0 since this indicates a conversion.
The operand types are scalar values that behave similar
to an f16 scalar that may be converted to f32.

Doesn't change the default printing for op_sel_hi, just
the parsing.

llvm-svn: 312179
2017-08-30 22:18:40 +00:00
Eric Christopher 5bea524091 Revert "The current version of LLVM X86 disassembler incorrectly interprets some possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs." temporarily while some regressions are addressed.
This reverts commit r311882.

llvm-svn: 311987
2017-08-29 08:23:46 +00:00
Stefan Pintilie c35e4de388 [Power9] Add new instructions for floating point status and control registers.
Added the following P9 instructions: mffsce, mffscdrn, mffscdrni, mffscrn,
  mffscrni, mffsl

Differential Revision: https://reviews.llvm.org/D37167

llvm-svn: 311903
2017-08-28 18:46:01 +00:00