Commit Graph

599 Commits

Author SHA1 Message Date
Chris Lattner 0048e574fb Fix a fairly major performance problem. If a PHI node had a constant as
an incoming value from a block, the selector would evaluate the constant
at the TOP of the block instead of at the end of the block.  This made the
live range for the constant span the entire block, increasing register
pressure needlessly.

llvm-svn: 12542
2004-03-30 19:10:12 +00:00
Chris Lattner 1a0e9ac2f5 Add the select lowering pass to get initial support for select instructions
llvm-svn: 12541
2004-03-30 18:41:59 +00:00
Chris Lattner 6ca9b89abb Malloc doesn't kill a load. This patch need not go into 1.2 though.
llvm-svn: 12500
2004-03-18 17:01:26 +00:00
Chris Lattner dc47e27188 Fix a really nasty bug that was breaking ijpeg in LLC mode. We were incorrectly
folding load instructions into other instructions across free instruction
boundaries.  Perhaps this will also fix the other strange failures?

llvm-svn: 12494
2004-03-18 06:29:54 +00:00
Alkis Evlogimenos 804dc659b6 Add LAHF instruction
llvm-svn: 12424
2004-03-15 17:20:14 +00:00
Alkis Evlogimenos 4837f6c0d9 Another API change to MRegisterInfo::foldMemoryOperand. Instead of a
MachineBasicBlock::iterator take a MachineInstr*.

llvm-svn: 12392
2004-03-14 20:14:27 +00:00
Alkis Evlogimenos 48da2f8a6d Change MRegisterInfo::foldMemoryOperand to return the folded
instruction to make the API more flexible.

llvm-svn: 12386
2004-03-14 07:19:51 +00:00
Chris Lattner 699aa70f0c It helps if I save the file. :)
llvm-svn: 12357
2004-03-13 00:24:52 +00:00
Chris Lattner 071a5e5649 Rename the intrinsic enum values for llvm.va_* from Intrinsic::va_* to
Intrinsic::va*.  This avoid conflicting with macros in the stdlib.h file.

llvm-svn: 12356
2004-03-13 00:24:00 +00:00
Alkis Evlogimenos 9884bda541 Add support for a wider range of CMOV instructions.
llvm-svn: 12336
2004-03-12 17:59:56 +00:00
Misha Brukman d313bdfa43 Fix compilation on Sparc: assert(0) => abort()
llvm-svn: 12289
2004-03-11 19:08:24 +00:00
Alkis Evlogimenos f234284986 Check if printing of implicit uses is required for all types of shift
instructions.

llvm-svn: 12258
2004-03-09 06:10:15 +00:00
Alkis Evlogimenos 8a3f2f3600 Differentiate between extended precision floats (80-bit) and double precision floats (64-bit)
llvm-svn: 12254
2004-03-09 03:37:54 +00:00
Alkis Evlogimenos 8ac958bf43 Use newly added API to emit bytes for instructions that gas misassembles
llvm-svn: 12253
2004-03-09 03:35:34 +00:00
Alkis Evlogimenos 508b459d12 Add emitInstruction() API so that we can get the bytes of a simple instruction
llvm-svn: 12252
2004-03-09 03:34:53 +00:00
Alkis Evlogimenos a7c2da3af5 Constify things a bit
llvm-svn: 12251
2004-03-09 03:30:12 +00:00
Chris Lattner 653e662a93 Implement folding explicit load instructions into binary operations. For a
testcase like this:

int %test(int* %P, int %A) {
        %Pv = load int* %P
        %B = add int %A, %Pv
        ret int %B
}

We now generate:
test:
        mov %ECX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        add %EAX, DWORD PTR [%ECX]
        ret

Instead of:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%EAX]
        add %EAX, %ECX
        ret

... saving one instruction, and often a register.  Note that there are a lot
of other instructions that could use this, but they aren't handled.  I'm not
really interested in adding them, but mul/div and all of the FP instructions
could be supported as well if someone wanted to add them.

llvm-svn: 12204
2004-03-08 01:58:35 +00:00
Chris Lattner 1dd6afe6a2 Rearrange and refactor some code. No functionality changes.
llvm-svn: 12203
2004-03-08 01:18:36 +00:00
Alkis Evlogimenos d6f62ba55b Add memory operand version of conditional move.
llvm-svn: 12190
2004-03-07 03:19:11 +00:00
Brian Gaeke 8351d8c1a8 make -print-machineinstrs work for both SparcV9 and X86
llvm-svn: 12122
2004-03-04 19:16:23 +00:00
Alkis Evlogimenos b9501c1f8c Add assertion for scale verification.
llvm-svn: 12120
2004-03-04 18:05:02 +00:00
Misha Brukman a6025e6480 Doxygenify some comments.
llvm-svn: 12064
2004-03-01 23:53:11 +00:00
Brian Gaeke 427cec1395 TargetCacheInfo has been removed; its only uses were to propagate a constant
(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.

llvm-svn: 12043
2004-03-01 06:43:29 +00:00
Chris Lattner 1f4642c47c Handle passing constant integers to functions much more efficiently. Instead
of generating this code:

        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        call Y

we now generate:
        mov DWORD PTR [%ESP], 4
        mov DWORD PTR [%ESP + 4], 123
        call Y

Which hurts the eyes less.  :)

Considering that register pressure around call sites is already high (with all
of the callee clobber registers n stuff), this may help a lot.

llvm-svn: 12028
2004-03-01 02:42:43 +00:00
Chris Lattner 5c7d3cda78 Fix a minor code-quality issue. When passing 8 and 16-bit integer constants
to function calls, we would emit dead code, like this:

int Y(int, short, double);
int X() {
  Y(4, 123, 4);
}

--- Old
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
***     mov %AX, 123
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Now we emit:
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Next up, eliminate the mov AX and movsx entirely!

llvm-svn: 12026
2004-03-01 02:34:08 +00:00
Alkis Evlogimenos 9a4653edfa Add instruction name description.
llvm-svn: 11998
2004-02-29 18:44:03 +00:00
Alkis Evlogimenos 0824ffc697 Use correct template for SHLD and SHRD instructions so that the memory
operand size is correctly specified.

llvm-svn: 11997
2004-02-29 09:19:40 +00:00
Alkis Evlogimenos c7fd0770a0 Improve allocation order:
1) For 8-bit registers try to use first the ones that are parts of the
   same register (AL then AH). This way we only alias 2 16/32-bit
   registers after allocating 4 8-bit variables.

2) Move EBX as the last register to allocate. This will cause less
   spills to happen since we will have 8-bit registers available up to
   register excaustion (assuming we use the allocation order). It
   would be nice if we could push all of the 8-bit aliased registers
   towards the end but we much prefer to keep callee saved register to
   the end to avoid saving them on entry and exit of the function.

For example this gives a slight reduction of spills with linear scan
on 164.gzip.

Before:

11221 asm-printer           - Number of machine instrs printed
  975 spiller               - Number of loads added
  675 spiller               - Number of stores added
  398 spiller               - Number of register spills

After:

11182 asm-printer           - Number of machine instrs printed
  952 spiller               - Number of loads added
  652 spiller               - Number of stores added
  386 spiller               - Number of register spills

llvm-svn: 11996
2004-02-29 09:17:01 +00:00
Alkis Evlogimenos ea81b79a97 A big X86 instruction rename. The instructions are renamed to make
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
2004-02-29 08:50:03 +00:00
Chris Lattner 1e36fb030c Eliminate the X86-specific BMI functions, using BuildMI instead.
Replace uses of addZImm with addImm.

llvm-svn: 11992
2004-02-29 07:22:16 +00:00
Chris Lattner 9a97573267 Fix a miscompilation of 197.parser that occurs when you have single basic
block loops.

llvm-svn: 11990
2004-02-29 07:10:16 +00:00
Chris Lattner ed01da8f0b Adjust to change in TII ctor arguments
llvm-svn: 11987
2004-02-29 06:31:44 +00:00
Chris Lattner ca89812db7 These two virtual methods are never called.
llvm-svn: 11984
2004-02-29 05:59:33 +00:00
Alkis Evlogimenos 876f6f96d0 Use correct template for ADC instruction with memory operands.
llvm-svn: 11974
2004-02-29 02:18:17 +00:00
Alkis Evlogimenos fa63580517 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them
to denote this fact.

llvm-svn: 11972
2004-02-28 23:46:44 +00:00
Alkis Evlogimenos 4953ae085a Floating point loads/stores act on memory operands. Rename them to
denote this fact.

llvm-svn: 11971
2004-02-28 23:42:35 +00:00
Alkis Evlogimenos c6948fa762 Rename instruction templates to be easier to the human eye to
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
2004-02-28 23:09:03 +00:00
Alkis Evlogimenos 5b5dee4afb Uncomment instructions that take both an immediate and a memory
operand but their sizes differ.

llvm-svn: 11969
2004-02-28 22:06:59 +00:00
Alkis Evlogimenos 194939086d Each instruction now has both an ImmType and a MemType. This describes
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
2004-02-28 22:02:05 +00:00
Alkis Evlogimenos 2debead504 Do not generate instructions with mismatched memory/immediate sized
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
2004-02-28 06:01:43 +00:00
Alkis Evlogimenos 24b3d0bdae Further comment updates.
llvm-svn: 11933
2004-02-28 03:20:31 +00:00
Alkis Evlogimenos f87966b8c4 Update comments.
llvm-svn: 11932
2004-02-28 03:12:31 +00:00
Alkis Evlogimenos 2dbc79df84 My previous commit broke the jit. The shift instructions always take
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
2004-02-28 02:56:26 +00:00
Alkis Evlogimenos b10b04c5ec Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of
instructions.

llvm-svn: 11923
2004-02-27 19:46:30 +00:00
Alkis Evlogimenos 75ed0f67bf Fix encoding of ADD and SUB family of instructions. Also rearrange
them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922
2004-02-27 18:57:00 +00:00
Alkis Evlogimenos 58270fcf1f Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}.
llvm-svn: 11921
2004-02-27 18:55:12 +00:00
Alkis Evlogimenos 9476b7cbe5 Add memory operand folding support for the SETcc family of
instructions.

llvm-svn: 11907
2004-02-27 16:13:37 +00:00
Alkis Evlogimenos 8d99063b38 Add memory operand folding support for SHLD and SHRD instructions.
llvm-svn: 11905
2004-02-27 15:03:18 +00:00
Alkis Evlogimenos 3537404299 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions.
llvm-svn: 11903
2004-02-27 09:28:43 +00:00
Alkis Evlogimenos f020dfb43c Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them
consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
2004-02-27 06:57:05 +00:00