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122 Commits

Author SHA1 Message Date
Lang Hames 95400e22f9 Remove redundant symbolization support from MCDisassembler interface. 
MCDisassembler has an MCSymbolizer member that is meant to take care of
symbolizing during disassembly, but it also has several methods that enable the
disassembler to do symbolization internally (i.e. without an attached symbolizer
object). There is no need for this duplication, but ARM64 had been making use of
it. This patch moves the ARM64 symbolization logic out of ARM64Disassembler and
into an ARM64ExternalSymbolizer class, and removes the duplicated MCSymbolizer
functionality from the MCDisassembler interface. Symbolization will now be
done exclusively through MCSymbolizers.

There should be no impact on disassembly for any platform, but this allows us to
tidy up the MCDisassembler interface and simplify the process of (and invariants
related to) disassembler setup.

llvm-svn: 206063
 2014-04-11 20:07:58 +00:00
David Blaikie ceec2bdaa5 Implement depth_first and inverse_depth_first range factory functions. 
Also updated as many loops as I could find using df_begin/idf_begin -
strangely I found no uses of idf_begin. Is that just used out of tree?

Also a few places couldn't use df_begin because either they used the
member functions of the depth first iterators or had specific ordering
constraints (I added a comment in the latter case).

Based on a patch by Jim Grosbach. (Jim - you just had iterator_range<T>
where you needed iterator_range<idf_iterator<T>>)

llvm-svn: 206016
 2014-04-11 01:50:01 +00:00
Jim Grosbach f77265bfee [ARM64,C++11] Range'ify use-lists iterators in address type promotion. 
llvm-svn: 206013
 2014-04-11 01:13:10 +00:00
Jim Grosbach 8838d793b7 [ARM64,C++11]: Range'ify use-list iterators in DAGToDAG. 
llvm-svn: 206007
 2014-04-11 00:27:22 +00:00
Jim Grosbach d3249d0923 [ARM64,C++11]: More range-based loop simplification. 
llvm-svn: 206006
 2014-04-11 00:27:19 +00:00
Jim Grosbach 577e921344 [ARM64,C++11]: Range'ify loops in InstrInfo. 
llvm-svn: 205992
 2014-04-10 22:00:18 +00:00
Jim Grosbach 8a0c50e5a9 [ARM64,C++11]: Range'ify loops in the conditional-compare pass. 
llvm-svn: 205988
 2014-04-10 21:49:24 +00:00
NAKAMURA Takumi 12fbced6e8 ARM64/*/LLVMBuild.txt: Prune redundant deps. 
llvm-svn: 205963
 2014-04-10 12:46:13 +00:00
NAKAMURA Takumi 554c287262 LLVMBuild.txt: Add missing dependencies. 
llvm-svn: 205962
 2014-04-10 11:16:47 +00:00
NAKAMURA Takumi 98905d3f85 LLVMBuild.txt: Reformat. 
llvm-svn: 205961
 2014-04-10 11:16:17 +00:00
NAKAMURA Takumi d8570e5bc2 Fix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid). 
FIXME: Could we use SmallString here?
llvm-svn: 205950
 2014-04-10 03:05:59 +00:00
Saleem Abdulrasool c5e0099ffc ARM64: add an explicit cast to silence a silly warning 
GCC 4.8 complains with:
  warning: enumeral and non-enumeral type in conditional expression

Although this is silly and harmless in this case, add an explicit cast to
silence the warning.

llvm-svn: 205949
 2014-04-10 02:48:10 +00:00
Juergen Ributzka 48c8c07d0a [ARM64] Fix immediate cost calculation for types larger than i64. 
The immediate cost calculation code was hitting an assertion in the included
test case, because APInt was still internally 128-bits. Truncating it to 64-bits
fixed the issue.

Fixes <rdar://problem/16572521>.

llvm-svn: 205947
 2014-04-10 01:36:59 +00:00
Bob Wilson ae89ddedff Simple fix for build failures resulting from r205867. 
llvm-svn: 205918
 2014-04-09 18:34:45 +00:00
Alp Toker 16f98b255d Fix some doc and comment typos 
llvm-svn: 205899
 2014-04-09 14:47:27 +00:00
Bradley Smith 246b0b617d [ARM64] Change SYS without a register to an alias to make disassembling more consistant. 
llvm-svn: 205898
 2014-04-09 14:44:58 +00:00
Bradley Smith 2cef19a2e6 [ARM64] Correctly disassemble ISB operand as ISB not DBarrier. 
llvm-svn: 205897
 2014-04-09 14:44:54 +00:00
Bradley Smith 239120cada [ARM64] Properly support both apple and standard syntax for FMOV 
llvm-svn: 205896
 2014-04-09 14:44:49 +00:00
Bradley Smith a2308f47d3 [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. 
llvm-svn: 205895
 2014-04-09 14:44:44 +00:00
Bradley Smith f280e91849 [ARM64] Conditional branches must always print their condition code, even AL. 
llvm-svn: 205894
 2014-04-09 14:44:39 +00:00
Bradley Smith a19b7e83dc [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. 
llvm-svn: 205893
 2014-04-09 14:44:36 +00:00
Bradley Smith a0d7a9a12f [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional. 
llvm-svn: 205892
 2014-04-09 14:44:31 +00:00
Bradley Smith 70c6acbbfd [ARM64] Add missing shifted register MVN alias to ORN 
llvm-svn: 205891
 2014-04-09 14:44:26 +00:00
Bradley Smith 403bbf95c0 [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations. 
llvm-svn: 205890
 2014-04-09 14:44:22 +00:00
Bradley Smith 779238a216 [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias. 
llvm-svn: 205889
 2014-04-09 14:44:18 +00:00
Bradley Smith f823079acd [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types 
llvm-svn: 205888
 2014-04-09 14:44:12 +00:00
Bradley Smith af2710c96f [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. 
llvm-svn: 205887
 2014-04-09 14:44:07 +00:00
Bradley Smith a0dce246ed [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. 
llvm-svn: 205886
 2014-04-09 14:44:03 +00:00
Bradley Smith 3971d3dc75 [ARM64] Rename LR to the UAL-compliant 'X30'. 
llvm-svn: 205885
 2014-04-09 14:43:59 +00:00
Bradley Smith 6f1aa59c31 [ARM64] Rename FP to the UAL-compliant 'X29'. 
llvm-svn: 205884
 2014-04-09 14:43:50 +00:00
Bradley Smith 5511f08055 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value. 
llvm-svn: 205883
 2014-04-09 14:43:40 +00:00
Bradley Smith eb4ca04db2 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. 
llvm-svn: 205882
 2014-04-09 14:43:35 +00:00
Bradley Smith db7b9b17eb [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear. 
llvm-svn: 205881
 2014-04-09 14:43:31 +00:00
Bradley Smith 60e7667886 [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero. 
llvm-svn: 205880
 2014-04-09 14:43:27 +00:00
Bradley Smith 7525b47208 [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. 
llvm-svn: 205879
 2014-04-09 14:43:24 +00:00
Bradley Smith 0243aa33fa [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu. 
llvm-svn: 205878
 2014-04-09 14:43:20 +00:00
Bradley Smith 8f906a3c5f [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
llvm-svn: 205877
 2014-04-09 14:43:15 +00:00
Bradley Smith 9f29b726d5 [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases. 
llvm-svn: 205876
 2014-04-09 14:43:11 +00:00
Bradley Smith e8b4166acc [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. 
llvm-svn: 205875
 2014-04-09 14:43:06 +00:00
Bradley Smith bc35b1f138 [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
llvm-svn: 205874
 2014-04-09 14:43:01 +00:00
Bradley Smith 4925be9b56 [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. 
llvm-svn: 205873
 2014-04-09 14:42:56 +00:00
Bradley Smith 3339427e2a [ARM64] Remove PrefetchOp and use ARM64PRFM instead. 
llvm-svn: 205872
 2014-04-09 14:42:53 +00:00
Bradley Smith 16478c4ccf [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway. 
llvm-svn: 205871
 2014-04-09 14:42:49 +00:00
Bradley Smith 3db2a85853 [ARM64] Remove ARM64SYS. 
llvm-svn: 205870
 2014-04-09 14:42:45 +00:00
Bradley Smith fb90df563f [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS. 
llvm-svn: 205869
 2014-04-09 14:42:42 +00:00
Bradley Smith 08c391c156 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. 
llvm-svn: 205868
 2014-04-09 14:42:36 +00:00
Bradley Smith 2ba17a4a17 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. 
llvm-svn: 205867
 2014-04-09 14:42:27 +00:00
Bradley Smith ceeb04df60 [ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. 
llvm-svn: 205866
 2014-04-09 14:42:16 +00:00
Bradley Smith 8c0b88c987 [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 
llvm-svn: 205865
 2014-04-09 14:42:11 +00:00
Bradley Smith 527bf86e56 [ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL) 
llvm-svn: 205864
 2014-04-09 14:42:07 +00:00