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Author SHA1 Message Date
Zvi Rackover 4b7d724d62 [X86] Optimize vector shifts with variable but uniform shift amounts 
Summary:
For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register.
The lower 64-bits of the register are evaluated to determine the shift amount.
This patch improves the construction of the vector containing the shift amount.

Reviewers: craig.topper, delena, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28353

llvm-svn: 291120
 2017-01-05 15:11:43 +00:00
Simon Pilgrim fbe0fcb009 [X86][SSE] Regenerate vshift tests 
llvm-svn: 277278
 2016-07-30 20:28:02 +00:00
Simon Pilgrim 5ec5c9cafe [X86][SSE] Avoid scalarization of v2i64 vector shifts (REAPPLIED) 
Fixed broken tests.

Differential Revision: http://reviews.llvm.org/D8416

llvm-svn: 232682
 2015-03-18 22:18:51 +00:00
Eric Christopher 050f590a0c Revert "[X86][SSE] Avoid scalarization of v2i64 vector shifts" as it 
appears to have broken tests/bots.

This reverts commit r232660.

llvm-svn: 232670
 2015-03-18 21:01:00 +00:00
Simon Pilgrim 5c837edc2a [X86][SSE] Avoid scalarization of v2i64 vector shifts 
Currently v2i64 vectors shifts (non-equal shift amounts) are scalarized, costing 4 x extract, 2 x x86-shifts and 2 x insert instructions - and it gets even more awkward on 32-bit targets.

This patch separately shifts the vector by both shift amounts and then shuffles the partial results back together, costing 2 x shuffles and 2 x sse-shifts instructions (+ 2 movs on pre-AVX hardware).

Note - this patch only improves the SHL / LSHR logical shifts as only these are supported in SSE hardware.

Differential Revision: http://reviews.llvm.org/D8416

llvm-svn: 232660
 2015-03-18 19:35:31 +00:00
Andrea Di Biagio 2876a67312 [X86] Avoid introducing extra shuffles when lowering packed vector shifts. 
When lowering a vector shift node, the backend checks if the shift count is a
shuffle with a splat mask. If so, then it introduces an extra dag node to
extract the splat value from the shuffle. The splat value is then used
to generate a shift count of a target specific shift.

However, if we know that the shift count is a splat shuffle, we can use the
splat index 'I' to extract the I-th element from the first shuffle operand.
The advantage is that the splat shuffle may become dead since we no longer
use it.

Example:

;;
define <4 x i32> @example(<4 x i32> %a, <4 x i32> %b) {
  %c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
  %shl = shl <4 x i32> %a, %c
  ret <4 x i32> %shl
}
;;

Before this patch, llc generated the following code (-mattr=+avx):
  vpshufd $0, %xmm1, %xmm1   # xmm1 = xmm1[0,0,0,0]
  vpxor  %xmm2, %xmm2
  vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
  vpslld %xmm1, %xmm0, %xmm0
  retq

With this patch, the redundant splat operation is removed from the code.
  vpxor  %xmm2, %xmm2
  vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
  vpslld %xmm1, %xmm0, %xmm0
  retq

llvm-svn: 223461
 2014-12-05 12:13:30 +00:00
Juergen Ributzka 5b6234dc4a Force CPU type to unbreak unit tests on Haswell machines. 
llvm-svn: 195971
 2013-11-30 03:07:16 +00:00
Quentin Colombet 6bf4baa408 [DAGCombiner] insert_vector_elt: Avoid building a vector twice. 
This patch prevents the following combine when the input vector is used more
than once.
insert_vector_elt (build_vector elt0, ..., eltN), NewEltIdx, idx
=>
build_vector elt0, ..., NewEltIdx, ..., eltN 

The reasons are:
- Building a vector may be expensive, so try to reuse the existing part of a
  vector instead of creating a new one (think big vectors).
- elt0 to eltN now have two users instead of one. This may prevent some other
  optimizations.

llvm-svn: 187396
 2013-07-30 00:24:09 +00:00
Stephen Lin d24ab20e9b Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. 
This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done

llvm-svn: 186280
 2013-07-14 06:24:09 +00:00
Bill Wendling 410ec4aad1 As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias 
(movzx/movsx) because they give more information. Revert that part of the patch.

llvm-svn: 129498
 2011-04-14 01:46:37 +00:00
Bill Wendling 7e07d6fb69 Have the X86 back-end emit the alias instead of what's being aliased. In most 
cases, it's much nicer and more informative reading the alias.

llvm-svn: 129497
 2011-04-14 01:11:51 +00:00
Chris Lattner ff392ab3ed now that generic vector types aren't selected onto MMX registers, these 
tests don't need -disable-mmx.

llvm-svn: 122188
 2010-12-19 20:12:58 +00:00
Dan Gohman 40503396da Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81290
 2009-09-08 23:54:48 +00:00
Daniel Dunbar abf2bb683a Remove dead greps. 
llvm-svn: 80946
 2009-09-03 20:59:02 +00:00
Mon P Wang eadd21ea3c Test cases for vector shifts changes r80935 
Changed the old vector shift test to use FileCheck

llvm-svn: 80936
 2009-09-03 19:57:35 +00:00
Dan Gohman 0d4bbf2c4a Remove obsolete -f flags. 
llvm-svn: 79992
 2009-08-25 15:38:29 +00:00
Mon P Wang d880efc005 Added sse test patterns for r62979 and r63193. 
llvm-svn: 63194
 2009-01-28 08:13:56 +00:00