Commit Graph

159 Commits

Author SHA1 Message Date
Dan Gohman e58ab79f33 Make x86's BT instruction matching more thorough, and add some
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266
2009-01-29 01:59:02 +00:00
Dan Gohman 4aa1846215 Make isOperationLegal do what its name suggests, and introduce a
new isOperationLegalOrCustom, which does what isOperationLegal
previously did.

Update a bunch of callers to use isOperationLegalOrCustom
instead of isOperationLegal. In some case it wasn't obvious
which behavior is desired; when in doubt I changed then to
isOperationLegalOrCustom as that preserves their previous
behavior.

This is for the second half of PR3376.

llvm-svn: 63212
2009-01-28 17:46:25 +00:00
Bob Wilson c58900504b Add SelectionDAG::getNOT method to construct bitwise NOT operations,
corresponding to the "not" and "vnot" PatFrags.  Use the new method
in some places where it seems appropriate.

llvm-svn: 62768
2009-01-22 17:39:32 +00:00
Sanjiv Gupta 1d2fc787a9 Few targets like PIC16 wants libcall generation for illegal type i16.
llvm-svn: 62467
2009-01-18 18:25:27 +00:00
Dan Gohman 307954ac69 Make getWidenVectorType const; this file was missed in the
previous commit.

llvm-svn: 62266
2009-01-15 17:39:39 +00:00
Dan Gohman dbc6c31f62 TargetLowering.h #includes SelectionDAGNodes.h, so it doesn't need its
own OpActionsCapacity magic number; it can just use ISD::BUILTIN_OP_END,
as long as it takes care to round up when needed.

llvm-svn: 61733
2009-01-05 19:40:39 +00:00
Duncan Sands 8feb694e8f Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).

llvm-svn: 61542
2009-01-01 15:52:00 +00:00
Mon P Wang a501640ffa Added support for vector widening.
llvm-svn: 61209
2008-12-18 20:03:17 +00:00
Eli Friedman c8228d263b Followup to r60283: optimize arbitrary width signed divisions as well
as unsigned divisions.  Same caveats as before.

llvm-svn: 60284
2008-11-30 06:35:39 +00:00
Eli Friedman 1b7fc154a5 Fix for PR2164: allow transforming arbitrary-width unsigned divides into
multiplies.

Some more cleverness would be nice, though. It would be nice if we 
could do this transformation on illegal types.  Also, we would 
prefer a narrower constant when possible so that we can use a narrower
multiply, which can be cheaper.

llvm-svn: 60283
2008-11-30 06:02:26 +00:00
Eli Friedman bd0f57821a APIntify a test which is potentially unsafe otherwise, and fix the
nearby FIXME.

I'm not sure what the right way to fix the Cell test was; if the 
approach I used isn't okay, please let me know.

llvm-svn: 60277
2008-11-30 04:59:26 +00:00
Duncan Sands 8d6e2e13d5 Rename SetCCResultContents to BooleanContents. In
practice these booleans are mostly produced by SetCC,
however the concept is more general.

llvm-svn: 59911
2008-11-23 15:47:28 +00:00
Dale Johannesen ffc67df2aa Fix the testb optimization so x86 also bootstraps.
Reenable test.

llvm-svn: 59101
2008-11-12 02:00:35 +00:00
Bill Wendling b85755c829 Temporarily revert r58979 and related patch. It's causing a failure in X86 bootstrap:
Comparing stages 2 and 3
warning: ./cc1-checksum.o differs
warning: ./cc1obj-checksum.o differs
warning: ./cc1objplus-checksum.o differs
warning: ./cc1plus-checksum.o differs
Bootstrap comparison failure!
./alias.o differs
./alloc-pool.o differs
./attribs.o differs
./bb-reorder.o differs
./bitmap.o differs
./build/errors.o differs
./build/genattrtab.o differs
./build/genautomata.o differs
./build/genemit.o differs
./build/genextract.o differs
...

-bw

llvm-svn: 59003
2008-11-10 21:22:06 +00:00
Dale Johannesen 671743369c Really fix testb optimization on big-endian.
Fixes ppc32 bootstrap.

llvm-svn: 58979
2008-11-10 07:16:42 +00:00
Dale Johannesen aa4d82d244 Temporarily revert 58825, which breaks PPC bootstrap.
xs

llvm-svn: 58930
2008-11-09 06:48:10 +00:00
Dale Johannesen bb5c9b4b68 Make testb optimization work on big-endian targets.
llvm-svn: 58874
2008-11-08 00:01:16 +00:00
Dale Johannesen 7aad542d35 When we're doing a compare of load-AND-constant to 0
(e.g. a bitfield test) narrow the load as much as possible.
The has the potential to avoid unnecessary partial-word
load-after-store conflicts, which cause stalls on several targets.
Also a size win on x86 (testb vs testl).

llvm-svn: 58825
2008-11-07 01:28:02 +00:00
Mon P Wang 9a8d60a7c0 Widening cleanup
llvm-svn: 58796
2008-11-06 05:31:54 +00:00
Mon P Wang 58c3794c27 Add initial support for vector widening. Logic is set to widen for X86.
One will only see an effect if legalizetype is not active.  Will move
support to LegalizeType soon.

llvm-svn: 58426
2008-10-30 08:01:45 +00:00
Dan Gohman 2fe6bee5b6 Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.

llvm-svn: 57748
2008-10-18 02:06:02 +00:00
Chris Lattner 860df6e84c Keep track of *which* input constraint matches an output
constraint.  Reject asms where an output has multiple
input constraints tied to it.

llvm-svn: 57687
2008-10-17 16:47:46 +00:00
Chris Lattner ef8901722e add an assert so that PR2356 explodes instead of running off an
array.  Improve some minor comments, refactor some helpers in
AsmOperandInfo.  No functionality change for valid code.

llvm-svn: 57686
2008-10-17 16:21:11 +00:00
Evan Cheng 3b0f5e4d61 - Add target lowering hooks that specify which setcc conditions are illegal,
i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.

llvm-svn: 57542
2008-10-15 02:05:31 +00:00
Evan Cheng 07d53b1d33 Rename LoadX to LoadExt.
llvm-svn: 57526
2008-10-14 21:26:46 +00:00
Matthijs Kooijman 43686a6665 * Make TargetLowering not crash when TargetMachine::getTargetAsmInfo() returns
null. This assumes that any target that does not have AsmInfo, does not
   support "LocAndDot".

llvm-svn: 57438
2008-10-13 12:41:46 +00:00
Dan Gohman 6e0548336a Rename ConstantSDNode's getSignExtended to getSExtValue, for
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.

llvm-svn: 56700
2008-09-26 21:54:37 +00:00
Evan Cheng e0add20c1b Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
llvm-svn: 56526
2008-09-24 00:05:32 +00:00
Dale Johannesen 7a74e71489 Make log, log2, log10, exp, exp2 use Expand by
default.

llvm-svn: 56471
2008-09-22 21:57:32 +00:00
Dan Gohman effb894453 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Dale Johannesen da2d80688b Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).

llvm-svn: 55753
2008-09-04 00:47:13 +00:00
Gabor Greif f304a7aa4d erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
Dan Gohman 2af34bd309 Add libcalls for the new rounding opcodes.
llvm-svn: 55133
2008-08-21 18:38:14 +00:00
Bruno Cardoso Lopes de5161fdf2 Add the remaining fp_round libcalls:
FPROUND_F80_F32, FPROUND_PPCF128_F32, 
FPROUND_F80_F64, FPROUND_PPCF128_F64

Support for soften float fp_round operands is added, Mips 
needs this to round f64->f32.

Also added support to soften float FABS result, Mips doesn't 
support double fabs results while in 'single float only' mode.

llvm-svn: 54484
2008-08-07 19:01:24 +00:00
Dan Gohman 2ce6f2ad5e Rename SDOperand to SDValue.
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Duncan Sands 77a3d05f1e Factorize some code for determining which libcall to use.
llvm-svn: 53713
2008-07-17 02:36:29 +00:00
Duncan Sands 3e7d0fa3ca It is pointless to turn a UINT_TO_FP into an
SINT_TO_FP libcall plus additional operations:
it might as well be a direct UINT_TO_FP libcall.
So only turn it into an SINT_TO_FP if the target
has special handling for SINT_TO_FP.

llvm-svn: 53461
2008-07-11 17:00:14 +00:00
Duncan Sands 37b7322b35 Add two missing SINT_TO_FP libcalls.
llvm-svn: 53460
2008-07-11 16:57:02 +00:00
Duncan Sands 927a3648d5 Add support for 128 bit shifts and 32 bit shifts
on 16 bit machines.

llvm-svn: 53458
2008-07-11 16:52:29 +00:00
Duncan Sands abdcac66dc Add support for 128 bit multiplicative operations.
Lack of these caused a bootstrap failure with Fortran
on x86-64 with LegalizeTypes turned on.  While there,
be nice to 16 bit machines and support expansion of
i32 too.

llvm-svn: 53408
2008-07-10 15:35:05 +00:00
Duncan Sands 5e6d1402c2 Add a mysteriously missing libcall, FPTOSINT_F80_I32.
Be nice to 16 bit machines by supporting FP_TO_XINT
expansion for these.

llvm-svn: 53407
2008-07-10 15:33:02 +00:00
Duncan Sands 33ff5c8d0d Add support for expanding PPC 128 bit floats.
For this it is convenient to permit floats to
be used with EXTRACT_ELEMENT, so I tweaked
things to allow that.  I also added libcalls
for ppcf128 to i32 forms of FP_TO_XINT, since
they exist in libgcc and this case can certainly
occur (and does occur in the testsuite) - before
the i64 libcall was being used.  Also, the
XINT_TO_FP result seemed to be wrong when
the argument is an i128: the wrong fudge
factor was added (the i32 and i64 cases were
handled directly, but the i128 code fell
through to some generic softening code which
seemed to think it was i64 to f32!).  So I
fixed it by adding a fudge factor that I
found in my breakfast cereal.

llvm-svn: 52739
2008-06-25 20:24:48 +00:00
Dan Gohman e38cc01244 Teach isGAPlusOffset to respect a GlobalAddressSDNode's offset
value, which is something that apparently isn't used much.

llvm-svn: 52158
2008-06-09 22:05:52 +00:00
Duncan Sands 67d0f332d5 Various tweaks related to apint codegen. No functionality
change for non-funky-sized integers.

llvm-svn: 52151
2008-06-09 15:48:25 +00:00
Duncan Sands 11dd424539 Remove comparison methods for MVT. The main cause
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits.  Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.

llvm-svn: 52098
2008-06-08 20:54:56 +00:00
Duncan Sands 13237ac3b9 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044
2008-06-06 12:08:01 +00:00
Evan Cheng b980f6fb3d Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
llvm-svn: 51008
2008-05-12 23:04:07 +00:00
Evan Cheng 2609d5e779 Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it.
llvm-svn: 50991
2008-05-12 19:56:52 +00:00
Dan Gohman 38dc08f36f Instead of enumerating each opcode that isn't handled that
ComputeMaskedBits handles, just use a 'default:'. This avoids
TargetLowering's list getting out of date with SelectionDAG's.

llvm-svn: 50693
2008-05-06 00:53:29 +00:00
Mon P Wang 3e58393c3d Added addition atomic instrinsics and, or, xor, min, and max.
llvm-svn: 50663
2008-05-05 19:05:59 +00:00