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2 Commits

Author SHA1 Message Date
Tim Renouf 361b5b2193 [AMDGPU] Support for v3i32/v3f32 
Added support for dwordx3 for most load/store types, but not DS, and not
intrinsics yet.

SI (gfx6) does not have dwordx3 instructions, so they are not enabled
there.

Some of this patch is from Matt Arsenault, also of AMD.

Differential Revision: https://reviews.llvm.org/D58902

Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9
llvm-svn: 356659
 2019-03-21 12:01:21 +00:00
Stanislav Mekhanoshin 344968fdb4 [AMDGPU] Split idot4/8 signed and unsigned tests. NFC. 
llvm-svn: 353593
 2019-02-09 01:02:28 +00:00