Commit Graph

366766 Commits

Author SHA1 Message Date
Denis Antrushin ee86688b81 [Statepoints][ISEL] gc.relocate uniquification should be based on SDValue, not IR Value.
When exporting statepoint results to virtual registers we try to avoid
generating exports for duplicated inputs. But we erroneously use
IR Value* to check if inputs are duplicated. Instead, we should use
SDValue, because even different IR values can get lowered to the same
SDValue.
I'm adding a (degenerate) test case which emphasizes importance of this
feature for invoke statepoints.
If we fail to export only unique values we will end up with something
like that:

  %0 = STATEPOINT
  %1 = COPY %0

landing_pad:
  <use of %1>

And when exceptional path is taken, %1 is left uninitialized (COPY is never
execute).

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D87695
2020-09-21 19:44:46 +07:00
Adam Balogh 4fc0214a10 [clang-tidy] New check cppcoreguidelines-prefer-member-initializer
Finds member initializations in the constructor body which can be placed
into the initialization list instead. This does not only improves the
readability of the code but also affects positively its performance.
Class-member assignments inside a control statement or following the
first control statement are ignored.

Differential Revision: https://reviews.llvm.org/D71199
2020-09-21 14:42:58 +02:00
Paul Walker f3fa954b5b [SVE] Change definition of reduction ISD nodes to have an SVE vector result type.
The current nodes, AArch64::SMAXV_PRED for example, are defined to
return a NEON vector result.  This is incorrect because they modify
the complete SVE register and are thus changed to represent such.

This patch also adds nodes for UADDV_PRED and SADDV_PRED, which
unifies the handling of all SVE reductions.

NOTE: Floating-point reductions are already implemented correctly,
so this patch is essentially making everything consistent with those.

Differential Revision: https://reviews.llvm.org/D87843
2020-09-21 13:16:28 +01:00
Paul Walker 6457455248 [SVE] Use NEON for extract_vector_elt when the index is in range.
Patch also adds missing patterns for unpacked vector types and
extracts of element zero.

Differential Revision: https://reviews.llvm.org/D87842
2020-09-21 13:12:28 +01:00
Eduardo Caldas 87f0b51d68 [SyntaxTree][NFC] follow naming convention + remove auto on empty vector declaration
Differential Revision: https://reviews.llvm.org/D88004
2020-09-21 11:45:15 +00:00
Christian Sigg 9ba3b7449d [MLIR] Fix typo and expand gpu.host_register description.
See comments in https://reviews.llvm.org/D85631.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D86214
2020-09-21 13:44:39 +02:00
Haojian Wu 41a8bbad5e Fix buildbot.
TemplateArgumentLocInfo cannot result in a constant expression anymore
after D87080.
2020-09-21 13:40:00 +02:00
Alexander Belyaev 17dc729bd4 Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
This reverts commit 0345d88de6.

Google internal backend uses EntrySU, we are looking into removing
dependency on it.

Differential Revision: https://reviews.llvm.org/D88018
2020-09-21 13:33:05 +02:00
Haojian Wu af29591650 [AST] Reduce the size of TemplateArgumentLocInfo.
allocate the underlying data of Template kind separately, this would reduce AST
memory usage

- TemplateArgumentLocInfo 24 => 8 bytes
- TemplateArgumentLoc  48 => 32 bytes
- DynTypeNode 56 => 40 bytes

ASTContext::.getASTAllocatedMemory changes:
  SemaDecl.cpp 255.5 MB => 247.5MB
  SemaExpr.cpp 293.5 MB => 283.5MB

Differential Revision: https://reviews.llvm.org/D87080
2020-09-21 13:08:53 +02:00
Florian Hahn 11dccf8d3a Recommit "[SCEV] Look through single value PHIs."
This commit was originally because it was suspected to cause a crash,
but a reproducer did not surface.

A crash that was exposed by this change was fixed in 1d8f2e5292.

This reverts the revert commit 0581c0b0ee.
2020-09-21 11:59:50 +01:00
Benjamin Kramer 2d76274b99 [mlir][VectorOps] Loosen restrictions on vector.reduction types
LLVM can deal with any integer or float type, don't arbitrarily restrict
it to f32/f64/i32/i64.

Differential Revision: https://reviews.llvm.org/D88010
2020-09-21 12:45:23 +02:00
David Green f4c5cadbcb [ARM] Select f32 constants with vmov.f16
This adds lowering for f32 values using the vmov.f16, which zeroes the
top bits whilst setting the lower bits to a pattern. This range of
values does not often come up, except where a f16 constant value has
been converted to a f32.

Differential Revision: https://reviews.llvm.org/D87790
2020-09-21 11:10:47 +01:00
serge-sans-paille 2a77441117 Do not dereference an array out of bound just to take its address
This is UB by the standard, and caught by the libstdc++ asserts

Differential Revision: https://reviews.llvm.org/D87892
2020-09-21 12:08:30 +02:00
Georgii Rymar 095f6fbbd7 [llvm-readelf/obj] - Stop printing invalid names for unnamed section symbols.
We have an issue with `ELFDumper<ELFT>::getSymbolSectionName`:
1) It is used deeply for both LLVM/GNU styles and might return LLVM-style only
   values to describe symbols: "Undefined", "Processor Specific", "Absolute", etc.

2) `getSymbolSectionName` is used by `getFullSymbolName` and these special values
   might appear instead of symbol names in many places.
   This occurs for unnamed section symbols currently.

This patch extracts the LLVM specific logic to `LLVMStyle<ELFT>::printSymbolSection`,
which seems to be the only place where we want to print the special values mentioned.
It also adds a meaningful new warning that is reported when we are unable to get
a section index for a section symbol.

Differential revision: https://reviews.llvm.org/D87764
2020-09-21 13:05:46 +03:00
Sam Parker 13c73632c7 [NFC][ARM] More tail predication tests.
Add mir tests for use/def of P0.
2020-09-21 10:58:05 +01:00
Sjoerd Meijer 4b8ade837e [AArch64] Cortex-A55 scheduler model
This is an initial commit adding the A55 model, but it isn't used/enabled yet.
We will follow up on this to improve the model, then flip the switch.

The optimisation guide describing Cortex-A55 micro-architecture in more detail
can be found here:

https://static.docs.arm.com/epm128372/20/arm_cortex_a55_software_optimization_guide_v2.pdf

Original patch by Javed Absar.

Differential Revision: https://reviews.llvm.org/D46884
2020-09-21 10:54:32 +01:00
Tres Popp ffdd4a46a9 [mlir] Shape.AssumingOp implements RegionBranchOpInterface.
This adds support for the interface and provides unambigious information
on the control flow as it is unconditional on any runtime values.
The code is tested through confirming that buffer-placement behaves as
expected.

Differential Revision: https://reviews.llvm.org/D87894
2020-09-21 11:33:11 +02:00
Eduardo Caldas 4a5cc389c5 [SyntaxTree][Synthesis] Implement `deepCopy`
Differential Revision: https://reviews.llvm.org/D87749
2020-09-21 09:27:15 +00:00
Alex Richardson aa85c6f2a5 [compiler-rt] Fix atomic support functions on 32-bit architectures
The code currently uses __c11_atomic_is_lock_free() to detect whether an
atomic operation is natively supported. However, this can result in a
runtime function call to determine whether the given operation is lock-free
and clang generating a call to e.g. __atomic_load_8 since the branch is
not a constant zero. Since we are implementing those runtime functions, we
must avoid those calls. This patch replaces __c11_atomic_is_lock_free()
with __atomic_always_lock_free() which always results in a compile-time
constant value. This problem was found while compiling atomic.c for MIPS32
since the -Watomic-alignment warning was being triggered and objdump showed
an undefined reference to _atomic_is_lock_free.

In addition to fixing 32-bit platforms this also enables the 16-byte case
that was disabled in r153779 (185f2edd70).

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D86510
2020-09-21 10:21:11 +01:00
Alex Richardson 8cf6778d30 [RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
This does not result in changes for any of the current tests, but it might
improve debug information in some cases.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D86522
2020-09-21 10:21:11 +01:00
James Henderson fa6da90aef [lld][ELF][test] Add additional LTO testing
The additional testing is testing we previously had in a downstream test
suite.

Reviewed by: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D87824
2020-09-21 10:18:09 +01:00
Max Kazantsev 98aed8aa00 [Test] Test auto-update 2020-09-21 16:06:18 +07:00
Lucas Prates 53d238a961 [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder
SelectionDAGBuilder was inconsistently mangling values based on ABI
Calling Conventions when getting them through copyFromRegs in
SelectionDAGBuilder, causing duplicate value type convertions for
function arguments. The checking for the mangling requirement was based
on the value's originating instruction and was performed outside of, and
inspite of, the regular Calling Convention Lowering.

The issue could be observed in a scenario such as:

```
%arg1 = load half, half* %const, align 2
%arg2 = call fastcc half @someFunc()
call fastcc void @otherFunc(half %arg1, half %arg2)
; Here, %arg2 was incorrectly mangled twice, as the CallConv data from
; the call to @someFunc() was taken into consideration for the check
; when getting the value for processing the call to @otherFunc(...),
; after the proper convertion had taken place when lowering the return
; value of the first call.
```

This patch fixes the issue by disregarding the Calling Convention
information for such copyFromRegs, making sure the ABI mangling is
properly contanined in the Calling Convention Lowering.

This fixes Bugzilla #47454.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87844
2020-09-21 10:05:34 +01:00
Mehdi Amini 702f06ad14 Fix crash in the pass pipeline when local reproducer is enabled
This crash only happens when a function pass is followed by a module
pass. In this case the splitting of the pass pipeline didn't handle
properly the verifier passes and ended up with an odd number of pass in
the pipeline, breaking an assumption of the local crash reproducer
executor and hitting an assertion.

Differential Revision: https://reviews.llvm.org/D88000
2020-09-21 08:52:50 +00:00
Florian Hahn 57ae9bb932 [LSR] Preserve MSSA when using SplitCriticalEdge.
LSR claims to MemorySSA, but we also have to make sure it is preserved
when splitting critical edges. This can be done by passing MSSAU to
SplitCriticalEdge.

Fixes PR47557.
2020-09-21 09:51:26 +01:00
Andrzej Warzynski 4eae6fc95f [clang] Fix incorrect call to TextDiagnostic::printDiagnosticMessage
As per the documentation, the 2nd argument in printDiagnosticMessage
should be a bool that specifies whether the underlying message is a
continuation note diagnostic or not. More specifically, it should be:
```
Level == DiagnosticsEngine::Note
```
instead of:
```
Level
```

This change means that `no input file` in the following scenario will be
now correctly printed in bold:
```
$ bin/clang
clang: error: no input files
```
In terminals that don't support text formatting the behaviour doesn't
change.

Differential Revision: https://reviews.llvm.org/D87816
2020-09-21 09:41:39 +01:00
David Spickett 349af80542 [clang][AArch64] Correct return type of Neon vqmovun intrinsics
Neon intrinsics vqmovunh_s16, vqmovuns_s32, vqmovund_s64
should have unsigned return types.

See https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vqmovun

Fixes https://bugs.llvm.org/show_bug.cgi?id=46840

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D85118
2020-09-21 09:21:51 +01:00
Eduardo Caldas e616a42598 [SyntaxTree] Test for '\' inside token.
Differential Revision: https://reviews.llvm.org/D87895
2020-09-21 06:56:14 +00:00
Haojian Wu f8f1e5fb39 [AST] Fix dependence-bits for CXXDefaultInitExpr.
Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D87382
2020-09-21 08:47:01 +02:00
Eduardo Caldas bb5b28f12f [SyntaxTree][Synthesis] Improve testing `createLeaf`
The new test shows that `createLeaf` depends on the C++ version.

Differential Revision: https://reviews.llvm.org/D87896
2020-09-21 06:11:46 +00:00
Richard Smith aa769358d8 [c++20] Consistent with the intent to allow all plausible types in
non-type template parameters, permit vector types.
2020-09-20 23:09:26 -07:00
Mehdi Amini dabe679488 Add missing new line after debug logging in MLIRContext (NFC) 2020-09-21 05:55:44 +00:00
SuJunda 000eb1f314 [docs][flang] Fix typos
Reviewed By: SouraVX

Differential Revision: https://reviews.llvm.org/D87885
2020-09-21 11:05:58 +05:30
Fangrui Song dbc616e982 [EHStreamer] Fix a "Continue to action" -fverbose-asm comment when multi-byte LEB128 encoding is needed
This only happens with more than 64 action records and it is difficult to construct a test.
2020-09-20 21:41:48 -07:00
Jez Ng abd70fb398 [lld-macho] Export trie addresses should be relative to the image base
We didn't notice this earlier this we were only testing the export trie
encoded in a dylib, whose image base starts at zero. But a regular
executable contains `__PAGEZERO`, which means it has a non-zero image
base. This bug was discovered after attempting to run some programs that
performed `dlopen` on an executable.

Reviewed By: #lld-macho, smeenai

Differential Revision: https://reviews.llvm.org/D87780
2020-09-20 20:43:15 -07:00
Jez Ng 0a7e56f74c [lld-macho] Mark weak symbols in symbol table
Reviewed By: #lld-macho, smeenai

Differential Revision: https://reviews.llvm.org/D86908
2020-09-20 20:43:14 -07:00
Richard Smith 0cd73dbe2c [c++20] For P1907R1: Add checking for structural types for non-type
template parameters.

No support for the new kinds of non-type template argument yet.

This is not entirely NFC for prior language modes: we have historically
incorrectly accepted rvalue references as the types of non-type template
parameters. Such invalid code is now rejected.
2020-09-20 20:20:52 -07:00
Qiu Chaofan 1d782c2987 [PowerPC] Pass nofpexcept flag to custom lowered constrained ops
This is a follow-up of D86605. For strict DAG FP node, if its FP
exception behavior metadata is ignore, it should have nofpexcept flag.
But during custom lowering, this flag isn't passed down.

This is also seen on X86 target.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D87390
2020-09-21 10:44:25 +08:00
Pengxuan Zheng deb00cf0b5 [Polly][NewPM] Port Simplify to the new pass manager
Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D87328
2020-09-20 19:18:01 -07:00
Fangrui Song d06485685d [XRay] Change mips to use version 2 sled (PC-relative address)
Follow-up to D78590. All targets use PC-relative addresses now.

Reviewed By: atanasyan, dberris

Differential Revision: https://reviews.llvm.org/D87977
2020-09-20 17:59:57 -07:00
wlei a8b8a9374a [llvm-profdata]Fix llvm-profdata crash on compact binary profile
llvm-profdata `show` and `overlap` will crash in `getFuncName` on compact binary profile. This change fixed this by switching to use `getName`.

 `getFuncName` is misused in llvm-profdata. As showed below, `GUIDToFuncNameMap` is only supported in compilation mode, there is no initialization in llvm-profdata. Compact profile whose MD5 is true would try to query `GUIDToFuncNameMap` then caused the crash. So fix this by switching to `getName`

Reviewed By: MaskRay, wmi, wenlei, weihe, hoy

Differential Revision: https://reviews.llvm.org/D87740
2020-09-20 16:58:34 -07:00
Nathan Ridge 90a8c44d92 [clangd] Fix typo in field name
Differential Revision: https://reviews.llvm.org/D87995
2020-09-20 19:52:39 -04:00
Craig Topper a74b1faba2 [X86] Make reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore work for avx512 after type legalization.
The scalar elements of the vXi1 build_vector will have been type legalized to i8 by padding with 0s. So we can't check for all ones. Instead we should just look at bit 0 of the constant.

Differential Revision: https://reviews.llvm.org/D87863
2020-09-20 13:54:20 -07:00
Craig Topper c89b3af0e3 [X86] Pre-commit test cases for D87863. NFC 2020-09-20 13:53:05 -07:00
Craig Topper 4e8c028158 [X86] Stop reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore from creating scalar i64 load/stores in 32-bit mode
If we emit a scalar i64 load/store it will get type legalized to two i32 load/stores.

Differential Revision: https://reviews.llvm.org/D87862
2020-09-20 13:46:59 -07:00
Craig Topper 9b1c98c0fb [X86] Add 32-bit command lines to masked_store.ll and masked_load.ll 2020-09-20 13:46:59 -07:00
David Green 29bd8ea110 [ARM] Constant fold VMOVrh
This adds simple constant folding for VMOVrh, to constant fold fp16
constants to integer values. It can help especially with soft calling
conventions, but some of the results are not optimal as we end up
loading using a vldr. This will be improved in a follow up patch.

Differential Revision: https://reviews.llvm.org/D87789
2020-09-20 21:32:51 +01:00
Nikita Popov 1a27238098 [CVP] Additional tests for comparison with offset (NFC)
Both icmps have an additional offset here. We would fold this if
the second one didn't.
2020-09-20 22:10:34 +02:00
Nikita Popov 445db89b53 [LVI] Get value range from mask comparison
InstCombine likes to canonicalize comparisons of the form
X == C || X == C+1 into (X & -2) == C'. Make sure LVI can still
recover the value range from this. Can of course also be useful
for proper mask comparisons.

For the sake of clarity, the implementation goes through KnownBits
to compute the range.
2020-09-20 21:13:57 +02:00
Nikita Popov 91af6a78d0 [CVP] Add tests for mask comparisons (NFC) 2020-09-20 21:13:57 +02:00