Commit Graph

395253 Commits

Author SHA1 Message Date
Matheus Izvekov 0c7cd4a873 [clang] NFC: refactor multiple implementations of getDecltypeForParenthesizedExpr
This cleanup patch refactors a bunch of functional duplicates of
getDecltypeForParenthesizedExpr into a common implementation.

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: aaronpuchert

Differential Revision: https://reviews.llvm.org/D100713
2021-07-28 23:27:43 +02:00
Mehdi Amini 6e9e4b5a6a Revert "Emit strong definition for TypeID storage in Op/Type/Attributes definition"
This reverts commit 660a56956c.

This broke the GCC5 build
2021-07-28 21:07:56 +00:00
River Riddle f8479d9de5 [mlir] Set the namespace of the BuiltinDialect to 'builtin'
Historically the builtin dialect has had an empty namespace. This has unfortunately created a very awkward situation, where many utilities either have to special case the empty namespace, or just don't work at all right now. This revision adds a namespace to the builtin dialect, and starts to cleanup some of the utilities to no longer handle empty namespaces. For now, the assembly form of builtin operations does not require the `builtin.` prefix. (This should likely be re-evaluated though)

Differential Revision: https://reviews.llvm.org/D105149
2021-07-28 21:00:10 +00:00
Walter Erquinigo d52ba48821 [trace] Introduce Hierarchical Trace Representation (HTR) and add command for Intel PT trace visualization
This diff introduces Hierarchical Trace Representation (HTR) and creates the `thread trace export ctf  -f <filename> -t <thread_id>` command to export an Intel PT trace's HTR to Chrome Trace Format (CTF) for visualization.

See `lldb/docs/htr.rst` for context/documentation on HTR.

**Overview of Changes**
    - Add HTR documentation (see `lldb/docs/htr.rst`)
    - Add HTR structures (layer, block, block metadata)
    - Implement "Basic Super Block" HTR pass
    - Add 'thread trace export ctf' command to export the HTR of an Intel PT
      trace to Chrome Trace Format (CTF)

As this diff is the first iteration of HTR and trace visualization, future diffs will build on this work by generalizing the internal design of HTR and implementing new HTR passes that provide better trace summarization/visualization.

See attached video for an example of Intel PT trace visualization:
{F17851042}

Original Author: jj10306

Submitted by: wallace

Reviewed By: wallace, clayborg

Differential Revision: https://reviews.llvm.org/D105741
2021-07-28 13:56:45 -07:00
Michael Benfield e12e02df09 [clang] Evaluate strlen of strcpy argument for -Wfortify-source.
Also introduce Expr::tryEvaluateStrLen.

Differential Revision: https://reviews.llvm.org/D104887
2021-07-28 20:52:57 +00:00
Louis Dionne 6929bd6d00 [libc++] Add UNSUPPORTED for clang-14 since the underlying bug hasn't been fixed yet
This started breaking in the CI because we bumped the Clang version to 14,
which requires adjusting the markup in the test suite. I think it's actually
nice the we need to do that and that it doesn't happen automatically, since
it serves as a reminder that this is broken in Clang.
2021-07-28 16:41:22 -04:00
Muhammad Omair Javaid 4b88a94ebe Revert "[trace] Introduce Hierarchical Trace Representation (HTR) and add command for Intel PT trace visualization"
This reverts commit aad17c55a8.

Breaks LLDB build on 32 bit Arm/Linux bot:
https://lab.llvm.org/buildbot/#/builders/17/builds/9497

Differential Revision: https://reviews.llvm.org/D105741
2021-07-29 01:34:24 +05:00
Itai Zukerman 3ff451ca6a [Bazel] Added missing targets to LLVM bazel rules.
Added the following targets to the LLVM Bazel overlay:

AVR
Mips
MPS430
SystemZ
XCore

Reviewed By: GMNGeoffrey

Differential Revision: https://reviews.llvm.org/D106921
2021-07-28 13:32:18 -07:00
Geoffrey Martin-Noble 668aa531d6 [Bazel] Update for dbed061bf1
This adds Bazel configuration for the TargetMCA targets, which currently
only includes AMDGPU.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D106996
2021-07-28 13:24:16 -07:00
Fangrui Song 660b753e28 [ELF][test] Convert --start-address= and --stop-address= values to hexadecimal
so that readers can connect them with the hexadecimal addresses in the output.
2021-07-28 12:55:09 -07:00
Fangrui Song f17e7df04a [ELF][test] Delete unneeded --triple=thumb* from llvm-objdump RUN lines 2021-07-28 12:47:12 -07:00
bakhtiyar 6ea22d4626 Optionally eliminate blocking runtime.await calls by converting functions to coroutines.
Interop parallelism requires needs awaiting on results. Blocking awaits are bad for performance. TFRT supports lightweight resumption on threads, and coroutines are an abstraction than can be used to lower the kernels onto TFRT threads.

Reviewed By: ezhulenev

Differential Revision: https://reviews.llvm.org/D106508
2021-07-28 12:37:05 -07:00
zoecarver 0f4b41e038 [libcxx][ranges] Add ranges::take_view.
Differential Revision: https://reviews.llvm.org/D106507
2021-07-28 12:14:21 -07:00
Ellis Hoag f623dc9a8c [DebugInfo][docs] Fix DISubprogram fields
D45024 renamed the field in `DISubprogram` from `variables:` to
`retainedNodes:`. Some of the docs were updated in D89082 but this
updates the rest.

Reviewed By: scott.linder

Differential Revision: https://reviews.llvm.org/D106926
2021-07-28 12:09:19 -07:00
Fangrui Song 828767f325 COFF/ELF: Place llvm.global_ctors elements in llvm.used if comdat is used
On ELF, an SHT_INIT_ARRAY outside a section group is a GC root. The current
codegen abuses SHT_INIT_ARRAY in a section group to mean a GC root.

On PE/COFF, the dynamic initialization for `__declspec(selectany)` in a comdat
can be garbage collected by `-opt:ref`.

Call `addUsedGlobal` for the two cases to fix the abuse/bug.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D106925
2021-07-28 11:44:19 -07:00
Eli Friedman 4adcff0b70 [ARM] Fix llvm-objdump disassembly of armv7m object files.
Apparently, the features were getting mixed up, so we'd try to
disassemble in ARM mode. Fix sub-architecture detection to compute the
correct triple if we're detecting it automatically, so the user doesn't
need to pass --triple=thumb etc.

It's possible we should be somehow tying the "+thumb-mode" target
feature more directly to Tag_CPU_arch_profile? But this seems to work
reasonably well, anyway.

While I'm here, fix up the other llvm-objdump tests that were explicitly
specifying an ARM triple; that shouldn't be necessary.

Differential Revision: https://reviews.llvm.org/D106912
2021-07-28 11:41:54 -07:00
Mehdi Amini 660a56956c Emit strong definition for TypeID storage in Op/Type/Attributes definition
By making an explicit template specialization for the TypeID provided by these classes,
the compiler will not emit an inline weak definition and rely on the linker to unique it.
Instead a single definition will be emitted in the C++ file alongside the implementation
for these classes. That will turn into a linker error what is now a hard-to-debug runtime
behavior where instances of the same class may be using a different TypeID inside of
different DSOs.

Differential Revision: https://reviews.llvm.org/D105903
2021-07-28 18:37:05 +00:00
Mehdi Amini 6cba96332b Add some missing CMake dependencies between MLIR dialects (NFC) 2021-07-28 18:37:05 +00:00
Dmitry Vyukov da7a5c09c8 tsan: don't print __tsan_atomic* functions in report stacks
Currently __tsan_atomic* functions do FuncEntry/Exit using caller PC
and then use current PC (pointing to __tsan_atomic* itself) during
memory access handling. As the result the top function in reports
involving atomics is __tsan_atomic* and the next frame points to user code.

Remove FuncEntry/Exit in atomic functions and use caller PC
during memory access handling. This removes __tsan_atomic*
from the top of report stacks, so that they point right to user code.

The motivation for this is performance.
Some atomic operations are very hot (mostly loads),
so removing FuncEntry/Exit is beneficial.
This also reduces thread trace consumption (1 event instead of 3).

__tsan_atomic* at the top of the stack is not necessary
and does not add any new information. We already say
"atomic write of size 4", "__tsan_atomic32_store" does not add
anything new.

It also makes reports consistent between atomic and non-atomic
accesses. For normal accesses we say "previous write" and point
to user code; for atomics we say "previous atomic write" and now
also point to user code.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D106966
2021-07-28 20:34:46 +02:00
Dmitry Vyukov 170a8c1284 sanitizer_common: avoid compiler-interted memset in deadlock detector
Compilers tends to insert memset/memcpy for some struct/array operations,
and these don't play well inside of sanitizer runtimes.
Avoiding these calls was the intention behind internal_memset.
Remove the leftover ={} that can result in memset call.

Reviewed By: vitalybuka, pgousseau

Differential Revision: https://reviews.llvm.org/D106978
2021-07-28 20:27:38 +02:00
Dmitry Vyukov 9dad34423b tsan: strip __libc_start_main frame
We strip all frames below main but in some cases it may be not enough.
Namely, when main is instrumented but does not call any other instrumented code.
In this case __tsan_func_entry in main obtains PC pointing to __libc_start_main
(as we pass caller PC to __tsan_func_entry), but nothing obtains PC pointing
to main itself (as main does not call any instrumented code).
In such case we will not have main in the stack, and stripping everything
below main won't work.
So strip __libc_start_main explicitly as well.
But keep stripping of main because __libc_start_main is glibc/linux-specific,
so looking for main is more reliable (and usually main is present in stacks).

Depends on D106957.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D106958
2021-07-28 20:26:42 +02:00
Dmitry Vyukov 6563bb53b5 tsan: don't use caller/current PC in Java interfaces
Caller PC is plain harmful as native caller PC has nothing to do with Java code.
Current PC is not particularly useful and may be somewhat confusing for Java users
as it makes top frame to point to some magical __tsan function.
But obtaining and using these PCs adds runtime cost for every java event.
Remove these PCs. Rely only on official Java frames.
It makes execution faster, code simpler and reports better.

Depends on D106956.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D106957
2021-07-28 20:25:20 +02:00
Dmitry Vyukov 5237b14087 tsan: print alloc stack for Java objects
We maintain information about Java allocations,
but for some reason never printed it in reports.
Print it.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D106956
2021-07-28 20:25:11 +02:00
Patrick Holland dbed061bf1 [MCA] Moving the target specific CustomBehaviour impl. from /tools/llvm-mca/ to /lib/Target/.
Differential Revision: https://reviews.llvm.org/D106775
2021-07-28 11:23:18 -07:00
Dmitry Vyukov c4cb9b64dd tsan: add more micro benchmarks
1. Add a set of micro benchmarks for memory accesses,
   mem* functions and unaligned accesses.
2. Add support for multiple benchmarks in a single binary
   (or it would require 12 new benchmark binaries).
3. Remove the "clock growth" machinery,
   it affects the current tsan runtime by increasing size of
   all vector clocks, but this won't be relevant for the new
   tsan runtime.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D106961
2021-07-28 20:11:59 +02:00
Dmitry Vyukov b5bc386ca1 tsan: remove mblock types
We used to count number of allocations/bytes based on the type
and maybe record them in heap block headers.
But that's all in the past, now it's not used for anything.
Remove the mblock type.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D106971
2021-07-28 20:09:25 +02:00
Dmitry Vyukov 5acdfb7eda tsan: remove unused pc arguments
Remove pc argument of ThreadIgnoreEnd, ThreadIgnoreSyncEnd
and AcquireGlobal functions. It's unused and in some places
we don't even have a pc and pass 0 anyway.
Don't confuse readers and don't pretend that pc is needed
and that passing 0 is somehow deficient.

Use simpler convention for ThreadIgnoreBegin and ThreadIgnoreSyncBegin:
accept only pc instread of pc+save_stack. 0 pc means "don't save stack".

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D106973
2021-07-28 20:07:49 +02:00
Walter Erquinigo aad17c55a8 [trace] Introduce Hierarchical Trace Representation (HTR) and add command for Intel PT trace visualization
This diff introduces Hierarchical Trace Representation (HTR) and creates the `thread trace export ctf  -f <filename> -t <thread_id>` command to export an Intel PT trace's HTR to Chrome Trace Format (CTF) for visualization.

See `lldb/docs/htr.rst` for context/documentation on HTR.

**Overview of Changes**
    - Add HTR documentation (see `lldb/docs/htr.rst`)
    - Add HTR structures (layer, block, block metadata)
    - Implement "Basic Super Block" HTR pass
    - Add 'thread trace export ctf' command to export the HTR of an Intel PT
      trace to Chrome Trace Format (CTF)

As this diff is the first iteration of HTR and trace visualization, future diffs will build on this work by generalizing the internal design of HTR and implementing new HTR passes that provide better trace summarization/visualization.

See attached video for an example of Intel PT trace visualization:
{F17851042}

Original Author: jj10306

Submitted by: wallace

Reviewed By: wallace, clayborg

Differential Revision: https://reviews.llvm.org/D105741
2021-07-28 11:04:13 -07:00
Sjoerd Meijer bc43078fe8 [LoopFlatten] Fix bug where SCEVCouldNotCompute object is used
The SCEV method getBackedgeTakenCount() returns a SCEVCouldNotCompute
object if the backedge-taken count is unpredictable. This fix ensures
there is no longer an attempt to use such an object to find the trip
count.

Patch by: Rosie Sumpter.

Differential Revision: https://reviews.llvm.org/D106970
2021-07-28 18:35:08 +01:00
Jeroen Dobbelaere 03b8c69d06 [PredicateInfo] Use Intrinsic::getDeclaration now that it handles unnamed types.
This is a second attempt to fix the EXPENSIVE_CHECKS issue that was mentioned  In D91661#2875179 by @jroelofs.

(The first attempt was in D105983)

D91661 more or less completely reverted D49126 and by doing so also removed the cleanup logic of the created declarations and calls.
This patch is a replacement for D91661 (which must itself be reverted first). It replaces the custom declaration creation with the
generic version and shows the test impact. It also tracks the number of NamedValues to detect if a new prototype was added instead
of looking at the available users of a prototype.

Reviewed By: jroelofs

Differential Revision: https://reviews.llvm.org/D106147
2021-07-28 19:30:29 +02:00
Jeroen Dobbelaere dc5570d149 Revert "Revert of D49126 [PredicateInfo] Use custom mangling to support ssa_copy with unnamed types."
This reverts commit 77080a1eb6.

This change introduced issues detected with EXPENSIVE_CHECKS. Reverting to restore the
needed function cleanup. A next patch will then just improve on the name mangling.
2021-07-28 19:30:29 +02:00
Aaron Ballman 71f0359a9d Simplify allowing pragma float_control in a linkage specification
This amends b0ef3d8f66 based on a suggestion from James Y Knight.
2021-07-28 13:29:41 -04:00
Aart Bik 2b013a6c8a [mlir][sparse] use proper type alias for filename ptr
Reviewed By: gussmith23

Differential Revision: https://reviews.llvm.org/D106904
2021-07-28 10:25:24 -07:00
Mats Larsen 9812339005
[NFC] Test commit to verify commit access 2021-07-28 18:53:46 +02:00
Fangrui Song 6da3d8b19c [llvm] Replace LLVM_ATTRIBUTE_NORETURN with C++11 [[noreturn]]
[[noreturn]] can be used since Oct 2016 when the minimum compiler requirement was bumped to GCC 4.8/MSVC 2015.

Note: the definition of LLVM_ATTRIBUTE_NORETURN is kept for now.
2021-07-28 09:31:14 -07:00
Alex Zinenko 49f745f59c [mlir] run the verifier before translating a module
In translation from MLIR to another IR, run the MLIR verifier on the parsed
module to ensure only valid modules are given to the translation. Previously,
we would send any module that could be parsed to the translation, including
semantically invalid modules, leading to surprising errors or lack thereof down
the pipeline.

Depends On D106937

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D106938
2021-07-28 18:15:58 +02:00
Alex Zinenko c1f719d1a7 [mlir] harden result type verification in llvm.call
The verifier of the llvm.call operation was not checking for mismatches between
the number of operation results and the number of results in the signature of
the callee. Furthermore, it was possible to construct an llvm.call operation
producing an SSA value of !llvm.void type, which should not exist. Add the
verification and treat !llvm.void result type as absence of call results.
Update the GPU conversions to LLVM that were mistakenly assuming that it was
fine for llvm.call to produce values of !llvm.void type and ensure these calls
do not produce results.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D106937
2021-07-28 18:15:56 +02:00
Jessica Clarke 6e8660a7d6 [NFC][PowerPC] Fix spe.ll to work with update_llc_test_checks.py again
Using split-file does not work with update_llc_test_checks.py. It's also
mostly redundant, as the single and double tests can just use a single
llc and FileCheck invocation for each FPU type using -check-prefixes
rather than -check-prefix, and update_llc_test_checks.py will merge what
it can. Only test_dasmconst needs to be SPE-only and so is pulled out
into its own mall file (rather than using sed to preprocess the file and
keep it commented out for EFPU2, which would work, but is ugly).

As well as cutting down on the number of RUN lines, this also results in
test_fma's CHECK lines being merged for both FPUs.

Reviewed By: kiausch

Differential Revision: https://reviews.llvm.org/D106969
2021-07-28 17:13:05 +01:00
Raphael Isemann 83c752bfa6 Revert "[lldb] Temporarily bump the max length of the pexpect error message to diagnose an lldb-aarch64 test failure"
This reverts commit 5db8e23212. The test has
been disabled since then on the bot and we got the logs we wanted.
2021-07-28 18:11:52 +02:00
Craig Topper 3106f85945 [RISCV] Fix grammar in a comment. NFC 2021-07-28 09:09:26 -07:00
Craig Topper 54588bcc05 [RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop.
The sign_extend we insert here can get turned into a zero_extend if
the sign bit is known zero. This can enable a setcc combine that
shrinks compares with zero_extend. This reduces the use count of
the zero_extend allowing other combines to turn it back into an
any_extend.

This restricts the combine to only cases where the result is used
by a CopyToReg. This works for my original motivating case. I
hope the CopyToReg use will prevent any converted extends from
turning back into an any_extend.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D106754
2021-07-28 09:05:45 -07:00
Mark de Wever 4e65688571 [libc++][nfc] Improve error diagnostics.
The error message for disabled filesystem and locale support is now done
in the same fashion as ranges and format in D106763.

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D106935
2021-07-28 17:57:23 +02:00
Chris Jackson 3992896043 Revert "[DebugInfo][LoopStrengthReduction] SCEV-based salvaging for LSR"
Reverted due to buildbot failures.
This reverts commit d675b594f4.
2021-07-28 16:44:54 +01:00
Dmitry Vyukov bfb597b24c tsan: improve lots_of_threads test
The current 10 threads is not particularly "lots" and not stressful.
Create 10x300 threads and ensure they all are running at the same time.

Depends on D106953.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D106954
2021-07-28 17:36:06 +02:00
Dmitry Vyukov acbb4fcd5e tsan: increase max number of threads supported by test-only barrier
Currently the barrier supports only 256 threads,
this does not allow to write reliable tests that use more threads.
Bump max number of threads to 1024 to support writing
good stress tests.
Also replace sched_yield() with usleep(100) on the wait path.
If we write tests that create hundreds of threads (and dozens
of tests can run in parallel), yield would consume massive
amounts of CPU time for spinning.

Depends on D106952.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D106953
2021-07-28 17:35:23 +02:00
Dmitry Vyukov 9ef9d01a50 tsan: extend signal_malloc test
Test that we report the warning for free()
and ensure the test finishes as we usually do with "DONE".

Depends on D106951.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D106952
2021-07-28 17:35:13 +02:00
Dmitry Vyukov 89edd1e95f tsan: fix warnings in tests
Compilers don't like attributes in this position:

warning: GCC does not allow 'noinline' attribute in this position on a function definition
error: attributes are not allowed on a function-definition

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D106951
2021-07-28 17:35:02 +02:00
Chris Jackson d675b594f4 [DebugInfo][LoopStrengthReduction] SCEV-based salvaging for LSR
Reapply commit 796b84d26f that was
reverted due to reports of crashes. A minor change now guards against
getVariableLocationOperand() returning a nullptr.

Differential Revision: https://reviews.llvm.org/D106659
2021-07-28 16:28:46 +01:00
Sanjay Patel 5b83261c15 [DivRemPairs] make sure we have a valid CFG for hoisting division
This transform was added with e38b7e8948
and as shown in:
https://llvm.org/PR51241
...it could crash without an extra check of the blocks.

There might be a more compact way to write this constraint,
but we can't just count the successors/predecessors without
affecting a test that includes a switch instruction.
2021-07-28 11:09:12 -04:00
Guillaume Chatelet d3c70d9f77 [libc] Simplify implementation of benchmarks
This also allows to run the distribution benchmarks in other frameworks
like the Google Benchmark facility.
2021-07-28 15:04:19 +00:00