Commit Graph

288367 Commits

Author SHA1 Message Date
Paul Semel ee5be798da [llvm-objcopy] Add --globalize-symbol option
llvm-svn: 331068
2018-04-27 19:09:44 +00:00
Ben Hamilton 345f8739d8 [clang-format/ObjC] Use getIdentifierInfo() instead of tok::identifier
Summary:
Previously, we checked tokens for `tok::identifier` to see if they
were identifiers inside an Objective-C selector.

However, this missed C++ keywords like `new` and `delete`.

To fix this, this diff uses `getIdentifierInfo()` to find
identifiers or keywords inside Objective-C selectors.

Test Plan: New tests added. Ran tests with:
  % make -j16 FormatTests && ./tools/clang/unittests/Format/FormatTests

Reviewers: djasper, jolesiak

Reviewed By: djasper

Subscribers: klimek, cfe-commits

Differential Revision: https://reviews.llvm.org/D46143

llvm-svn: 331067
2018-04-27 18:51:12 +00:00
Jun Bum Lim 47aece1344 [CodeGen] Use RegUnits to track register aliases (NFC)
Summary: Use RegUnits to track register aliases in PostRASink and AArch64LoadStoreOptimizer.

Reviewers: thegameg, mcrosier, gberry, qcolombet, sebpop, MatzeB, t.p.northover, javed.absar

Reviewed By: thegameg, sebpop

Subscribers: javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45695

llvm-svn: 331066
2018-04-27 18:44:37 +00:00
Simon Pilgrim 8a937e00d8 [X86] Split WriteFBlend/WriteFVarBlend/WriteFVarShuffle into XMM and YMM/ZMM scheduler classes
This removes all the WriteFBlend/WriteFVarBlend InstRW overrides - some WriteFVarShuffle remain to be fixed.

llvm-svn: 331065
2018-04-27 18:19:48 +00:00
Rafael Espindola f1652d4c60 Split .eh_frame sections in parellel.
We can now split them in the same spot we split merge sections.

llvm-svn: 331064
2018-04-27 18:17:36 +00:00
Bruno Cardoso Lopes fbff2fafb3 [Modules][ObjC] ASTReader should add protocols for class extensions
During deserialization clang is currently missing the merging of
protocols into the canonical interface for the class extension.

This merging only currently happens during parsing and should also
be considered during deserialization.

rdar://problem/38724303

llvm-svn: 331063
2018-04-27 18:01:23 +00:00
Mark Searles a6322924e6 [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
Differential Revision: https://reviews.llvm.org/D46154

llvm-svn: 331062
2018-04-27 17:59:15 +00:00
Philip Reames de5a1da2d2 [GuardWidening] Add some clarifying comments about heuristics [NFC]
llvm-svn: 331061
2018-04-27 17:41:37 +00:00
Philip Reames 9258e9d190 [LoopGuardWidening] Split out a loop pass version of GuardWidening
The idea is to have a pass which performs the same transformation as GuardWidening, but can be run within a loop pass manager without disrupting the pass manager structure.  As demonstrated by the test case, this doesn't quite get there because of issues with post dom, but it gives a good step in the right direction.  the motivation is purely to reduce compile time since we can now preserve locality during the loop walk.

This patch only includes a legacy pass.  A follow up will add a new style pass as well.

llvm-svn: 331060
2018-04-27 17:29:10 +00:00
Sanjay Patel f6d595bd44 [docs] add fp-cast-overflow-workaround options to release notes
llvm-svn: 331059
2018-04-27 16:33:35 +00:00
Rafael Espindola 9bf1006278 Split merge sections early.
Now that getSectionPiece is fast (uses a hash) it is probably OK to
split merge sections early.

The reason I want to do this is to split eh_frame sections in the same
place.

This does mean that we have to decompress early. Given that the only
compressed sections are debug info, I don't think we are missing much.

It is a small improvement: 0.5% on the geometric mean.

llvm-svn: 331058
2018-04-27 16:29:57 +00:00
Sanjay Patel c1ecbf261f [docs] more dashes
llvm-svn: 331057
2018-04-27 16:24:39 +00:00
Sanjay Patel cee47befe4 [docs] add -ffp-cast-overflow-workaround to the release notes
This option was added with:
D46135
rL331041
...copying the text from UsersManual.rst for more exposure.

llvm-svn: 331056
2018-04-27 16:21:22 +00:00
Nirav Dave 6b01b88012 [MC] Undo spurious commit added into r331052.
llvm-svn: 331055
2018-04-27 16:16:06 +00:00
Simon Pilgrim c3c767bf50 [X86] Split WriteFHadd into XMM and YMM/ZMM scheduler classes
This removes all the HADD/HSUB PS/PD InstRW overrides.

llvm-svn: 331054
2018-04-27 16:11:57 +00:00
Stuart Brady a38f573ad0 Test commit removing trailing whitespace
llvm-svn: 331053
2018-04-27 16:11:56 +00:00
Nirav Dave 38b4b54a2c [MC] Provide default value for IsResolved.
llvm-svn: 331052
2018-04-27 16:11:24 +00:00
Simon Pilgrim b2aa89c909 [X86][AVX] Split WriteFLogic into XMM and YMM/ZMM scheduler classes
This removes all the AND/ANDN/OR/XOR PS/PD InstRW overrides.

llvm-svn: 331051
2018-04-27 15:50:33 +00:00
Simon Dardis e3c3c5a7a7 [mips] Analyze and provide selection patterns microMIPSR6 branches
These branches were previously unanalyzable and unselectable. Add them and
recognize how to generate their inverses.

Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D46113

llvm-svn: 331050
2018-04-27 15:49:49 +00:00
Greg Clayton 776cd7ad44 Always normalize FileSpec paths.
Always normalizing lldb_private::FileSpec paths will help us get a consistent results from comparisons when setting breakpoints and when looking for source files. This also removes a lot of complexity from the comparison routines. Modified the DWARF line table parser to use the normalized compile unit directory if needed.

Differential Revision: https://reviews.llvm.org/D45977

llvm-svn: 331049
2018-04-27 15:45:58 +00:00
Nirav Dave 1b5533c9e8 [MC] Modify MCAsmStreamer to always build MCAssembler. NFCI.
llvm-svn: 331048
2018-04-27 15:45:54 +00:00
Nirav Dave 8728e097df [MC] Allow MCAssembler to be constructed without all subcomponents. NFCI.
llvm-svn: 331047
2018-04-27 15:45:27 +00:00
Zaara Syeda 82dd99e08e [PPC64] Add offset to local entry point when calling functions without plt
PPC64 V2 ABI describes two entry points to a function. The global entry point
sets up the TOC base pointer. When calling a local function, the call should
branch to the local entry point rather than the global entry point.
Section 3.4.1 describes using the 3 most significant bits of the st_other
field to find out how many instructions there are between the local and global
entry point. This patch adds the correct offset required to branch to the local
entry point of a function.

Differential Revision: https://reviews.llvm.org/D45729

llvm-svn: 331046
2018-04-27 15:41:19 +00:00
Rui Ueyama 50bf643cfb Do not set RequiresNullTerminator. NFC.
When reading object files, we don't need '\0' at end of each file.

llvm-svn: 331045
2018-04-27 15:32:04 +00:00
Francis Visoiu Mistrih c855e92ca9 [AArch64] Place the first ldp at the end when ReverseCSRRestoreSeq is true
Put the first ldp at the end, so that the load-store optimizer can run
and merge the ldp and the add into a post-index ldp.

This didn't work in case no frame was needed and resulted in code size
regressions.

llvm-svn: 331044
2018-04-27 15:30:54 +00:00
Frederic Riss ffb8d8711c Mark test as @skipIfOutOfTreeDebugserver
This test will currently fail for people using the system debugserver.

llvm-svn: 331043
2018-04-27 15:30:09 +00:00
Kostya Kortchinsky 03b7c4dabb [CMake] Enable warnings for runtimes
Summary:
`HandleLLVMOptions` adds `-w` to the cflags if `LLVM_ENABLE_WARNINGS` is not on.
With `-w`, `check_cxx_compiler_flag` doesn't error out for unsupported flags
(for example `-mcrc` on x86_64), and those flags end up being detected as
working - and really they aren't.

I am not entirely sure what the best way to solve this is, but setting
`LLVM_ENABLE_WARNINGS` prior to including `HandleLLVMOptions` does the job.

Reviewers: phosek, beanz

Reviewed By: phosek

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D46079

llvm-svn: 331042
2018-04-27 15:10:50 +00:00
Sanjay Patel d175476566 [Driver, CodeGen] add options to enable/disable an FP cast optimization
As discussed in the post-commit thread for:
rL330437 ( http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20180423/545906.html )

We need a way to opt-out of a float-to-int-to-float cast optimization because too much 
existing code relies on the platform-specific undefined result of those casts when the 
float-to-int overflows.

The LLVM changes associated with adding this function attribute are here:
rL330947
rL330950
rL330951

Also as suggested, I changed the LLVM doc to mention the specific sanitizer flag that 
catches this problem:
rL330958

Differential Revision: https://reviews.llvm.org/D46135

llvm-svn: 331041
2018-04-27 14:22:48 +00:00
Jonas Paulsson 9a485985cd [SystemZ] Remove scheduling info from some Pseudo instructions (NFC).
If the MachineInstr uses a custom inserter and is then erased after
instruction selection, there is no use for mapping it to a sched class.

Review: Ulrich Weigand
llvm-svn: 331040
2018-04-27 14:09:03 +00:00
Oliver Stannard 2fcee8bd52 [ARM,AArch64] Add intrinsics for dot product instructions
The ACLE spec which describes these intrinsics hasn't been published yet, but
this is based on the final draft which will be published soon, and these have
already been implemented by GCC.

Differential revision: https://reviews.llvm.org/D46109

llvm-svn: 331039
2018-04-27 14:03:32 +00:00
Oliver Stannard 39ee9de64c [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro
This adds a pre-defined macro to test if the compiler has support for the
v8.2-A dot rpoduct intrinsics in AArch32 mode.

The AAcrh64 equivalent has already been added by rL330229.

The ACLE spec which describes this macro hasn't been published yet, but this is
based on the final internal draft, and GCC has already implemented this.

Differential revision: https://reviews.llvm.org/D46108

llvm-svn: 331038
2018-04-27 13:56:02 +00:00
Florian Hahn f3fea0f11f [LoopInterchange] Allow some loops with PHI nodes in the exit block.
We currently support LCSSA PHI nodes in the outer loop exit, if their
incoming values do not come from the outer loop latch or if the
outer loop latch has a single predecessor. In that case, the outer loop latch
will be executed only if the inner loop gets executed. If we have multiple
predecessors for the outer loop latch, it may be executed even if the inner
loop does not get executed.

This is a first step to support the case described in
https://bugs.llvm.org/show_bug.cgi?id=30472

Reviewers: efriedma, karthikthecool, mcrosier

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D43237

llvm-svn: 331037
2018-04-27 13:52:51 +00:00
Oliver Stannard 76088a5929 [AArch64] Codegen for v8.2A dot product intrinsics
This adds IR intrinsics for the AArch64 dot-product instructions introduced in
v8.2-A.

Differential revisioon: https://reviews.llvm.org/D46107

llvm-svn: 331036
2018-04-27 13:45:32 +00:00
Benjamin Kramer 733c7fc55d [NVPTX] Turn on Loop/SLP vectorization
Since PTX has grown a <2 x half> datatype vectorization has become more
important. The late LoadStoreVectorizer intentionally only does loads
and stores, but now arithmetic has to be vectorized for optimal
throughput too.

This is still very limited, SLP vectorization happily creates <2 x half>
if it's a legal type but there's still a lot of register moving
happening to get that fed into a vectorized store. Overall it's a small
performance win by reducing the amount of arithmetic instructions.

I haven't really checked what the loop vectorizer does to PTX code, the
cost model there might need some more tweaks. I didn't see it causing
harm though.

Differential Revision: https://reviews.llvm.org/D46130

llvm-svn: 331035
2018-04-27 13:36:05 +00:00
Simon Pilgrim aef5ca7299 [X86] Replace some system instruction instregex single matches with instrs entry. NFCI.
llvm-svn: 331034
2018-04-27 13:32:42 +00:00
Aleksandar Beserminji 3546c1603a [mips] Fix how compiler fuse instructions to fmadd/fmsub
This patch makes compiler does not fuse fmul and fadd/fsub into
fmadd/fmsub by default. Instead, -fp-contract=fast option can
be used when such behavior is desired.

Differential Revision: https://reviews.llvm.org/D46057

llvm-svn: 331033
2018-04-27 13:30:27 +00:00
Oliver Stannard f3632143da [ARM] Codegen for v8.2A dot product intrinsics
This adds IR intrinsics for the ARM dot-product instructions introduced in
v8.2-A.

Differential revision: https://reviews.llvm.org/D46106

llvm-svn: 331032
2018-04-27 12:50:40 +00:00
Sam McCall a4962cce49 [clangd] Fix unicode handling, using UTF-16 where LSP requires it.
Summary:
The Language Server Protocol unfortunately mandates that locations in files
be represented by line/column pairs, where the "column" is actually an index
into the UTF-16-encoded text of the line.
(This is because VSCode is written in JavaScript, which is UTF-16-native).

Internally clangd treats source files at UTF-8, the One True Encoding, and
generally deals with byte offsets (though there are exceptions).

Before this patch, conversions between offsets and LSP Position pretended
that Position.character was UTF-8 bytes, which is only true for ASCII lines.
Now we examine the text to convert correctly (but don't actually need to
transcode it, due to some nice details of the encodings).

The updated functions in SourceCode are the blessed way to interact with
the Position.character field, and anything else is likely to be wrong.
So I also updated the other accesses:
 - CodeComplete needs a "clang-style" line/column, with column in utf-8 bytes.
   This is now converted via Position -> offset -> clang line/column
   (a new function is added to SourceCode.h for the second conversion).
 - getBeginningOfIdentifier skipped backwards in UTF-16 space, which is will
   behave badly when it splits a surrogate pair. Skipping backwards in UTF-8
   coordinates gives the lexer a fighting chance of getting this right.
   While here, I clarified(?) the logic comments, fixed a bug with identifiers
   containing digits, simplified the signature slightly and added a test.

This seems likely to cause problems with editors that have the same bug, and
treat the protocol as if columns are UTF-8 bytes. But we can find and fix those.

Reviewers: hokein

Subscribers: klimek, ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits

Differential Revision: https://reviews.llvm.org/D46035

llvm-svn: 331029
2018-04-27 11:59:28 +00:00
Alex Bradbury f5800a2aa0 [RISCV] Add remat.ll test case
This test case demonstrates suboptimal codegen due to the fact that simple 
constants aren't recognised as rematerialisable.

llvm-svn: 331028
2018-04-27 11:50:30 +00:00
David Green c4cccea4c9 [ARM] Enable misched for R52.
Back when the R52 schedule was added in rL286949, there was no way
to enable machine schedules in ARM for specific cores. Since then a
target feature has been added. This enables the feature for R52,
removing the need to manually specify compiler flags.

llvm-svn: 331027
2018-04-27 11:29:49 +00:00
Sven van Haastregt 4700faa28e [OpenCL] Add separate read_only and write_only pipe IR types
SPIR-V encodes the read_only and write_only access qualifiers of pipes,
so separate LLVM IR types are required to target SPIR-V.  Other backends
may also find this useful.

These new types are `opencl.pipe_ro_t` and `opencl.pipe_wo_t`, which
replace `opencl.pipe_t`.

This replaces __get_pipe_num_packets(...) and __get_pipe_max_packets(...)
which took a read_only pipe with separate versions for read_only and
write_only pipes, namely:

 * __get_pipe_num_packets_ro(...)
 * __get_pipe_num_packets_wo(...)
 * __get_pipe_max_packets_ro(...)
 * __get_pipe_max_packets_wo(...)

These separate versions exist to avoid needing a bitcast to one of the
two qualified pipe types.

Patch by Stuart Brady.

Differential Revision: https://reviews.llvm.org/D46015

llvm-svn: 331026
2018-04-27 10:37:04 +00:00
Mikhail Maltsev ffaa8a8781 [IR] Do not assume that function pointers are aligned
Summary:
The value tracking analysis uses function alignment to infer that the
least significant bits of function pointers are known to be zero.
Unfortunately, this is not correct for ARM targets: the least
significant bit of a function pointer stores the ARM/Thumb state
information (i.e., the LSB is set for Thumb functions and cleared for
ARM functions).

The original approach (https://reviews.llvm.org/D44781) introduced a
new field for function pointer alignment in the DataLayout structure
to address this. But it seems unlikely that optimizations based on
function pointer alignment would bring much benefit in practice to
justify the additional maintenance burden, so this patch simply
assumes that function pointer alignment is always unknown.

Reviewers: javed.absar, efriedma

Reviewed By: efriedma

Subscribers: kristof.beyls, llvm-commits, hfinkel, rogfer01

Differential Revision: https://reviews.llvm.org/D46110

llvm-svn: 331025
2018-04-27 09:12:12 +00:00
Petar Jovanovic d4349f3bf6 [mips] Add support for Virtualization ASE
This includes

  Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall
                mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0,

  Assembler directives: .set virt, .set novirt, .module virt, .module novirt

  Attribute: virt

  .MIPS.abiflags: VZ (0x100)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D44905

llvm-svn: 331024
2018-04-27 09:12:08 +00:00
Dmitry Vyukov 21dc68fe7b tsan: improve "destroy of a locked mutex" reports
1. Allow to suppress by current stack.
We generally allow to suppress by all main stacks.
Current is probably the stack one wants to use to
suppress such reports.

2. Fix last lock stack restoration.
We trimmed shadow value by storing it in u32.
This magically worked for the test that provoked
the report on the main thread. But this breaks
for locks in any other threads.

llvm-svn: 331023
2018-04-27 08:59:35 +00:00
Serguei Katkov 1956a48d27 [SCEV] Add trivial case handling for umin utilities. NFC.
Reviewers: sanjoy, mkazantsev
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46175

llvm-svn: 331022
2018-04-27 08:02:50 +00:00
Raphael Isemann 0d24edab02 Make MultiplexASTDeserializationListener part of the API [NFC]
Summary:
This patch moves the MultiplexASTDeserializationListener declaration into a public header.

We're currently using this multiplexer in the cling interpreter to attach another
ASTDeserializationListener during the execution (so, after the MultiplexConsumer is already
attached which prevents us from attaching more). So far we're doing this by patching clang
and making this class public, but it makes things easier if we make this instead just public in
upstream.

Reviewers: thakis, v.g.vassilev, rsmith, bruno

Reviewed By: bruno

Subscribers: llvm-commits, cfe-commits, v.g.vassilev

Differential Revision: https://reviews.llvm.org/D37475

llvm-svn: 331021
2018-04-27 07:05:40 +00:00
Akira Hatanaka ccda3d2970 [CodeGen] Avoid destructing a callee-destructued struct type in a
function if a function delegates to another function.

Fix a bug introduced in r328731, which caused a struct with ObjC __weak
fields that was passed to a function to be destructed twice, once in the
callee function and once in another function the callee function
delegates to. To prevent this, keep track of the callee-destructed
structs passed to a function and disable their cleanups at the point of
the call to the delegated function.

This reapplies r331016, which was reverted in r331019 because it caused
an assertion to fail in EmitDelegateCallArg on a windows bot. I made
changes to EmitDelegateCallArg so that it doesn't try to deactivate
cleanups for structs that have trivial destructors (cleanups for those
structs are never pushed to the cleanup stack in EmitParmDecl).

rdar://problem/39194693

Differential Revision: https://reviews.llvm.org/D45382

llvm-svn: 331020
2018-04-27 06:57:00 +00:00
Akira Hatanaka b4f3637cec Revert "[CodeGen] Avoid destructing a callee-destructued struct type in a"
This reverts commit r331016, which broke a windows bot.

http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/11727

llvm-svn: 331019
2018-04-27 05:56:55 +00:00
Fangrui Song 1f3e2b2966 [ELF] Fix typo. NFC
llvm-svn: 331018
2018-04-27 05:50:40 +00:00
Richard Smith 3b8ccd5dbc Fix typo.
llvm-svn: 331017
2018-04-27 04:27:26 +00:00