ecef1d9cbc
[Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding.
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The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes.
Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware.
This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register.
llvm-svn: 261006
2016-02-16 20:38:17 +00:00
7cd0892729
[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.
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llvm-svn: 252443
2015-11-09 04:07:48 +00:00
05da79d5ac
[Hexagon] Remove the remnants of isConstExtProfitable
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llvm-svn: 250845
2015-10-20 19:04:53 +00:00
7c9587136d
[Hexagon] Adding skeleton of HVX extension instructions.
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llvm-svn: 250600
2015-10-17 01:33:04 +00:00
79ec06525e
[Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing intrinsic parameters to appropriate width.
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llvm-svn: 239634
2015-06-12 19:57:32 +00:00
1e9d1d768c
[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.
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llvm-svn: 239477
2015-06-10 16:52:32 +00:00
be8c453d58
[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
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llvm-svn: 239161
2015-06-05 16:00:11 +00:00
c40be85adc
Revert r239095 incorrect test tree.
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llvm-svn: 239102
2015-06-04 21:32:42 +00:00
fc52c11d80
[Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements.
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llvm-svn: 239095
2015-06-04 21:16:16 +00:00
55bdeb7bc7
[Hexagon] Use constant extenders to fix up hardware loops
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Use a loop instruction with a constant extender for a hardware
loop instruction that is too far away from the start of the loop.
This is cheaper than changing the SA register value.
Differential Revision: http://reviews.llvm.org/D9262
llvm-svn: 235882
2015-04-27 14:16:43 +00:00
a29622a8c5
Remove unused complex patterns for addressing modes on Hexagon.
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llvm-svn: 232057
2015-03-12 16:44:50 +00:00
6d5a4b5dcd
Eliminate constant-extender profitability checks from Hexagon isel
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llvm-svn: 231992
2015-03-12 00:19:59 +00:00
4fd203d3e1
[Hexagon] Removing more V4 predicates since V4 is the required minimum.
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llvm-svn: 228614
2015-02-09 21:56:37 +00:00
5149135369
[Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms.
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llvm-svn: 228220
2015-02-04 22:36:28 +00:00
987b0943c8
[Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them.
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llvm-svn: 228184
2015-02-04 20:38:01 +00:00
202f22bbda
Migrate HexagonISelDAGToDAG to setting a subtarget pointer during
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runOnMachineFunction. Update all uses of the Subtarget accordingly.
llvm-svn: 227840
2015-02-02 19:22:03 +00:00
19ed07c75a
[Hexagon] Deleting a lot of old variants of intrinsics and updating references.
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llvm-svn: 227338
2015-01-28 18:29:11 +00:00
9327bdad2f
[Hexagon] Converting remaining ALU32/ALU intrinsics.
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llvm-svn: 226480
2015-01-19 18:33:58 +00:00
68b2e050f0
[Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
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llvm-svn: 225283
2015-01-06 19:03:20 +00:00
1445553474
[Hexagon] Adding dealloc_return encoding and absolute address stores.
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llvm-svn: 225267
2015-01-06 16:15:15 +00:00
af1e5de141
[Hexagon] Adding classes and load unsigned byte instruction, updating usages.
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llvm-svn: 224730
2014-12-22 21:20:03 +00:00
d9a00a9c38
[Hexagon] Adding doubleword multiplies with and without accumulation.
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llvm-svn: 224293
2014-12-16 00:07:24 +00:00
5929cfc534
Move all operand definitions into HexagonOperands.td
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llvm-svn: 169213
2012-12-04 05:00:31 +00:00
c86b3e1b26
Define unsigned const-ext predicates.
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llvm-svn: 169149
2012-12-03 20:39:45 +00:00
6aba56e9d4
Removing unnecessary 'else' statement from the predicates defined in HexagonOperards.td.
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llvm-svn: 169148
2012-12-03 20:14:38 +00:00
014dfe4de0
Define signed const-ext predicates.
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llvm-svn: 169117
2012-12-03 06:54:50 +00:00
519b3856dd
Define signed const-ext immediate operands and their predicates.
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llvm-svn: 168810
2012-11-28 20:58:14 +00:00
b5bb659d50
Fix comments in HexagonOperands.td.
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llvm-svn: 168617
2012-11-26 21:56:51 +00:00
0df99bd2e4
Add new predicates for the immediate operands.
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llvm-svn: 168451
2012-11-21 20:05:09 +00:00
3ec3a49432
Use one common 'let' expression to set PrintMethod for all immediate operands.
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llvm-svn: 168449
2012-11-21 19:53:42 +00:00
b90c5f12f0
Finish the renaming.
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llvm-svn: 168437
2012-11-21 16:56:33 +00:00
6c0a3550c8
Renamed HexagonImmediates.td -> HexagonOperands.td.
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llvm-svn: 168434
2012-11-21 16:28:18 +00:00
Colin LeMahieu