Commit Graph

238 Commits

Author SHA1 Message Date
Krzysztof Parzyszek 7c7bb538cb [Hexagon] Treat all conditional branches as predicted (not-taken by default)
llvm-svn: 268946
2016-05-09 18:22:07 +00:00
Craig Topper 6e6a1f0a5b [Hexagon] Set ctlz_zero_undef/cttz_zero_undef to Expand so LegalizeDAG will convert them to ctlz/cttz. Remove the now unneccessary isel patterns. NFC
llvm-svn: 267266
2016-04-23 02:49:31 +00:00
Colin LeMahieu ecef1d9cbc [Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding.
The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes.

Another way is to put a .word32 and mix code and data within a function.  The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware.

This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits.  Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register.

llvm-svn: 261006
2016-02-16 20:38:17 +00:00
Krzysztof Parzyszek 7d5b4db7f9 [Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
We can generate the actual instructions from the intrinsics without the
need for pseudo-instructions. Also, since the intrinsics have a side-
effect in a form of a store, attempt to optimize away loads from the
store location.

llvm-svn: 260690
2016-02-12 17:01:51 +00:00
Krzysztof Parzyszek 7b413c6c63 [Hexagon] Use general purpose registers to spill pred/mod registers into
Patch by Tobias Edler Von Koch.

llvm-svn: 258527
2016-01-22 19:15:58 +00:00
Krzysztof Parzyszek 2d0418e842 [Hexagon] Add system instructions for cache manipulation
llvm-svn: 256936
2016-01-06 14:22:22 +00:00
Krzysztof Parzyszek 21dc8bdd9e [Hexagon] Add PIC support
llvm-svn: 256025
2015-12-18 20:19:30 +00:00
Colin LeMahieu 3c7ecf9af1 [Hexagon] Adding instruction aliases and tests.
llvm-svn: 252579
2015-11-10 01:58:26 +00:00
Krzysztof Parzyszek 26b2c9080f [Hexagon] Fix isNVStorable flag in .td files
An upper half and a double word cannot be used as value sources in a
new-value store.

llvm-svn: 250867
2015-10-20 22:40:57 +00:00
Krzysztof Parzyszek 05da79d5ac [Hexagon] Remove the remnants of isConstExtProfitable
llvm-svn: 250845
2015-10-20 19:04:53 +00:00
Colin LeMahieu 7c9587136d [Hexagon] Adding skeleton of HVX extension instructions.
llvm-svn: 250600
2015-10-17 01:33:04 +00:00
Sergey Dmitrouk 842a51bad8 Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"
[DebugInfo] Add debug locations to constant SD nodes

This adds debug location to constant nodes of Selection DAG and updates
all places that create constants to pass debug locations
(see PR13269).

Can't guarantee that all locations are correct, but in a lot of cases choice
is obvious, so most of them should be. At least all tests pass.

Tests for these changes do not cover everything, instead just check it for
SDNodes, ARM and AArch64 where it's easy to get incorrect locations on
constants.

This is not complete fix as FastISel contains workaround for wrong debug
locations, which drops locations from instructions on processing constants,
but there isn't currently a way to use debug locations from constants there
as llvm::Constant doesn't cache it (yet). Although this is a bit different
issue, not directly related to these changes.

Differential Revision: http://reviews.llvm.org/D9084

llvm-svn: 235989
2015-04-28 14:05:47 +00:00
Daniel Jasper 48e93f7181 Revert "[DebugInfo] Add debug locations to constant SD nodes"
This breaks a test:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870

llvm-svn: 235987
2015-04-28 13:38:35 +00:00
Sergey Dmitrouk adb4c69d5c [DebugInfo] Add debug locations to constant SD nodes
This adds debug location to constant nodes of Selection DAG and updates
all places that create constants to pass debug locations
(see PR13269).

Can't guarantee that all locations are correct, but in a lot of cases choice
is obvious, so most of them should be. At least all tests pass.

Tests for these changes do not cover everything, instead just check it for
SDNodes, ARM and AArch64 where it's easy to get incorrect locations on
constants.

This is not complete fix as FastISel contains workaround for wrong debug
locations, which drops locations from instructions on processing constants,
but there isn't currently a way to use debug locations from constants there
as llvm::Constant doesn't cache it (yet). Although this is a bit different
issue, not directly related to these changes.

Differential Revision: http://reviews.llvm.org/D9084

llvm-svn: 235977
2015-04-28 11:56:37 +00:00
Krzysztof Parzyszek 952d951418 [Hexagon] Some cleanup of instruction selection code
llvm-svn: 235552
2015-04-22 21:17:00 +00:00
Krzysztof Parzyszek cd97c985c7 [Hexagon] Use A2_tfrsi for constant pool and jump table addresses
llvm-svn: 235535
2015-04-22 18:25:53 +00:00
Krzysztof Parzyszek 4fa2a9f7fd [Hexagon] Overhaul of stack object allocation
- Use static allocation for aligned stack objects.
- Simplify dynamic stack object allocation.
- Simplify elimination of frame-indices.

llvm-svn: 235521
2015-04-22 16:43:53 +00:00
Krzysztof Parzyszek a29622a8c5 Remove unused complex patterns for addressing modes on Hexagon.
llvm-svn: 232057
2015-03-12 16:44:50 +00:00
Krzysztof Parzyszek 6d5a4b5dcd Eliminate constant-extender profitability checks from Hexagon isel
llvm-svn: 231992
2015-03-12 00:19:59 +00:00
Colin LeMahieu bdc6c83d24 [Hexagon] Adding frame index + add load/store patterns.
llvm-svn: 231850
2015-03-10 21:24:13 +00:00
Colin LeMahieu 092d9c18a8 [Hexagon] Adding DuplexInst instruction format and duplex class defs.
llvm-svn: 231828
2015-03-10 19:53:14 +00:00
Colin LeMahieu 3b6747df13 [Hexagon] Adding nodes for vector insert/extract lowering.
llvm-svn: 231825
2015-03-10 19:40:03 +00:00
Colin LeMahieu ee776452f9 [Hexagon] Renaming HexagonJT to JT and adding CP for constantpool.
llvm-svn: 231824
2015-03-10 19:29:53 +00:00
Colin LeMahieu fa79110cc7 [Hexagon] Removing unused patterns.
llvm-svn: 231723
2015-03-09 23:08:46 +00:00
Colin LeMahieu 7b1799c7f8 [Hexagon] Use single tailcall pseudoinst and fix checking for label jumping versus tail calling.
llvm-svn: 231713
2015-03-09 22:05:21 +00:00
Colin LeMahieu 2efa2d01d7 [Hexagon] Reapply r231699. Remove assumption that second operand is an immediate when checking if A2_tfrsi is combinable.
llvm-svn: 231710
2015-03-09 21:48:13 +00:00
Colin LeMahieu ed853397c6 [Hexagon] Reverting r231699
llvm-svn: 231703
2015-03-09 21:19:02 +00:00
Colin LeMahieu 8c4dfaa13b [Hexagon] Updating constant set to simpler versions.
llvm-svn: 231699
2015-03-09 20:33:12 +00:00
Colin LeMahieu 542510925b [Hexagon] Removing old halfword codegen instructions and updating const32/64 splitting.
llvm-svn: 231695
2015-03-09 20:11:02 +00:00
Colin LeMahieu 96bfaa9766 [Hexagon] Eliminating immediate condition set.
llvm-svn: 231693
2015-03-09 19:57:18 +00:00
Colin LeMahieu d46aeffc54 [Hexagon] Removing TFR_condset_ir/TFR_condset_ri modeling.
llvm-svn: 231689
2015-03-09 19:31:25 +00:00
Colin LeMahieu 63adf969a5 [Hexagon] Changing AddrFI back to ADDRri to address test issue.
llvm-svn: 231687
2015-03-09 18:57:33 +00:00
Colin LeMahieu bd8d0f3108 [Hexagon] Adding PackHL nodes and some missing modeling instructions and patterns
llvm-svn: 231678
2015-03-09 18:34:05 +00:00
Colin LeMahieu 404d5b242d [Hexagon] Adding vector load with post-increment instructions. Adding decoder function for 64bit control register class.
llvm-svn: 228708
2015-02-10 16:59:36 +00:00
Colin LeMahieu 641c24b9bf [Hexagon] Removing v2-4 flags. V4 is the minimum supported version.
llvm-svn: 228605
2015-02-09 21:07:35 +00:00
Colin LeMahieu 955c4ff9c3 [Hexagon] Factoring classes out of store patterns.
llvm-svn: 228602
2015-02-09 20:33:46 +00:00
Colin LeMahieu 6b3aac8ad9 [Hexagon] Deleting unused patterns.
llvm-svn: 228348
2015-02-05 21:43:56 +00:00
Colin LeMahieu de68b66b4d [Hexagon] Simplifying and formatting several patterns. Changing a pattern multiply to be expanded.
llvm-svn: 228347
2015-02-05 21:13:25 +00:00
Colin LeMahieu 99c5ce1ce4 [Hexagon] Factoring a class out of some store patterns, deleting unused definitions and reformatting some patterns.
llvm-svn: 228345
2015-02-05 20:38:58 +00:00
Colin LeMahieu d40bb5353d [Hexagon] Factoring out a class for immediate transfers and cleaning up formatting.
llvm-svn: 228343
2015-02-05 20:08:52 +00:00
Colin LeMahieu b882f2b5cf [Hexagon] Renaming Y2_barrier. Fixing issues where doubleword variants of instructions can't be newvalue producers.
llvm-svn: 228330
2015-02-05 18:56:28 +00:00
Colin LeMahieu 27d50073b3 [Hexagon] Renaming A2_subri, A2_andir, A2_orir. Fixing formatting.
llvm-svn: 228326
2015-02-05 18:38:08 +00:00
Colin LeMahieu f297dbed48 [Hexagon] Renaming A2_addi and formatting.
llvm-svn: 228318
2015-02-05 17:49:13 +00:00
Colin LeMahieu a66cf6f2df [Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by default and remove explicitly setting it.
llvm-svn: 228316
2015-02-05 17:32:17 +00:00
Colin LeMahieu ceebe8659b [Hexagon] Deleting unused instructions and adding isCodeGenOnly to some defs.
llvm-svn: 228238
2015-02-05 00:10:16 +00:00
Colin LeMahieu 510ba0c661 [Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them to asm parse but not cause decode conflicts.
llvm-svn: 228080
2015-02-04 00:07:26 +00:00
Colin LeMahieu e4101e2c9e [Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1.
llvm-svn: 228050
2015-02-03 22:09:51 +00:00
Colin LeMahieu 99cc7c1070 [Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests.
llvm-svn: 228010
2015-02-03 19:15:11 +00:00
Colin LeMahieu cefca69d72 [Hexagon] Adding vector shift instructions and tests.
llvm-svn: 227619
2015-01-30 21:58:46 +00:00
Colin LeMahieu cc4329b836 [Hexagon] Adding vector predicate instructions.
llvm-svn: 227613
2015-01-30 21:24:06 +00:00