Commit Graph

6 Commits

Author SHA1 Message Date
David Green d96161a179 [ARM/AArch64] Move REQUIRES after update_cc_test_checks line. NFC
c17d9b4b12 added REQUIRES lines to a lot of Arm and AArch64
test, but added them to the very beginning, before the existing
update_cc_test_checks lines. This just moves them later so as to not
mess up the existing ordering when the checks are regenerated.
2021-11-13 19:09:01 +00:00
Saleem Abdulrasool c17d9b4b12 headers: optionalise some generated resource headers
This splits out the generated headers and conditonalises them upon the
target being enabled.

The motivation here is that the RISCV header alone added 10MB to the
resource directory, which was previously at 10MB, increasing the build
size and time. This header is contributing ~50% of the size of the
resource headers (~10MB).

The ARM generated headers are contributing about ~10% or 1MB.

This could be extended further adding only the static resource headers
for the targets that the LLVM build supports.

The changes to the tests for ARM mirror what the RISCV target already
did and rnk identified as a possible issue.

Testing:
  cmake -G Ninja -D LLVM_TARGETS_TO_BUILD=X86 -D LLVM_ENABLE_PROJECTS="clang;lld" ../clang
  ninja check-clang

Differential Revision: https://reviews.llvm.org/D112890
Reviewed By: craig.topper
2021-11-09 22:30:29 +00:00
Ivan A. Kosarev 1b7851212b [NEON] Define fp16 vld and vst intrinsics conditionally
This patch fixes definitions of vld and vst NEON intrinsics so
that we only define them if half-precision arithmetic is
supported on the target platform, as prescribed in ACLE 2.0.

Differential Revision: https://reviews.llvm.org/D49075

llvm-svn: 340140
2018-08-19 16:30:57 +00:00
Ivan A. Kosarev ff08ea77b5 [NEON] Define half-precision vmaxnm intrinsics only when available
Differential Revision: https://reviews.llvm.org/D49375

llvm-svn: 337704
2018-07-23 16:01:35 +00:00
Ivan A. Kosarev 26037539e4 [NEON] Define half-precision vrnd intrinsics only when available
Differential Revision: https://reviews.llvm.org/D49376

llvm-svn: 337699
2018-07-23 14:53:44 +00:00
Silviu Baranga 3102a01258 [ARM] Guard the declarations of f16 to f32 vcvt intrinsics in arm_neon.h by testing __ARM_FP
Summary:
Conversions between float and half are only available when the
taraget has the half-precision extension. Guard these intrinsics
so that they don't cause crashes in the backend.

Fixes PR27550.

Reviewers: rengolin, t.p.northover

Subscribers: cfe-commits, aemerson, t.p.northover, rengolin

Differential Revision: http://reviews.llvm.org/D19665

llvm-svn: 268047
2016-04-29 15:03:32 +00:00