Commit Graph

331834 Commits

Author SHA1 Message Date
Reid Kleckner a36f316390 Forward declare Optional<T> in STLExtras.h
WIP stats
2019-11-13 16:34:00 -08:00
Stanislav Mekhanoshin af7d4022c7 [AMDGPU] Fixed mfma-loop test. NFC. 2019-11-13 16:03:54 -08:00
Jonas Devlieghere 8ac053eea2 [LLDB] Cleanup the DataEncoder utility. (NFC)
This commit removes unused methods from the DataEncoder class and cleans
up the API by making all the internal methods private.
2019-11-13 15:44:51 -08:00
Reid Kleckner bfe663ce22 Revert a hunk from 9634064cfa
This causes errors when building LLDB because the Windows implementation
doesn't implement this method:

C:\src\llvm-project\lldb\source\Plugins\ScriptInterpreter\Python\ScriptInterpreterPython.cpp(915,19): error: allocating an object of abstract class type 'lldb_private::ConnectionGenericFile'
              new ConnectionGenericFile(read_file, true));
                  ^
C:\src\llvm-project\lldb\include\lldb/Utility/Connection.h(174,28): note: unimplemented pure virtual method 'GetReadObject' in 'ConnectionGenericFile'
  virtual lldb::IOObjectSP GetReadObject() = 0;
                           ^
2019-11-13 15:43:54 -08:00
Jonas Devlieghere 33c3e0b96c [LLDB] Implement pure virtual method in MockConnection
I made GetReadObject pure virtual in the base class and forgot to add
the method to the mock class.
2019-11-13 15:37:57 -08:00
Reid Kleckner 364d1785a6 Sink MachineFunction private method out of line
This method is private and only called from this file and doesn't need
to be inline. Saves a TargetMachine.h include in MachineFunction.h, a
popular header. The include was introduced in 98603a8153 despite the
forward decl of LLVMTargetMachine.
2019-11-13 15:36:58 -08:00
Craig Topper 188d92b947 [X86] Don't treat mxcsr as a register name when parsing MS inline assembly.
No instruction takes mxcsr as a an operand so we should always
treat it as an identifier name.
2019-11-13 15:26:18 -08:00
Jonas Devlieghere 9634064cfa [LLDB] Fix another set of -Wdocumentation warnings
At this point I'm just fixing issues as I see them pop up locally in
incremental builds.
2019-11-13 15:13:06 -08:00
Jonas Devlieghere 95807cb039 [LLDB] Remove dead code from StreamFile 2019-11-13 15:08:51 -08:00
Davide Italiano 294ef766e8 [RegisterContext] Remove now unneded vestiges. 2019-11-13 14:53:13 -08:00
Jonas Devlieghere 8df482e51c [LLDB] Fix a bunch of -Wdocumentation warnings in ExpressionParser 2019-11-13 14:40:55 -08:00
Adrian Prantl 9072f0103b Remove redundant check. (NFC) 2019-11-13 14:19:01 -08:00
Adrian Prantl 7f9d36e2db Use cheaper, equivalent predicate. (NFC) 2019-11-13 14:16:40 -08:00
Craig Topper f7e9d81a8e [X86] Don't set the operation action for i16 SINT_TO_FP to Promote just because SSE1 is enabled.
Instead do custom promotion in the handler so that we can still
allow i16 to be used with fp80. And f64 without sse2.
2019-11-13 14:07:56 -08:00
Craig Topper 787595b2e7 [X86] Fix typo in comment. NFC 2019-11-13 14:07:55 -08:00
Craig Topper fee9067261 [X86] Move all the FP_TO_XINT/XINT_TO_FP setOperationActions into the same !useSoftFloat block. Qualify all of the Promote actions for these with !useSoftFloat too. NFCI
The Promote action doesn't apply until LegalizeDAG. By the time
we get there, we would have already softened all the FP operations
if useSoftFloat was true. So there wouldn't be any operation left
to Promote.
2019-11-13 14:07:54 -08:00
Adrian Prantl 3d30c142e1 Rename clang-module-related *DWO* functions to *ClangModule* (NFC)
This avoids confusing them with fission-related functionality.

I also moved two accessor functions from DWARFDIE into static
functions in DWARFASTParserClang were their only use is located.
2019-11-13 14:07:20 -08:00
Hiroshi Yamauchi 3f0969daf9 [PGO][PGSO] Temporarily disable the large working set size behavior.
Summary:
This temporarily disables the large working set size behavior in profile guided
size optimization due to internal benchmark regressions.

Reviewers: davidxl

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70207
2019-11-13 14:00:47 -08:00
Marek Kurdej d94f63758a libc++ status page: Fix HTML. 2019-11-13 22:51:29 +01:00
Sanjay Patel be08af8816 [SimplifyCFG] add test for select with FMF; NFC 2019-11-13 16:45:42 -05:00
Adrian Prantl 78586775f7 Rename ParseTypeFromDWO to ParseTypeFromClangModule (NFC)
Because that is what this function really does. The old name is
misleading.
2019-11-13 13:37:43 -08:00
Richard Smith aeaddf926a Revert "[RISCV] Use compiler-rt if no GCC installation detected"
This change causes test failures for builds configured with
-DCLANG_DEFAULT_RTLIB=compiler-rt.

This reverts commit 3289352e6b.
2019-11-13 13:14:57 -08:00
Sanjay Patel a3e61946c5 [SLP] fix miscompile on min/max reductions with extra uses (PR43948)
The bug manifests as replacing a reduction operand with an undef
value.

The problem appears to be limited to cases where a min/max reduction
has extra uses of the compare operand to the select.

In the general case, we are tracking "ExternallyUsedValues" and
an "IgnoreList" of the reduction operations, but those may not apply
to the final compare+select in a min/max reduction.

For that, we use replaceAllUsesWith (RAUW) to ensure that the new
vectorized reduction values are transferred to all subsequent users.

Differential Revision: https://reviews.llvm.org/D70148
2019-11-13 15:57:35 -05:00
mydeveloperday 52980576ee [clang-format] refactor the use of the SMDiagnostics in replacement warnings
Summary:
Review comments in {D69854} recommended a simpler approach of creating the SMDiagnostics to remove much of the complexity. (thanks @thakis)

@vlad.tsyrklevich I've rebuilt on both Windows and Linux (running Linux with Address and Undefined sanitizers) over the clang code base

Reviewers: thakis, klimek, mitchell-stellar, vlad.tsyrklevich

Reviewed By: thakis

Subscribers: cfe-commits, thakis, vlad.tsyrklevich

Tags: #clang-format, #clang

Differential Revision: https://reviews.llvm.org/D69921
2019-11-13 20:55:44 +00:00
Martin Storsjö 38bc9559ba [LLD] [COFF] Fix automatically importing data symbols from DLLs with LTO
This broke in 51dcb292cc, "[lld-link] diagnose undefined symbols
before LTO when possible" (very soon after the 9.0 branch, so
luckily the 9.0 release is unaffected).

The code for loading objects we believe might be needed for autoimport
(loadMinGWAutomaticImports()) does run before the new
reportUnresolvable() function, but it had a condition to only operate
on symbols from regular object files. This condition came from
resolveRemainingUndefines(), but as loadMinGWAutomaticImports() now
has to operate before the LTO, it has to operate on undefineds from
LTO objects as well.

Differential Revision: https://reviews.llvm.org/D70166
2019-11-13 22:48:36 +02:00
Dimitry Andric 597b77fb7f Add -disable-builtin option to opt
Summary:
The option allows to disable specific target library builtin functions,
instead of -disable-simplify-libcalls, which disables all of them.

This is a prerequisite for D70143, which fixes PR43081.

Reviewers: xbolva00, spatel, jdoerfert, efriedma

Reviewed By: efriedma

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70193
2019-11-13 21:32:49 +01:00
Jonas Devlieghere ad882774fe [LLDB] Fix a bunch of -Wdocumentation warnings 2019-11-13 12:28:10 -08:00
Francis Visoiu Mistrih 3dfe4cf982 [dsymutil] Add -dump to llvm-bcanalyzer invocations 2019-11-13 12:27:26 -08:00
Craig Topper 84e83b54bd [TargetLowering] Increase the storage size of NumRegistersForVT to allow the type break down for v256i1 and other types to be stored correctly
v256i1 on X86 without avx512 breaks down to 256 i8 values when passed between basic blocks. But the NumRegistersForVT was sized at a byte for each VT. This results in 256 being stored as 0.

This patch enlarges the type to 16 bits and adds an assert to ensure that no information is lost when the entry is stored.

Differential Revision: https://reviews.llvm.org/D70138
2019-11-13 12:09:35 -08:00
Simon Atanasyan 63bbbcde9f [mips] Reduce number of nested `if` statements. NFC 2019-11-13 22:57:55 +03:00
Simon Atanasyan 14d3162285 [mips] Add test to check ELF output for JAL XGOT expansion. NFC 2019-11-13 22:57:55 +03:00
Simon Atanasyan 3216d28449 [mips] Add tests to check `jal sym+offset`. NFC 2019-11-13 22:57:54 +03:00
Quentin Colombet de94cda81b [LiveInterval] Allow updating subranges with slightly out-dated IR
During register coalescing, we update the live-intervals on-the-fly.
To do that we are in this strange mode where the live-intervals can
be slightly out-of-sync (more precisely they are forward looking)
compared to what the IR actually represents.
This happens because the register coalescer only updates the IR when
it is done with updating the live-intervals and it has to do it this
way because updating the IR on-the-fly would actually clobber some
information on how the live-ranges that are being updated look like.

This is problematic for updates that rely on the IR to accurately
represents the state of the live-ranges. Right now, we have only
one of those: stripValuesNotDefiningMask.
To reconcile this need of out-of-sync IR, this patch introduces a
new argument to LiveInterval::refineSubRanges that allows the code
doing the live range updates to reason about how the code should
look like after the coalescer will have rewritten the registers.
Essentially this captures how a subregister index with be offseted
to match its position in a new register class.

E.g., let say we want to merge:
    V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32>

We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32>
overlap, i.e., by choosing a class where we can find "offset + 1 == 3".
Put differently we align V2's sub3 with V1's sub1:
    V2: sub0 sub1 sub2 sub3
    V1: <offset>  sub0 sub1

This offset will look like a composed subregidx in the the class:
     V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
 =>  V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>

Now if we didn't rewrite the uses and def of V1, all the checks for V1
need to account for this offset to match what the live intervals intend
to capture.

Prior to this patch, we would fail to recognize the uses and def of V1
and would end up with machine verifier errors: No live segment at def.
This could lead to miscompile as we would drop some live-ranges and
thus, miss some interferences.

For this problem to trigger, we need to reach stripValuesNotDefiningMask
while having a mismatch between the IR and the live-ranges (i.e.,
we have to apply a subreg offset to the IR.)

This requires the following three conditions:
1. An update of overlapping subreg lanes: e.g., dsub0 == <ssub0, ssub1>
2. An update with Tuple registers with a possibility to coalesce the
   subreg index: e.g., v1.dsub_1 == v2.dsub_3
3. Subreg liveness enabled.

looking at the IR to decide what is alive and what is not, i.e., calling
stripValuesNotDefiningMask.
coalescer maintains for the live-ranges information.

None of the targets that currently use subreg liveness (i.e., the targets
that fulfill #3, Hexagon, AMDGPU, PowerPC, and SystemZ IIRC) expose #1 and
and #2, so this patch also artificial enables subreg liveness for ARM,
so that a nice test case can be attached.
2019-11-13 11:17:56 -08:00
Michael Liao 2bf9b9a5a3 [TTI] Fix cast cost on vector types.
- Only split vector types when both src and dst types are splittable.
2019-11-13 13:54:07 -05:00
Francis Visoiu Mistrih 1ca85b3d33 [llvm-bcanalyzer] Don't dump the contents if -dump is not passed
With all the previous refactorings this slipped through and now we
always dump the contents of the bitcode files, even if -dump is not
passed.
2019-11-13 10:38:57 -08:00
Ahmed Bougacha 7313d7d618 [AArch64][v8.3a] Add missing imp-defs on RETA*.
RETA always implicitly uses LR, unlike RET which merely has an
alias that defaults it to LR.
Additionally, RETA implicitly uses SP as well, which it uses as
a discriminator to authenticate LR.

This isn't usually noticeable, because RET_ReallyLR is used in most
of the backend.  However, the post-RA scheduler, if enabled, will
cause miscompiles if the imp-uses are missing.

While there, fix a typo in the lone affected testcase.
2019-11-13 10:38:11 -08:00
Ahmed Bougacha 643ac6c042 [AArch64][v8.3a] Add LDRA '[xN]!' alias.
The instruction definition has been retroactively expanded to
allow for an alias for '[xN, 0]!' as '[xN]!'.
That wouldn't make sense on LDR, but does for LDRA.
2019-11-13 10:38:11 -08:00
Sanjay Patel 142cbe73e9 [SLP] improve test readability; NFC 2019-11-13 12:59:00 -05:00
Yonghong Song 1583158042 [BPF] fix clang test failure for bpf-attr-preserve-access-index-4.c
Depending on different cmake configures, clang may generate different
IR name for slot variables. Let us use the regex instead of hard
coding the name. I did the same for other bpf-attr-preserve-access-index
tests with such an approach, but somehow did not do for this one.
2019-11-13 09:40:57 -08:00
Edward Jones 3289352e6b [RISCV] Use compiler-rt if no GCC installation detected
If a GCC installation is not detected, then this attempts to
use compiler-rt and the compiler-rt crtbegin/crtend
implementations as a fallback.

Differential Revision: https://reviews.llvm.org/D68407
2019-11-13 17:18:33 +00:00
David Stenberg 7417cc149b Fix typo in DwarfDebug [NFC] 2019-11-13 18:06:16 +01:00
David Tenty 8b2b2c08d9 Don't set LLVM_NO_DEAD_STRIP on AIX
Summary:
when building plugins, as AIX has symbols in it's standard library that
must be garbage collected or we will see link errors. Export lists will
handle this instead on AIX.

Reviewers: stevewan, sfertile, jasonliu, xingxue, DiggerLin

Reviewed By: DiggerLin

Subscribers: mgorny, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70130
2019-11-13 11:59:47 -05:00
Yonghong Song f5824799f6 [BPF] add missing attribute in pragma-attribute-supported-attributes-list.test
Add the newly supported BPF specific __attribute__((preserve_access_index)
in the pragma-attribute-supported-attributes-list.test.
2019-11-13 08:50:42 -08:00
Sanjay Patel e9bf7a60a0 [SLP] reduce code duplication for min/max vs. other reductions; NFCI 2019-11-13 11:26:08 -05:00
Yonghong Song 4e2ce228ae [BPF] Add preserve_access_index attribute for record definition
This is a resubmission for the previous reverted commit
9434360401 with the same subject. This commit fixed the
segfault issue and addressed additional review comments.

This patch introduced a new bpf specific attribute which can
be added to struct or union definition. For example,
  struct s { ... } __attribute__((preserve_access_index));
  union u { ... } __attribute__((preserve_access_index));
The goal is to simplify user codes for cases
where preserve access index happens for certain struct/union,
so user does not need to use clang __builtin_preserve_access_index
for every members.

The attribute has no effect if -g is not specified.

When the attribute is specified and -g is specified, any member
access defined by that structure or union, including array subscript
access and inner records, will be preserved through
  __builtin_preserve_{array,struct,union}_access_index()
IR intrinsics, which will enable relocation generation
in bpf backend.

The following is an example to illustrate the usage:
  -bash-4.4$ cat t.c
  #define __reloc__ __attribute__((preserve_access_index))
  struct s1 {
    int c;
  } __reloc__;

  struct s2 {
    union {
      struct s1 b[3];
    };
  } __reloc__;

  struct s3 {
    struct s2 a;
  } __reloc__;

  int test(struct s3 *arg) {
    return arg->a.b[2].c;
  }
  -bash-4.4$ clang -target bpf -g -S -O2 t.c

A relocation with access string "0:0:0:0:2:0" will be generated
representing access offset of arg->a.b[2].c.

forward declaration with attribute is also handled properly such
that the attribute is copied and populated in real record definition.

Differential Revision: https://reviews.llvm.org/D69759
2019-11-13 08:23:44 -08:00
Matthew Malcomson e5f3760e8c Fix comment spelling {addresing -> addressing} (NFC) 2019-11-13 16:14:32 +00:00
Vedant Kumar e7aab320b1 [profile] Factor out logic for mmap'ing merged profile, NFC
Split out the logic to get the size of a merged profile and to do a
compatibility check. This can be shared with both the continuous+merging
mode implementation, as well as the runtime-allocated counters
implementation planned for Fuchsia.

Lifted out of D69586.

Differential Revision: https://reviews.llvm.org/D70135
2019-11-13 07:52:15 -08:00
Sanjay Patel 3d6b53980c [InstCombine] propagate fast-math-flags (FMF) to select when inverting fcmp+select
As noted by the FIXME comment, this is not correct based on our current FMF semantics.
We should be propagating FMF from the final value in a sequence (in this case the
'select'). So the behavior even without this patch is wrong, but we did not allow FMF
on 'select' until recently.

But if we do the correct thing right now in this patch, we'll inevitably introduce
regressions because we have not wired up FMF propagation for 'phi' and 'select' in
other passes (like SimplifyCFG) or other places in InstCombine. I'm not seeing a
better incremental way to make progress.

That said, the potential extra damage over the existing wrong behavior from this
patch is very limited. AFAIK, the only way to have different FMF on IR in the same
function is if we have LTO inlined IR from 2 modules that were compiled using
different fast-math settings.

As seen in the tests, we may actually see some improvements with this patch because
adding the FMF to the 'select' allows matching to min/max intrinsics that were
previously missed (in the common case, the 'fcmp' and 'select' should have identical
FMF to begin with).

Next steps in the transition:

    Make similar changes in instcombine as needed.
    Enable phi-to-select FMF propagation in SimplifyCFG.
    Remove dependencies on fcmp with FMF.
    Deprecate FMF on fcmp.

Differential Revision: https://reviews.llvm.org/D69720
2019-11-13 10:38:42 -05:00
Pavel Labath 1eea3fa063 DWARFDebugLoclists: Add an api to get the location lists of a DWARF unit
Summary:
This avoid the need to duplicate the location lists searching logic in
various users. The "inline location list dumping" code (which is the
only user actually updated to handle DWARF v5 location lists)  is
switched to this method. After adding v4 location list support, I'll
switch other users too.

Reviewers: dblaikie, probinson, JDevlieghere, aprantl, SouraVX

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70084
2019-11-13 16:26:16 +01:00
Simon Pilgrim e84b7a5fe2 Remove commented out CHECK-NEXT to try and appease llvm-clang-x86_64-expensive-checks-win buildbot 2019-11-13 14:59:12 +00:00