Commit Graph

180240 Commits

Author SHA1 Message Date
Manuel Klimek edf925b935 Mark successors as reachable/unreachable instead of changing the CFG.
As suggested by Ted, this makes a few warnings less aggressive.

llvm-svn: 215128
2014-08-07 18:44:19 +00:00
Justin Bogner 1b9f936f91 FileCheck: Add a flag to allow checking empty input
Currently FileCheck errors out on empty input. This is usually the
right thing to do, but makes testing things like "this command does
not emit some error message" hard to test. This usually leads to
people using "command 2>&1 | count 0" instead, and then the bots that
use guard malloc fail a few hours later.

By adding a flag to FileCheck that allows empty inputs, we can make
tests that consist entirely of "CHECK-NOT" lines feasible.

llvm-svn: 215127
2014-08-07 18:40:37 +00:00
Joerg Sonnenberger f74c74693c Indent
llvm-svn: 215126
2014-08-07 18:05:32 +00:00
Adam Nemet 2e2537f665 [AVX512] Generate masking instruction variants with tablegen
After adding the masking variants to several instructions, I have decided to
experiment with generating these from the non-masking/unconditional
variant. This will hopefully reduce the amount repetition that we currently
have in order to define an instruction with all its variants (for a reg/mem
instruction this would be 6 instruction defs and 2 Pat<> for the intrinsic).

The patch is the first cut that is currently only applied to valignd/q to make
the patch small.

A few notes on the approach:

  * In order to stitch together the dag for both the conditional and the
  unconditional patterns I pass the RHS of the set rather than the full
  pattern (set dest, RHS).
  * Rather than subclassing each instruction base class (e.g. AVX512AIi8),
  with a masking variant which wouldn't scale, I derived the masking
  instructions from a new base class AVX512 (this is just I<> with
  Requires<HasAVX512>).  The instructions derive from this now, plus a new set
  of classes that add the format bits and everything else that instruction
  base class provided (i.e. AVX512AIi8 vs. AVX512AIi8Base).

I hope we can go incrementally from here.  I expect that:

  * We will need different variants of the masking class.  One example is
  instructions requiring three vector sources.  In this case we tie one of the
  source operands to dest rather than a new implicit source operand ($src0)
  * Add the zero-masking variant
  * Add more AVX512*Base classes as new uses are added

I've looked at X86.td.expanded before and after to make sure that nothing got
lost for valignd/q.

llvm-svn: 215125
2014-08-07 17:53:55 +00:00
Zachary Turner 3f55974024 Optimizations for FileSpec.
llvm-svn: 215124
2014-08-07 17:33:36 +00:00
Zachary Turner df62f20c75 Fix FileSpec to be able to understand Windows paths.
This patch adds the notion of a "path syntax" to FileSpec.  There
are two syntaxes (Posix and Windows) and one "meta syntax",
Host Native, which uses the current platform to figure out the
appropriate syntax for host paths.

This allows paths from one platform to be represented and
manipulated on another platform even if they have different path
syntaxes.

llvm-svn: 215123
2014-08-07 17:33:07 +00:00
NAKAMURA Takumi 17ae2fca4c llvm/test/tools/llvm-objdump: Reorganize target-dependent some tests.
llvm-svn: 215122
2014-08-07 17:17:19 +00:00
Johannes Doerfert 2ef3f4fd23 Make used analysis passes explicit
Use the explicit analysis if possible, only for splitBlock we will continue
  to use the Pass * argument. This change allows us to remove the getAnalysis
  calls from the code generation.

llvm-svn: 215121
2014-08-07 17:14:54 +00:00
Manuel Klimek cadc603e91 Fix CFG for temporary dtors when the branch taken is known.
Use the parent context when visiting temporaries when we do not insert a
temporary dtor decision branch.

llvm-svn: 215120
2014-08-07 17:02:21 +00:00
Zachary Turner c349434010 Fix the build broken as a result of deleting jit from LLVM.
llvm-svn: 215119
2014-08-07 16:50:45 +00:00
Manuel Klimek 7c03013c8b Model temporary destructors from logical operators with known values.
If the truth value of a LHS is known, we can build the knowledge whether
a temporary destructor is executed or not into the CFG. This is needed
by the return type analysis.

llvm-svn: 215118
2014-08-07 16:05:51 +00:00
Rafael Espindola a3ddbc9d23 Fix the ocaml bindings.
llvm-svn: 215117
2014-08-07 14:48:13 +00:00
Rafael Espindola ea9c317000 fix configure+make build
llvm-svn: 215116
2014-08-07 14:38:49 +00:00
Rafael Espindola 868dd398ee Remove empty directories.
llvm-svn: 215115
2014-08-07 14:25:55 +00:00
Manuel Klimek 0ce9108104 Only have one path in the CFG for ternaries if the condition is known.
The return type analysis requires that the CFG is simplified when the
truth values of branches are statically known at analysis time.

llvm-svn: 215114
2014-08-07 14:25:43 +00:00
Rafael Espindola b0ece4e07d Update for llvm API change.
llvm-svn: 215113
2014-08-07 14:23:03 +00:00
Evgeniy Stepanov f5c1f8ac84 [sanitizer] Intercept timerfd_settime, timerfd_gettime.
llvm-svn: 215112
2014-08-07 14:21:42 +00:00
Rafael Espindola f8b27c41e8 Nuke the old JIT.
I am sure we will be finding bits and pieces of dead code for years to
come, but this is a good start.

Thanks to Lang Hames for making MCJIT a good replacement!

llvm-svn: 215111
2014-08-07 14:21:18 +00:00
Joerg Sonnenberger 84d35dfe96 Add mfasr and mtasr
llvm-svn: 215110
2014-08-07 13:35:34 +00:00
Joerg Sonnenberger 853feaa808 Add mfrtcu and mfrtcl instructions
llvm-svn: 215109
2014-08-07 13:16:58 +00:00
Joerg Sonnenberger 1837a7b4fa Support mttbl and mttbu mnemonic
llvm-svn: 215108
2014-08-07 13:06:23 +00:00
Hafiz Abid Qadeer 101e490b1e Fixed the build broken by the r215046.
llvm-svn: 215107
2014-08-07 12:54:20 +00:00
Evgeniy Stepanov 37e069c2ac [msan] Fix fcvt interceptor.
fcvt() result can be heap-allocated and must be unpoisoned.

llvm-svn: 215106
2014-08-07 12:45:55 +00:00
Joerg Sonnenberger a3d4dc9eb4 Add RFID instruction.
llvm-svn: 215105
2014-08-07 12:39:59 +00:00
Joerg Sonnenberger 83ef5c7753 Fix Itineray class of rfi
llvm-svn: 215104
2014-08-07 12:35:16 +00:00
Joerg Sonnenberger 6ae087abc6 Spell e500 feature in lower case.
llvm-svn: 215103
2014-08-07 12:31:28 +00:00
Joerg Sonnenberger 39f095ae5a Add first bunch of SPE instructions. As they overlap with Altivec, mark
them as parser-only until the disassembler is extended to handle
predicates properly.

llvm-svn: 215102
2014-08-07 12:18:21 +00:00
Alexander Kornienko 7151ad7762 Insert parens to avoid a warning:
suggest parentheses around arithmetic in operand of '^' [-Wparentheses]

llvm-svn: 215101
2014-08-07 12:09:34 +00:00
Aaron Ballman b677f7ac4b Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)). No functional changes intended.
llvm-svn: 215100
2014-08-07 12:07:33 +00:00
Daniel Sanders 449344315f [mips] Add assembler support for .set msa/nomsa directive.
Summary:
These directives are used to toggle whether the assembler accepts MSA-specific instructions or not.

Patch by Matheus Almeida and Toma Tabacu.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4783

llvm-svn: 215099
2014-08-07 12:03:36 +00:00
Pavel Chupin 124889243a Fix lld-x86_64-win7 Build #11969
llvm-svn: 215097
2014-08-07 11:09:59 +00:00
Manuel Klimek b5616c9f8d Re-applying r214962.
Changes to the original patch:
- model the CFG for temporary destructors in conditional operators so that
  the destructors of the true and false branch are always exclusive. This
  is necessary because we must not have impossible paths for the path
  based analysis to work.
- add multiple regression tests with ternary operators

Original description:
Fix modelling of non-lifetime-extended temporary destructors in the
analyzer.

Changes to the CFG:
When creating the CFG for temporary destructors, we create a structure
that mirrors the branch structure of the conditionally executed
temporary constructors in a full expression.
The branches we create use a CXXBindTemporaryExpr as terminator which
corresponds to the temporary constructor which must have been executed
to enter the destruction branch.

2. Changes to the Analyzer:
When we visit a CXXBindTemporaryExpr we mark the CXXBindTemporaryExpr as
executed in the state; when we reach a branch that contains the
corresponding CXXBindTemporaryExpr as terminator, we branch out
depending on whether the corresponding CXXBindTemporaryExpr was marked
as executed.

llvm-svn: 215096
2014-08-07 10:42:17 +00:00
Chandler Carruth 4e8fcbd3fd [x86] Fix another miscompile found through fuzz testing the new vector
shuffle lowering.

This is closely related to the previous one. Here we failed to use the
source offset when swapping in the other case -- where we end up
swapping the *final* shuffle. The cause of this bug is a bit different:
I simply wasn't thinking about the fact that this mask is actually
a slice of a wide mask and thus has numbers that need SourceOffset
applied. Simple fix. Would be even more simple with an algorithm-y thing
to use here, but correctness first. =]

llvm-svn: 215095
2014-08-07 10:37:35 +00:00
Chandler Carruth e206385e99 [x86] Fix another miscompile in the new vector shuffle lowering found
via the fuzz tester.

Here I missed an offset when round-tripping a value through a shuffle
mask. I got it right 2 lines below. See a problem? I do. ;] I'll
probably be adding a little "swap" algorithm which accepts a range and
two values and swaps those values where they occur in the range. Don't
really have a name for it, let me know if you do.

llvm-svn: 215094
2014-08-07 10:14:27 +00:00
Jim Cownie 3051f9761e Commit PowerPC64 support from Carlo Bertolli at IBM.
llvm-svn: 215093
2014-08-07 10:12:54 +00:00
Chandler Carruth 78494364d1 [x86] Fix another miscompile in the new vector shuffle lowering found
through the new fuzzer.

This one is great: bad operator precedence led the modulus to happen at
the wrong point. All the asserts didn't fire because there were usually
the right values past the end of the 4 element region we were looking
at. Probably could have gotten a crash here with ASan + fuzzing, but the
correctness tests pinpointed this really nicely.

llvm-svn: 215092
2014-08-07 09:45:02 +00:00
Pavel Chupin f55eb450e5 [x32] Use ebp/esp as frame and stack pointer
Summary:
Since pointers are 32-bit on x32 we can use ebp and esp as frame and stack
pointer. Some operations like PUSH/POP and CFI_INSTRUCTION still
require 64-bit register, so using 64-bit MachineFramePtr where required.

X86_64 NaCl uses 64-bit frame/stack pointers, however it's been found that
both isTarget64BitLP64 and isTarget64BitILP32 are true for NaCl. Addressing
this issue here as well by making isTarget64BitLP64 false.

Also mark hasReservedSpillSlot unreachable on X86. See inlined comments.

Test Plan: Add one new simple test and upgrade 2 existing with x32 target case.

Reviewers: nadav, dschuff

Subscribers: llvm-commits, zinovy.nis

Differential Revision: http://reviews.llvm.org/D4617

llvm-svn: 215091
2014-08-07 09:41:19 +00:00
Chandler Carruth 27046758de [x86] Fix a miscompile in the new shuffle lowering found through the new
fuzz testing.

The function which tested for adjacency did what it said on the tin, but
when I called it, I wanted it to do something more thorough: I wanted to
know if the *pairs* of shuffle elements were adjacent and started at
0 mod 2. In one place I had the decency to try to test for this, but in
the other it was completely skipped, miscompiling this test case. Fix
this by making the helper actually do what I wanted it to do everywhere
I called it (and removing the now redundant code in one place).

I *really* dislike the name "canWidenShuffleElements" for this
predicate. If anyone can come up with a better name, please let me know.
The other name I thought about was "canWidenShuffleMask" but is it
really widening the mask to reduce the number of lanes shuffled? I don't
know. Naming things is hard.

llvm-svn: 215089
2014-08-07 08:11:31 +00:00
Pete Cooper 9b90dc7c6a Update Tablegen documents given that binary literals are now sized
llvm-svn: 215088
2014-08-07 05:47:13 +00:00
Pete Cooper 94891ddf0d Update BitRecTy::convertValue to allow if expressions with bit values on both sides of the if
llvm-svn: 215087
2014-08-07 05:47:10 +00:00
Pete Cooper 0bf1ea72ee Change the { } expression in tablegen to accept sized binary literals which are not just 0 and 1.
It also allows nested { } expressions, as now that they are sized, we can merge pull bits from the nested value.

In the current behaviour, everything in { } must have been convertible to a single bit.
However, now that binary literals are sized, its useful to be able to initialize a range of bits.

So, for example, its now possible to do

bits<8> x = { 0, 1, { 0b1001 }, 0, 0b0 }

llvm-svn: 215086
2014-08-07 05:47:07 +00:00
Pete Cooper 2cfdfe5882 Change BitsInit to inherit from TypedInit.
This is useful in a later patch where binary literals such as 0b000 will become BitsInit values instead of IntInit values.

llvm-svn: 215085
2014-08-07 05:47:04 +00:00
Pete Cooper 2597764ad9 Change TableGen so that binary literals such as 0b001 are now sized.
Instead of these becoming an integer literal internally, they now become bits<n> values.

Prior to this change, 0b001 was 1 bit long.  This is confusing as clearly the user gave 3 bits.
This new type holds both the literal value and the size, and so can ensure sizes match on initializers.

For example, this used to be legal

bits<1> x = 0b00;

but now it must be written as

bits<2> x = 0b00;

llvm-svn: 215084
2014-08-07 05:47:00 +00:00
Pete Cooper 99ad2a3b67 TableGen: Change { } to only accept bits<n> entries when n == 1.
Prior to this change, it was legal to do something like

  bits<2> opc = { 0, 1 };
  bits<2> opc2 = { 1, 0 };
  bits<2> a = { opc, opc2 };

This involved silently dropping bits from opc and opc2 which is very hard to debug.

Now the above test would be an error.  Having tested with an assert, none of LLVM/clang was relying on this behaviour.

Thanks to Adam Nemet for the above test.

llvm-svn: 215083
2014-08-07 05:46:57 +00:00
Pete Cooper c18261d467 Fix a whole bunch of binary literals which were the wrong size. All were being silently zero extended to the correct width.
The commit after this changes { } and 0bxx literals to be of type bits<n> and not int.  This means we need to write exactly the right number of bits, and not rely on the values being silently zero extended for us.

llvm-svn: 215082
2014-08-07 05:46:54 +00:00
Viktor Kutuzov c68a37c531 Add FreeBSD support to the address sanitizer's malloc_context_size.cc test case
Differential Revision: http://reviews.llvm.org/D4665

llvm-svn: 215081
2014-08-07 04:58:41 +00:00
Chandler Carruth ae42d7d020 Add an option to the shuffle fuzzer that lets you fuzz exclusively
within a single bit-width of vectors. This is particularly useful for
when you know you have bugs in a certain area and want to find simpler
test cases than those produced by an open-ended fuzzing that ends up
legalizing the vector in addition to shuffling it.

llvm-svn: 215056
2014-08-07 04:49:54 +00:00
Bill Wendling fcb526020a Use the minor number for the revision numbers.
llvm-svn: 215055
2014-08-07 04:21:45 +00:00
Chandler Carruth 7f3facb7e6 Add a vector shuffle fuzzer.
This is a python script which for a given seed generates a random
sequence of random shuffles of a random vector width. It embeds this
into a function and emits a main function which calls the test routine
and checks that the results (where defined) match the obvious results.

I'll be using this to drive out miscompiles from the new vector shuffle
logic now that it is clean of any crashes I can find with llvm-stress.

Note, my python skills are very poor. Sorry if this is terrible code,
and feel free to tell me how I should write this or just patch it as
necessary.

The tests generated try to be very portable and use boring C routines.
It technically will mis-declare the C routines and pass 32-bit integers
to parametrs that expect 64-bit integers. If someone wants to fix this
and has less terrible ideas of how to do it, I'm all ears. Fortunately,
this "just works" for x86. =]

llvm-svn: 215054
2014-08-07 04:13:51 +00:00
Justin Bogner 4d10c23909 Driver: Add tests for -fprofile-arcs and -fno-profile-arcs
I tried to be lazy and get away with no test in r215051, but Chad
caught me :)

llvm-svn: 215053
2014-08-07 03:58:32 +00:00