Commit Graph

18322 Commits

Author SHA1 Message Date
Jim Grosbach cabb48d511 Parameterize away the ARM T1Cop class.
llvm-svn: 135082
2011-07-13 21:17:59 +00:00
Jim Grosbach adb29b6dbb Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
2011-07-13 21:14:23 +00:00
Eli Friedman ef67e7d623 Refactor out checking for displacements on x86-64 addressing modes. No functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress.
Part of <rdar://problem/9763308>.

llvm-svn: 135079
2011-07-13 20:44:23 +00:00
Jim Grosbach e2f9840cdb Fix encoding for ARM BXJ instruction.
llvm-svn: 135077
2011-07-13 20:25:01 +00:00
Jim Grosbach 801d3ad1b2 Fix encoding of predicate bits on ARM BX_pred.
llvm-svn: 135076
2011-07-13 20:21:31 +00:00
Jim Grosbach 975b641ee8 Range checking for 16-bit immediates in ARM assembly.
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Evan Cheng 2d7faa5e3e Fix up TargetLoweringObjectFile ctors to properly initialize fields.
llvm-svn: 135068
2011-07-13 19:54:59 +00:00
Jim Grosbach e255be93a8 Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.

llvm-svn: 135066
2011-07-13 19:24:09 +00:00
Jim Grosbach c845e55374 Add tests for ARM parsing of 'BKPT' instruction.
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach bb24c595f7 Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

llvm-svn: 135055
2011-07-13 18:49:30 +00:00
Jim Grosbach 04afb071e1 Destination register operand is optional for ADC and SBC ARM.
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach 7dcd1354f1 Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Jim Grosbach 06210a28de 80 columns.
llvm-svn: 135047
2011-07-13 17:25:55 +00:00
Jim Grosbach 602aa90ab8 Update MCParsedAsmOperand debug methods.
Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.

llvm-svn: 135043
2011-07-13 15:34:57 +00:00
Jay Foad 57aa636794 Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.
llvm-svn: 135040
2011-07-13 10:26:04 +00:00
Evan Cheng 21e9051922 Add an entry.
llvm-svn: 135024
2011-07-13 01:33:00 +00:00
Bruno Cardoso Lopes 1021b4a9dd AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
llvm-svn: 135023
2011-07-13 01:15:33 +00:00
Bill Wendling ee6e776be2 Don't emit the FDE end label if the last thing emitted was a compact unwind and
not the FDE

llvm-svn: 135020
2011-07-13 00:49:09 +00:00
Eli Friedman 16323380cd Add an assert (which should never trigger) that triggers on a testcase I'm looking at.
llvm-svn: 135018
2011-07-13 00:44:29 +00:00
Evan Cheng f863e3fb73 Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317

llvm-svn: 135017
2011-07-13 00:42:17 +00:00
Bill Wendling 0402e8fe4b Assign variable before we test it.
llvm-svn: 135015
2011-07-13 00:23:39 +00:00
Bill Wendling ed3c44224b Fix obvious think-o.
llvm-svn: 135014
2011-07-13 00:20:09 +00:00
Bill Wendling 929b90ff32 Clean up the handling of an EBP/RBP unwind frame pointer. In particular, don't
assert when the frame pointer is -1 (i.e., the function is "frameless").

Still to do: "frameless" unwind information.

llvm-svn: 135013
2011-07-13 00:16:14 +00:00
Bill Wendling 5d11676eef There is a cyclic dependency between MC and Target if this method is out-of-line.
llvm-svn: 135006
2011-07-12 22:35:01 +00:00
Jay Foad b804a2b751 Second attempt at de-constifying LLVM Types in FunctionType::get(),
StructType::get() and TargetData::getIntPtrType().

llvm-svn: 134982
2011-07-12 14:06:48 +00:00
Tobias Grosser 6c3501d5c6 Remove IntegerType constness from TargetData
llvm-svn: 134978
2011-07-12 11:36:58 +00:00
Bill Wendling a78cd228c2 Revert r134893 and r134888 (and related patches in other trees). It was causing
an assert on Darwin llvm-gcc builds.

Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.

http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354

--- Reverse-merging r134893 into '.':
U    include/llvm/Target/TargetData.h
U    include/llvm/DerivedTypes.h
U    tools/bugpoint/ExtractFunction.cpp
U    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/ARM/ARMGlobalMerge.cpp
U    lib/Target/TargetData.cpp
U    lib/VMCore/Constants.cpp
U    lib/VMCore/Type.cpp
U    lib/VMCore/Core.cpp
U    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Instrumentation/ProfilingUtils.cpp
U    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G    include/llvm/DerivedTypes.h
U    include/llvm/Support/TypeBuilder.h
U    include/llvm/Intrinsics.h
U    unittests/Analysis/ScalarEvolutionTest.cpp
U    unittests/ExecutionEngine/JIT/JITTest.cpp
U    unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U    unittests/VMCore/PassManagerTest.cpp
G    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U    lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U    lib/VMCore/IRBuilder.cpp
G    lib/VMCore/Type.cpp
U    lib/VMCore/Function.cpp
G    lib/VMCore/Core.cpp
U    lib/VMCore/Module.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/Transforms/Utils/CloneFunction.cpp
G    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Utils/InlineFunction.cpp
U    lib/Transforms/Instrumentation/GCOVProfiling.cpp
U    lib/Transforms/Scalar/ObjCARC.cpp
U    lib/Transforms/Scalar/SimplifyLibCalls.cpp
U    lib/Transforms/Scalar/MemCpyOptimizer.cpp
G    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/Transforms/IPO/ArgumentPromotion.cpp
U    lib/Transforms/InstCombine/InstCombineCompares.cpp
U    lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U    lib/Transforms/InstCombine/InstCombineCalls.cpp
U    lib/CodeGen/DwarfEHPrepare.cpp
U    lib/CodeGen/IntrinsicLowering.cpp
U    lib/Bitcode/Reader/BitcodeReader.cpp

llvm-svn: 134949
2011-07-12 01:15:52 +00:00
Evan Cheng 58a98141d9 Most MCCodeEmitter's don't meed MCContext.
llvm-svn: 134922
2011-07-11 21:24:15 +00:00
Jim Grosbach a9a3f0a414 Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.

llvm-svn: 134903
2011-07-11 17:09:57 +00:00
Jim Grosbach 581da64241 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

llvm-svn: 134902
2011-07-11 16:48:36 +00:00
Jay Foad 7c57be3e2b De-constify Types in StructType::get() and TargetData::getIntPtrType().
llvm-svn: 134893
2011-07-11 09:56:20 +00:00
Jay Foad 56cc1530ee De-constify Types in FunctionType::get().
llvm-svn: 134888
2011-07-11 07:56:41 +00:00
Evan Cheng c5e6d2f519 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Cameron Zwarich 776403b642 Fix <rdar://problem/9751331>.
llvm-svn: 134882
2011-07-11 01:29:42 +00:00
Jakub Staszak 9b07c0ab6b Use BranchProbability instead of floating points in IfConverter.
llvm-svn: 134858
2011-07-10 02:58:07 +00:00
Chris Lattner b1ed91f397 Land the long talked about "type system rewrite" patch. This
patch brings numerous advantages to LLVM.  One way to look at it
is through diffstat:
 109 files changed, 3005 insertions(+), 5906 deletions(-)

Removing almost 3K lines of code is a good thing.  Other advantages
include:

1. Value::getType() is a simple load that can be CSE'd, not a mutating
   union-find operation.
2. Types a uniqued and never move once created, defining away PATypeHolder.
3. Structs can be "named" now, and their name is part of the identity that
   uniques them.  This means that the compiler doesn't merge them structurally
   which makes the IR much less confusing.
4. Now that there is no way to get a cycle in a type graph without a named
   struct type, "upreferences" go away.
5. Type refinement is completely gone, which should make LTO much MUCH faster
   in some common cases with C++ code.
6. Types are now generally immutable, so we can use "Type *" instead 
   "const Type *" everywhere.

Downsides of this patch are that it removes some functions from the C API,
so people using those will have to upgrade to (not yet added) new API.  
"LLVM 3.0" is the right time to do this.

There are still some cleanups pending after this, this patch is large enough
as-is.

llvm-svn: 134829
2011-07-09 17:41:24 +00:00
Evan Cheng 21a9772ac1 Revert accidental commit.
llvm-svn: 134800
2011-07-09 06:26:27 +00:00
Evan Cheng 91111d2706 Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795
2011-07-09 05:47:46 +00:00
Eli Friedman fe2088bb1f Really force on 64bit for 64-bit targets. Should fix remaining failures on unknown x86/non-x86 targets.
llvm-svn: 134773
2011-07-08 23:43:01 +00:00
Eli Friedman 5286833f4a Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets.
llvm-svn: 134768
2011-07-08 23:07:42 +00:00
Evan Cheng 45543ba4e8 Fix indentation.
llvm-svn: 134764
2011-07-08 22:49:55 +00:00
Evan Cheng 284b467d9f Add support for ARM / Thumb mode switching with .code 16 and .code 32.
llvm-svn: 134760
2011-07-08 22:36:29 +00:00
Jim Grosbach 39c67b5e08 Mark tBRIND as predicable.
llvm-svn: 134758
2011-07-08 22:33:49 +00:00
Evan Cheng 60fc0fca5c Restore old behavior. Always auto-detect features unless cpu or features are specified.
llvm-svn: 134757
2011-07-08 22:30:25 +00:00
Jim Grosbach 59a3ab6e46 Pseudo-ize tBRIND.
llvm-svn: 134755
2011-07-08 22:25:23 +00:00
Eli Friedman e2f76c4ade Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
llvm-svn: 134753
2011-07-08 22:16:47 +00:00
Jim Grosbach 7471937ad7 Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.

llvm-svn: 134746
2011-07-08 21:50:04 +00:00
Julien Lerouge 112fcc164a Add _allrem, _aullrem and _allmul to the runtime for MSVC.
http://llvm.org/bugs/show_bug.cgi?id=10305

llvm-svn: 134744
2011-07-08 21:40:25 +00:00
Cameron Zwarich f03fa189ca Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742
2011-07-08 21:39:21 +00:00
Evan Cheng 964cb5feb0 For non-x86 host, used generic as CPU name.
llvm-svn: 134741
2011-07-08 21:14:14 +00:00
Jim Grosbach d61ae786bd Pseudo-ize tBX_RET and tBX_RET_vararg.
llvm-svn: 134739
2011-07-08 21:10:35 +00:00
Benjamin Kramer debe69fb37 Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo.
Found by valgrind.

llvm-svn: 134738
2011-07-08 21:06:23 +00:00
Jim Grosbach cb1b0b7130 Shuffle productions around a bit.
No functional change.

llvm-svn: 134737
2011-07-08 21:04:05 +00:00
Jim Grosbach 204c128f66 Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.
llvm-svn: 134734
2011-07-08 20:39:19 +00:00
Jim Grosbach 4af8647e17 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
llvm-svn: 134732
2011-07-08 20:32:21 +00:00
Benjamin Kramer dbdff47cb3 Silence compiler warning.
llvm-svn: 134730
2011-07-08 20:18:13 +00:00
Jim Grosbach 3840c90f73 Add more info to FIXME.
llvm-svn: 134729
2011-07-08 20:18:11 +00:00
Jim Grosbach 166cd88645 Move Thumb tail call pseudos to Thumb.td file.
Fix a FIXME.

llvm-svn: 134727
2011-07-08 20:13:35 +00:00
Evan Cheng 22e9d8f40e TargetAsmParser doesn't need reference to Target.
llvm-svn: 134721
2011-07-08 19:33:14 +00:00
Jim Grosbach dbfb29d6c0 Use ARMPseudoExpand for ARM tail calls.
llvm-svn: 134719
2011-07-08 18:50:22 +00:00
Jim Grosbach 7ddc1d709f Shuffle productions around a bit.
No functional change.

llvm-svn: 134714
2011-07-08 18:26:27 +00:00
Jim Grosbach 2dfe8e3ccd Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712
2011-07-08 18:15:12 +00:00
Chandler Carruth f21cebf6dd Add CMake support for the new TableGen file introduced in r134705.
llvm-svn: 134707
2011-07-08 17:54:08 +00:00
Jim Grosbach 95dee40343 Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705
2011-07-08 17:40:42 +00:00
Evan Cheng 4d1ca96bfc Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678
2011-07-08 01:53:10 +00:00
Akira Hatanaka f9a85356bc Raise assertion when MachineOperand has unexpected target flag.
llvm-svn: 134671
2011-07-08 00:42:35 +00:00
Akira Hatanaka 8ccd65842d Make sure variable Kind is assigned a value to suppress warning.
llvm-svn: 134668
2011-07-08 00:26:25 +00:00
Nick Lewycky 9badf60203 Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!

llvm-svn: 134665
2011-07-08 00:19:27 +00:00
Eric Christopher 7a2a0f80de Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.

Fixes PR9675 and rdar://9740801

llvm-svn: 134664
2011-07-08 00:04:56 +00:00
Akira Hatanaka 9c6028f98e Lower MachineInstr to MC Inst and print to .s files.
llvm-svn: 134661
2011-07-07 23:56:50 +00:00
Eric Christopher 719c29702f Handle fpcr register.
Part of PR10299 and rdar://9740322

llvm-svn: 134653
2011-07-07 22:54:12 +00:00
Eric Christopher 9721396dab Add support for the X86 'l' constraint.
Fixes PR10149 and rdar://9738585

llvm-svn: 134648
2011-07-07 22:29:07 +00:00
Akira Hatanaka 28d6677a53 Remove unnecessary newline.
llvm-svn: 134645
2011-07-07 22:06:18 +00:00
Evan Cheng 13bcc6c1c7 Add Mode64Bit feature and sink it down to MC layer.
llvm-svn: 134641
2011-07-07 21:06:52 +00:00
Bill Wendling 1a423d8b35 Move a function out-of-line.
llvm-svn: 134640
2011-07-07 21:05:13 +00:00
Akira Hatanaka 9f6f6f6ecc Rather than having printMemOperand change the way memory operands are printed
based on a modifier, split it into two functions.

llvm-svn: 134637
2011-07-07 20:54:20 +00:00
Akira Hatanaka 77a9e6e7df Define class MipsMCInstLower.
llvm-svn: 134633
2011-07-07 20:24:54 +00:00
Akira Hatanaka ddd1265316 Change visibility of MipsAsmPrinter.
llvm-svn: 134630
2011-07-07 20:10:52 +00:00
Akira Hatanaka 04da3658c6 Define class MipsMCSymbolRefExpr.
llvm-svn: 134629
2011-07-07 19:27:22 +00:00
Akira Hatanaka 9d1936a270 Simplify MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134628
2011-07-07 19:13:09 +00:00
Evan Cheng 6dbe713a49 Rewrite comment in English.
llvm-svn: 134627
2011-07-07 19:09:06 +00:00
Evan Cheng 1834f5dcb6 Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
llvm-svn: 134626
2011-07-07 19:05:12 +00:00
Akira Hatanaka 2e766ed2f8 Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
2011-07-07 18:57:00 +00:00
Akira Hatanaka ac4db9251b Add missing return statement.
llvm-svn: 134622
2011-07-07 18:27:36 +00:00
Oscar Fuentes 32a45e5aeb Update CMake library dependencies
llvm-svn: 134616
2011-07-07 16:33:00 +00:00
Douglas Gregor cc4a55f6f2 Fix CMake build
llvm-svn: 134614
2011-07-07 15:59:22 +00:00
Cameron Zwarich 148220306f The VMLA instruction and its friends are not actually fused; they're plain old
multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609
2011-07-07 08:28:52 +00:00
Evan Cheng f2c2616e72 Sink feature IsThumb into MC layer.
llvm-svn: 134608
2011-07-07 08:26:46 +00:00
Evan Cheng 1a72add615 Compute feature bits at time of MCSubtargetInfo initialization.
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
Bill Wendling 667be58220 Use ArrayRef instead of a std::vector&.
llvm-svn: 134595
2011-07-07 04:42:01 +00:00
Evan Cheng 8b2bda09a5 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
llvm-svn: 134590
2011-07-07 03:55:05 +00:00
Bill Wendling b6adf46f62 Add a target hook to encode the compact unwind information.
llvm-svn: 134577
2011-07-07 00:54:13 +00:00
Evan Cheng 2bd65363a8 Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
llvm-svn: 134569
2011-07-07 00:08:19 +00:00
Evan Cheng 928ce72bcd Add ARM MC registry routines.
llvm-svn: 134547
2011-07-06 22:02:34 +00:00
Evan Cheng 3ddfbd325d Rename files for consistency.
llvm-svn: 134546
2011-07-06 22:01:53 +00:00
Jim Grosbach 7c301ea093 Mark ARM pseudo-instructions as isPseudo.
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540
2011-07-06 21:35:46 +00:00
Jim Grosbach 4db363af7c Remove un-used encoding info from Pseudo MLAv5.
Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.

llvm-svn: 134533
2011-07-06 20:57:35 +00:00
Bill Wendling 5ace8edfd6 Constify getCompactUnwindRegNum.
llvm-svn: 134527
2011-07-06 20:33:48 +00:00
Evan Cheng ab37af9af3 createMCInstPrinter doesn't need TargetMachine anymore.
llvm-svn: 134525
2011-07-06 19:45:42 +00:00
Kevin Enderby 6ee1d2bd78 Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
push with a small constant produces a 2-byte push.

llvm-svn: 134501
2011-07-06 17:23:46 +00:00
Evan Cheng 4d806e2830 Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo.
llvm-svn: 134457
2011-07-06 02:02:33 +00:00
Eli Friedman 415412e82f Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
llvm-svn: 134424
2011-07-05 18:21:20 +00:00
Jim Grosbach ea53901dc9 ARM estimateStackSize() needs to account for simplified call frames.
If the function allocates reserved stack space for callee argument frames,
estimateStackSize() needs to account for that, as it doesn't show up as
ordinary frame objects. Otherwise, a callee with a large argument list will
throw off the calculations for whether to allocate an emergency spill slot
and we get assert() failures in the register scavenger.

rdar://9715469

llvm-svn: 134415
2011-07-05 16:05:50 +00:00
Roman Divacky cc5e53383e Remove accidentaly left node from previous iteration of the patch.
Noticed by Benjamin Kramer!

llvm-svn: 134376
2011-07-04 15:42:45 +00:00
Roman Divacky 075491f2cd Make the i64 and f64 be 64bit ABI aligned in the target description.
This is what both the ABI and clang says.

llvm-svn: 134367
2011-07-03 16:24:07 +00:00
Duncan Sands 4bea037504 Remove unused array.
llvm-svn: 134323
2011-07-02 16:36:24 +00:00
Jakob Stoklund Olesen e925f22b40 Consistent diagnostic capitalization and redundant context elimination.
llvm-svn: 134311
2011-07-02 07:23:40 +00:00
Jakob Stoklund Olesen 25a404eb81 Include a source location when complaining about bad inline assembly.
Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.

This enables proper clang diagnostics from the backend:

$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
           ^
1 error generated.

llvm-svn: 134307
2011-07-02 03:53:34 +00:00
Eric Christopher a8a56f7e5c TargetConstant immediates won't be placed into registers so tighten
up the valid constant check earlier.

rdar://9692967

llvm-svn: 134286
2011-07-01 23:04:38 +00:00
Evan Cheng c9c090d7a5 Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
llvm-svn: 134281
2011-07-01 22:36:09 +00:00
Evan Cheng 0711c4d489 Add MCSubtargetInfo target registry stuff.
llvm-svn: 134279
2011-07-01 22:25:04 +00:00
Eli Friedman d24a7da658 Calling-convention specifications for illegal types are no-ops. Simplify based on this.
llvm-svn: 134264
2011-07-01 21:33:28 +00:00
Jim Grosbach cf1464d943 ARMv7M vs. ARMv7E-M support.
The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992

llvm-svn: 134261
2011-07-01 21:12:19 +00:00
Evan Cheng 0d639a28aa Rename TargetSubtarget to TargetSubtargetInfo for consistency.
llvm-svn: 134259
2011-07-01 21:01:15 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
2011-07-01 20:45:01 +00:00
Jim Grosbach 68b0e8456e Fix off-by-one error.
(low two bits always zero, so off by one bit of encoded value).

llvm-svn: 134247
2011-07-01 19:07:09 +00:00
Evan Cheng 703a0fbf39 Hide the call to InitMCInstrInfo into tblgen generated ctor.
llvm-svn: 134244
2011-07-01 17:57:27 +00:00
Jim Grosbach 4def704a21 Pseudo-ize t2MOVCC[ri].
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.

llvm-svn: 134242
2011-07-01 17:14:11 +00:00
Akira Hatanaka f2bcad972d Improve Mips back-end's handling of DBG_VALUE.
llvm-svn: 134224
2011-07-01 01:04:43 +00:00
Eric Christopher 29f1db85dd Add support for the 'j' immediate constraint. This is conditionalized on
supporting the instruction that the constraint is for 'movw'.

Part of rdar://9119939

llvm-svn: 134222
2011-07-01 01:00:07 +00:00
Eric Christopher c011d31543 Add support for the ARM 't' register constraint. And another testcase
for the 'x' register constraint.

Part of rdar://9119939

llvm-svn: 134220
2011-07-01 00:30:46 +00:00
Eric Christopher f09b0f1043 We'll return a null RC by default if we can't match.
Part of rdar://9119939

llvm-svn: 134217
2011-07-01 00:19:27 +00:00
Eric Christopher f1c74595aa Add support for the 'x' constraint.
Part of rdar://9307836 and rdar://9119939

llvm-svn: 134215
2011-07-01 00:14:47 +00:00
Eric Christopher 1f054f27af Capitalize the unsigned part of the initializer.
llvm-svn: 134211
2011-06-30 23:59:16 +00:00
Eric Christopher cf2007ca78 Rename Pair to RCPair lacking any better naming ideas.
llvm-svn: 134210
2011-06-30 23:50:52 +00:00
Bill Wendling 3f049b8b7e Use the correct registers on X86_64.
llvm-svn: 134208
2011-06-30 23:47:14 +00:00
Jakob Stoklund Olesen d0e2352b65 Fix a problem with fast-isel return values introduced in r134018.
We would put the return value from long double functions in the wrong
register.

This fixes gcc.c-torture/execute/conversion.c

llvm-svn: 134205
2011-06-30 23:42:18 +00:00
Jim Grosbach e9cc901814 Refact ARM Thumb1 tMOVr instruction family.
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

llvm-svn: 134204
2011-06-30 23:38:17 +00:00
Eric Christopher f45daac30f Add support for the 'h' constraint.
Part of rdar://9119939

llvm-svn: 134203
2011-06-30 23:23:01 +00:00
Bill Wendling b403f0c4ed Add target a target hook to get the register number used by the compact unwind
encoding for the registers it knows about. Return -1 if it can't handle that
register.

llvm-svn: 134202
2011-06-30 23:20:32 +00:00
Eric Christopher c486b47b15 Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.
No functional change.

Part of rdar://9119939

llvm-svn: 134198
2011-06-30 22:17:01 +00:00
Jim Grosbach b98ab91e39 Thumb1 register to register MOV instruction is predicable.
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

llvm-svn: 134197
2011-06-30 22:10:46 +00:00
Jakob Stoklund Olesen 2034261972 Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.c
llvm-svn: 134193
2011-06-30 21:30:30 +00:00
Jim Grosbach e4750ef6ec Pseudo-ize the Thumb tTPsoft instruction.
It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.

llvm-svn: 134178
2011-06-30 19:38:01 +00:00
Jim Grosbach 353da73186 Pseudo-ize the t2LDMIA_RET instruction.
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.

llvm-svn: 134173
2011-06-30 18:25:42 +00:00
Jim Grosbach 417671a7b1 Pseudo-ize the Thumb tPOP_RET instruction.
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.

llvm-svn: 134172
2011-06-30 17:34:04 +00:00
Jim Grosbach cfe3b14d77 Kill dead code.
llvm-svn: 134131
2011-06-30 02:23:05 +00:00
Jim Grosbach ed5134a921 Size reducing SP adjusting t2ADDri needs to check predication.
tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."

llvm-svn: 134130
2011-06-30 02:22:49 +00:00
Evan Cheng 0b33a323ac Fix ARMSubtarget feature parsing.
llvm-svn: 134129
2011-06-30 02:12:44 +00:00
Evan Cheng fe6e405e8c Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
2011-06-30 01:53:36 +00:00
Joerg Sonnenberger 91e5662075 Recognize the xstorerng alias for VIA PadLock's xstore instruction.
llvm-svn: 134126
2011-06-30 01:38:03 +00:00
Eric Christopher 16cde8ad36 Make sure we use the correct register class here since we'll need to
care about spill values.

llvm-svn: 134122
2011-06-30 01:05:46 +00:00
Eric Christopher c932173773 Fix a small thinko for constant i64 lock/orq optimization where we
we didn't have an opcode for 64-bit constant or expressions.

Fixes rdar://9692967

llvm-svn: 134121
2011-06-30 00:48:30 +00:00
Jim Grosbach a8a8067dec Remove redundant Thumb2 ADD/SUB SP instruction definitions.
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.

llvm-svn: 134114
2011-06-29 23:25:04 +00:00
Jakob Stoklund Olesen 9f4cc4645b Always adjust the stack pointer immediately after the call.
Some x86-32 calls pop values off the stack, and we need to readjust the
stack pointer after the call. This happens when ADJCALLSTACKUP is
eliminated.

It could happen that spill code was inserted between the CALL and
ADJCALLSTACKUP instructions, and we would compute wrong stack pointer
offsets for those frame index references.

Fix this by inserting the stack pointer adjustment immediately after the
call instead of where the ADJCALLSTACKUP instruction was erased.

I don't have a test case since we don't currently insert code in that
position. We will soon, though. I am testing a regalloc patch that
didn't work on Linux because of this.

llvm-svn: 134113
2011-06-29 23:11:39 +00:00
Cameron Zwarich 34c8f51d65 In the ARM global merging pass, allow extraneous alignment specifiers. This pass
already makes the assumption, which is correct on ARM, that a type's alignment is
less than its alloc size. This improves codegen with Clang (which inserts a lot of
extraneous alignment specifiers) and fixes <rdar://problem/9695089>.

llvm-svn: 134106
2011-06-29 22:24:25 +00:00
Eric Christopher 1b8b9419ba Remove getRegClassForInlineAsmConstraint from the ARM port.
Part of rdar://9643582

llvm-svn: 134095
2011-06-29 21:10:36 +00:00
Eric Christopher 03e756b93b Remove todo.
llvm-svn: 134094
2011-06-29 21:05:54 +00:00
Jim Grosbach d86f34d631 Refactor away tSpill and tRestore pseudos in ARM backend.
The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.

llvm-svn: 134092
2011-06-29 20:26:39 +00:00
Eric Christopher e449141788 Add a TODO for the Alpha port inline asm constraints.
llvm-svn: 134089
2011-06-29 19:41:27 +00:00