Commit Graph

187 Commits

Author SHA1 Message Date
Evan Cheng efd9b4240f - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580
2011-07-20 07:51:56 +00:00
Evan Cheng 2129f59637 Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468
2011-07-19 06:37:02 +00:00
Evan Cheng 67c033e6b8 Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
better location welcome).

llvm-svn: 135438
2011-07-18 22:29:13 +00:00
Evan Cheng d60fa58ba1 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424
2011-07-18 20:57:22 +00:00
Chris Lattner 229907cd11 land David Blaikie's patch to de-constify Type, with a few tweaks.
llvm-svn: 135375
2011-07-18 04:54:35 +00:00
Chandler Carruth 9a0001aedb Major update to CMake build to reflect changes in r135219 in the
backend. Moved some MCAsmInfo files down into the MCTargetDesc
sublibraries, removed some (i suspect long) dead files from other parts
of the CMake build, etc. Also copied the include directory hack from the
Makefile.

Finally, updated the lib deps. I spot checked this, and think its
correct, but review appreciated there.

llvm-svn: 135234
2011-07-15 00:40:52 +00:00
Evan Cheng 1705ab00ab Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
llvm-svn: 135219
2011-07-14 23:50:31 +00:00
Evan Cheng bc153d49b7 Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
2011-07-14 20:59:42 +00:00
Jay Foad b804a2b751 Second attempt at de-constifying LLVM Types in FunctionType::get(),
StructType::get() and TargetData::getIntPtrType().

llvm-svn: 134982
2011-07-12 14:06:48 +00:00
Bill Wendling a78cd228c2 Revert r134893 and r134888 (and related patches in other trees). It was causing
an assert on Darwin llvm-gcc builds.

Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.

http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354

--- Reverse-merging r134893 into '.':
U    include/llvm/Target/TargetData.h
U    include/llvm/DerivedTypes.h
U    tools/bugpoint/ExtractFunction.cpp
U    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/ARM/ARMGlobalMerge.cpp
U    lib/Target/TargetData.cpp
U    lib/VMCore/Constants.cpp
U    lib/VMCore/Type.cpp
U    lib/VMCore/Core.cpp
U    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Instrumentation/ProfilingUtils.cpp
U    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G    include/llvm/DerivedTypes.h
U    include/llvm/Support/TypeBuilder.h
U    include/llvm/Intrinsics.h
U    unittests/Analysis/ScalarEvolutionTest.cpp
U    unittests/ExecutionEngine/JIT/JITTest.cpp
U    unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U    unittests/VMCore/PassManagerTest.cpp
G    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U    lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U    lib/VMCore/IRBuilder.cpp
G    lib/VMCore/Type.cpp
U    lib/VMCore/Function.cpp
G    lib/VMCore/Core.cpp
U    lib/VMCore/Module.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/Transforms/Utils/CloneFunction.cpp
G    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Utils/InlineFunction.cpp
U    lib/Transforms/Instrumentation/GCOVProfiling.cpp
U    lib/Transforms/Scalar/ObjCARC.cpp
U    lib/Transforms/Scalar/SimplifyLibCalls.cpp
U    lib/Transforms/Scalar/MemCpyOptimizer.cpp
G    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/Transforms/IPO/ArgumentPromotion.cpp
U    lib/Transforms/InstCombine/InstCombineCompares.cpp
U    lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U    lib/Transforms/InstCombine/InstCombineCalls.cpp
U    lib/CodeGen/DwarfEHPrepare.cpp
U    lib/CodeGen/IntrinsicLowering.cpp
U    lib/Bitcode/Reader/BitcodeReader.cpp

llvm-svn: 134949
2011-07-12 01:15:52 +00:00
Jay Foad 56cc1530ee De-constify Types in FunctionType::get().
llvm-svn: 134888
2011-07-11 07:56:41 +00:00
Evan Cheng c5e6d2f519 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Evan Cheng 91111d2706 Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795
2011-07-09 05:47:46 +00:00
Evan Cheng 4d1ca96bfc Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678
2011-07-08 01:53:10 +00:00
Evan Cheng 1a72add615 Compute feature bits at time of MCSubtargetInfo initialization.
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
Evan Cheng c9c090d7a5 Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
llvm-svn: 134281
2011-07-01 22:36:09 +00:00
Evan Cheng 0d639a28aa Rename TargetSubtarget to TargetSubtargetInfo for consistency.
llvm-svn: 134259
2011-07-01 21:01:15 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
2011-07-01 20:45:01 +00:00
Evan Cheng 703a0fbf39 Hide the call to InitMCInstrInfo into tblgen generated ctor.
llvm-svn: 134244
2011-07-01 17:57:27 +00:00
Evan Cheng fe6e405e8c Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
2011-06-30 01:53:36 +00:00
Eric Christopher dabd8a7bef Move the Blackfin port away from getRegClassForInlineAsmConstraint by
creating a few specific register classes.

Part of rdar://9643582

llvm-svn: 134086
2011-06-29 19:30:29 +00:00
Evan Cheng 194c3dc01f Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
llvm-svn: 134030
2011-06-28 21:14:33 +00:00
Evan Cheng 0beca53a29 Hide more details in tablegen generated MCRegisterInfo ctor function.
llvm-svn: 134027
2011-06-28 20:44:22 +00:00
Evan Cheng 1e210d08d8 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
llvm-svn: 134024
2011-06-28 20:07:07 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Evan Cheng 8d71a75777 More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
llvm-svn: 133944
2011-06-27 21:26:13 +00:00
Evan Cheng d9997acd14 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.

llvm-svn: 133922
2011-06-27 18:32:37 +00:00
Evan Cheng 247533179a Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782
2011-06-24 01:44:41 +00:00
Jakob Stoklund Olesen b68fee1e82 Delete unneeded allocation order override.
llvm-svn: 133331
2011-06-18 02:30:02 +00:00
Jakob Stoklund Olesen 99f35eab45 Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

llvm-svn: 133105
2011-06-15 23:28:14 +00:00
Jakob Stoklund Olesen 5750ca7089 Remove custom allocation order boilerplate that is no longer needed.
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781
2011-06-09 16:56:59 +00:00
Eric Christopher 0713a9d8fc Add a parameter to CCState so that it can access the MachineFunction.
No functional change.

Part of PR6965

llvm-svn: 132763
2011-06-08 23:55:35 +00:00
Jakob Stoklund Olesen e1c6d3acb4 Blackfin always uses a reserved call frame.
Materializing the stack pointer update before a call requires a scratch
register that may not be available.

llvm-svn: 132601
2011-06-03 22:45:18 +00:00
Jakob Stoklund Olesen aff1060207 Use TRI::has{Sub,Super}ClassEq() where possible.
No functional change.

llvm-svn: 132455
2011-06-02 05:43:46 +00:00
Rafael Espindola 08600bcf65 Use the dwarf->llvm mapping to print register names in the cfi
directives.

Fixes PR9826.

llvm-svn: 132317
2011-05-30 20:20:15 +00:00
Eli Friedman 2518f8376d Make the logic for determining function alignment more explicit. No functionality change.
llvm-svn: 131012
2011-05-06 20:34:06 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Owen Anderson b2c80da4ae Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
llvm-svn: 126518
2011-02-25 21:41:48 +00:00
Oscar Fuentes ba1186c23e Use explicit add_subdirectory's for LLVM target sublibraries instead
of testing for its presence at cmake time.

This way the build automatically regenerates the makefiles when a svn
update brings in a new sublibrary.

llvm-svn: 126068
2011-02-20 02:55:27 +00:00
Jakob Stoklund Olesen 4bc5e38960 Teach frame lowering to ignore debug values after the terminators.
llvm-svn: 123399
2011-01-13 21:28:52 +00:00
Anton Korobeynikov 441ae5b88c Update CMake stuff
llvm-svn: 123171
2011-01-10 12:39:23 +00:00
Anton Korobeynikov 2f93128109 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
llvm-svn: 123170
2011-01-10 12:39:04 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Chris Lattner 3e5fbd74ed rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
2010-12-21 02:38:05 +00:00
Anton Korobeynikov 7283b8d18c Move more PEI-related hooks to TFI
llvm-svn: 120229
2010-11-27 23:05:25 +00:00
Anton Korobeynikov 0eecf5d201 Move hasFP() and few related hooks to TargetFrameInfo.
llvm-svn: 119740
2010-11-18 21:19:35 +00:00
Anton Korobeynikov 51d2e9ca29 Attempt to unbreak cmake-based builds
llvm-svn: 119098
2010-11-15 00:48:12 +00:00
Anton Korobeynikov f7183edb59 First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
llvm-svn: 119097
2010-11-15 00:06:54 +00:00
Chris Lattner 66031ed839 move all the target's asmprinters into the main target. The piece
that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.

llvm-svn: 119056
2010-11-14 18:43:56 +00:00
John Thompson e8360b7182 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
llvm-svn: 117667
2010-10-29 17:29:13 +00:00