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306 Commits

Author SHA1 Message Date
Tom Stellard ed882c2f1b R600/SI: Add a calling convention for compute shaders 
llvm-svn: 183137
 2013-06-03 17:40:11 +00:00
Tom Stellard 046039e81b R600/SI: Custom lower i64 sign_extend 
llvm-svn: 183136
 2013-06-03 17:40:03 +00:00
Tom Stellard 0518ff89ba R600/SI: Adjust some instructions' out register class after ISel 
This is necessary to avoid generating VGPR to SGPR copies in some
cases.

llvm-svn: 183135
 2013-06-03 17:39:58 +00:00
Tom Stellard bad1f59212 R600/SI: Handle REG_SEQUENCE in fitsRegClass() 
llvm-svn: 183134
 2013-06-03 17:39:54 +00:00
Tom Stellard b5a97004fb R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands() 
llvm-svn: 183133
 2013-06-03 17:39:50 +00:00
Tom Stellard 2183b70523 R600/SI: Fixup CopyToReg register class in PostprocessISelDAG() 
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR.  This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else.  The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.

llvm-svn: 183132
 2013-06-03 17:39:46 +00:00
Tom Stellard 07a10a3d3f R600/SI: Add support for global loads 
llvm-svn: 183131
 2013-06-03 17:39:43 +00:00
Tom Stellard 556d9aa841 R600/SI: Rework MUBUF store instructions 
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

llvm-svn: 183130
 2013-06-03 17:39:37 +00:00
Vincent Lejeune 91a942b93e R600: 3 op instructions have no write bit but the result are store in PV 
llvm-svn: 183111
 2013-06-03 15:56:12 +00:00
Vincent Lejeune eabf83e0a2 R600: CALL_FS consumes a stack size entry 
llvm-svn: 183108
 2013-06-03 15:44:42 +00:00
Vincent Lejeune f83df1f1cb R600: use capital letter for PV channel 
llvm-svn: 183107
 2013-06-03 15:44:35 +00:00
Vincent Lejeune a09873dda7 R600: Constraints input regs of interp_xy,_zw 
llvm-svn: 183106
 2013-06-03 15:44:16 +00:00
Ahmed Bougacha b1a4d9da3b Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061
 2013-05-31 23:45:26 +00:00
Patrik Hagglund ae8faf2e9a Temporary fix to get rid of gcc warning. 
llvm-svn: 182832
 2013-05-29 07:32:08 +00:00
Andrew Trick ef9de2a739 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703
 2013-05-25 02:42:55 +00:00
Tom Stellard 1b086cbcb8 R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg 
Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182600
 2013-05-23 18:26:42 +00:00
Benjamin Kramer d78bb468bd Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 
llvm-svn: 182594
 2013-05-23 17:10:37 +00:00
Benjamin Kramer 635e368e33 R600: Hide symbols of implementation details. 
Also removes an unused function.

llvm-svn: 182587
 2013-05-23 15:43:05 +00:00
Aaron Ballman 15f193a1a3 Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style. 
llvm-svn: 182585
 2013-05-23 14:55:00 +00:00
Rafael Espindola 00345fa97b Fix 32 bit build in c++11 mode. 
The error was:
error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing]
        MI.getOperand(6).getImm() & 0x1F,

llvm-svn: 182584
 2013-05-23 13:22:30 +00:00
Rafael Espindola 39aca620db Fix a leak on the r600 backend. 
This should bring the valgrind bot back to life.

llvm-svn: 182561
 2013-05-23 03:31:47 +00:00
Rafael Espindola bd6847fbea clang-format this file. 
llvm-svn: 182560
 2013-05-23 03:28:39 +00:00
Rafael Espindola e3d83fb8c3 Fix use after free (pr16103). 
llvm-svn: 182482
 2013-05-22 15:31:11 +00:00
Rafael Espindola ebd8e38849 Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER. 
Fixes a use of uninitialized memory found by asan and valgind.

llvm-svn: 182480
 2013-05-22 14:57:42 +00:00
NAKAMURA Takumi 4f328e1c2f R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. Specify namespaces explicitly here. 
MSC is confused about "memcpy" between <cstring> and llvm::Intrinsic::memcpy, when llvm::Intrinsic were exposed.

llvm-svn: 182452
 2013-05-22 06:37:31 +00:00
NAKAMURA Takumi 18ca09c1cc R600: Whitespace and untabify. 
llvm-svn: 182451
 2013-05-22 06:37:25 +00:00
Owen Anderson 616852848a Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend. 
llvm-svn: 182450
 2013-05-22 06:36:09 +00:00
Rafael Espindola 21ea01d132 Attempt to fix the mingw32 bot. 
This should hopefully fix
http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32

llvm-svn: 182446
 2013-05-22 02:30:47 +00:00
Rafael Espindola 525cf28652 s/u_int32_t/uint32_t/ 
llvm-svn: 182444
 2013-05-22 01:36:19 +00:00
Rafael Espindola f568827654 Fix warning in non-assert build. 
llvm-svn: 182443
 2013-05-22 01:29:38 +00:00
Benjamin Kramer 927ca942ce R600: Fix bug detected by GCC warning. 
R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

llvm-svn: 182293
 2013-05-20 15:58:43 +00:00
Tom Stellard f1ee716446 R600/SI: Use a multiclass for MUBUF_Load_Helper 
This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182288
 2013-05-20 15:02:31 +00:00
Tom Stellard b8458f88d6 R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182287
 2013-05-20 15:02:28 +00:00
Tom Stellard d2eebf001e R600/SI: Add pattern for rotr 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
 2013-05-20 15:02:24 +00:00
Tom Stellard 5643c4ac72 R600: Swap the legality of rotl and rotr 
The hardware supports rotr and not rotl.

llvm-svn: 182285
 2013-05-20 15:02:19 +00:00
Tom Stellard 1cfd7a50bb R600/SI: Add patterns for 64-bit shift operations 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284
 2013-05-20 15:02:12 +00:00
Tom Stellard 459a79a81c R600/SI: Use the same names for VOP3 operands and encoding fields 
This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182283
 2013-05-20 15:02:08 +00:00
Tom Stellard b35efba4d9 R600/SI: Make fitsRegClass() operands const 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182282
 2013-05-20 15:02:01 +00:00
Matt Arsenault 75865923c9 Add LLVMContext argument to getSetCCResultType 
llvm-svn: 182180
 2013-05-18 00:21:46 +00:00
Rafael Espindola 5986ce0e5d Fix the build in c++11 mode. 
The errors were:

non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list

and

non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list

llvm-svn: 182168
 2013-05-17 22:45:52 +00:00
Vincent Lejeune d3fcb5016c R600: Lower int_load_input to copyFromReg instead of Register node 
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

llvm-svn: 182130
 2013-05-17 16:51:06 +00:00
Vincent Lejeune 3d5118ca40 R600: Use bottom up scheduling algorithm 
llvm-svn: 182129
 2013-05-17 16:50:56 +00:00
Vincent Lejeune 4c81d4da6f R600: Use depth first scheduling algorithm 
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)

llvm-svn: 182128
 2013-05-17 16:50:44 +00:00
Vincent Lejeune e958c8e0d8 R600: Replace big texture opcode switch in scheduler by usesTC/usesVC 
llvm-svn: 182127
 2013-05-17 16:50:37 +00:00
Vincent Lejeune 519f21eed3 R600: Relax some vector constraints on Dot4. 
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

llvm-svn: 182126
 2013-05-17 16:50:32 +00:00
Vincent Lejeune d3eed66e8c R600: Improve texture handling 
llvm-svn: 182125
 2013-05-17 16:50:20 +00:00
Vincent Lejeune 4ebef18ab5 R600: Rename 128 bit registers. 
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.

llvm-svn: 182124
 2013-05-17 16:50:09 +00:00
Vincent Lejeune 0fca91d52e R600: Some factorization 
llvm-svn: 182123
 2013-05-17 16:50:02 +00:00
Vincent Lejeune f9f4e1e7db R600: Factorize Fetch size limit inside AMDGPUSubTarget 
llvm-svn: 182122
 2013-05-17 16:49:55 +00:00
Vincent Lejeune 709e01688d R600: prettier dump of clamp 
llvm-svn: 182121
 2013-05-17 16:49:49 +00:00